Inter-gate film merging WAT test structure and detection method

Abstract

The present invention discloses a gate-to-gate thin film merging WAT test structure, the main structure of which is a group of chain resistance structures of active area-contact hole-upper metal, each active area has a group of symmetrical gates, the spacing of which is the minimum allowable spacing of the design rules, and half of the gate and the active area outside the gate are covered by a silicide barrier layer to prevent them from forming low-resistance silicide. During the test, by testing the resistance of the chain structure, it can be judged whether the wafer product has the problem of gate-to-gate thin film merging during the entire process, which is convenient and accurate. The present invention also discloses a detection method using the gate-to-gate thin film merging WAT test structure.

Description

Technical Field

[0001] The present invention relates to semiconductor detection technology, and in particular to a POLY SPACERMERGE WAT (Wafer Acceptance Test) test structure (testkey) and a detection method. Background Art

[0002] With the development of the times, chips have become a "necessity" in global life. With the advancement of chip technology, people's lives are becoming more and more intelligent, various travel is becoming more and more convenient, and the amount of information available every day is also increasing.

[0003] Today, as the requirements for integrated circuit design and manufacturing become increasingly higher, the characteristic dimensions of MOS tubes are becoming smaller and smaller, and many processes are even constantly pushing the limits of the technology.

[0004] One of the important steps to reduce the feature size is to reduce the line width of the polysilicon gate (metal gate), and then the spacing between the gates will also be reduced to achieve the goal of reducing the overall size of the device. After the gate is formed, SAPCER1 / SPACER2 (sidewall 1 / sidewall 2) and hard mask films covering many processes such as SMT (:stress memorization technique, stress memory technology) / SiGe will need to be grown. When the gate spacing becomes extremely small, the film will merge (MERGE) between the gate spacing, such as Figure 1 As shown in the figure, the thickness of the merged film will far exceed the process window for removing the film later, which will eventually lead to the failure to remove the film that should be removed in that area, and block the formation of low-resistance silicide.

[0005] Common defect detection (defect scan) has low sensitivity and low sample rate, so we need to find more effective and comprehensive detection methods.

[0006] WAT (Wafer Acceptance Test) is an important station in wafer manufacturing. It is used to detect (also called inspection) whether the electrical performance of various devices on the manufactured wafers meets the specification requirements. If some important parameters do not meet the requirements, the wafer will be scrapped and will not enter the next stage.

[0007] The test structure on the wafer used to collect WAT data is called a WAT ​​test structure (WAT testkey). Through the combination of these test structures and the analysis of the test results, basically every process of wafer manufacturing can be monitored. The WAT test structure is not designed inside the actual product chip, because the design inside the chip will occupy additional chip area, and the additional chip area will increase the cost of the chip. The WAT test structure is between PADs, and many different test structures form a group of test modules. The chip foundry will define a name for each group of test modules, and each wafer will contain many such different WAT test modules. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a WAT ​​test structure and detection method for gate film merging. By testing the resistance of the chain structure, it can be determined whether the problem of gate film merging occurs in the entire process of the wafer product, which is convenient and accurate.

[0009] In order to solve the above technical problems, the present invention provides a WAT ​​test structure for combining a thin film between detection gates, which forms a low-voltage NMOS half region and a low-voltage PMOS half region on a wafer;

[0010] The low voltage NMOS half region is used to form a plurality of NMOS tubes;

[0011] The low voltage PMOS half region is used to form a plurality of PMOS tubes;

[0012] Shallow trench isolation is formed between each NMOS tube and PMOS tube;

[0013] For each NMOS tube and PMOS tube, two gates are arranged symmetrically in the active area, and side walls are formed on the left and right sides of each gate. The left and right spacing between gates is the minimum design rule.

[0014] A silicide barrier layer is covered on the active area on the left side of the middle of the left gate and the shallow trench isolation, and a silicide barrier layer is covered on the active area on the right side of the middle of the right gate and the shallow trench isolation;

[0015] Forming low-resistance silicide on the active area between adjacent sidewalls of two gate sections arranged symmetrically on the left and right;

[0016] A contact hole for connecting with an upper metal layer is formed in the active region beyond the upper and lower ends of the gate and through two gate symmetry axes arranged symmetrically on the left and right sides;

[0017] The contact holes of each NMOS tube in the low-voltage NMOS half area are connected in a chain-like manner through metal in sequence from beginning to end;

[0018] The contact holes of each PMOS tube in the low-voltage PMOS half area are connected in a chain-like manner through metal in sequence;

[0019] The lower contact hole of the tail end NMOS tube of the low voltage NMOS half region is connected to the lower contact hole of the head end PMOS tube of the low voltage PMOS half region through metal;

[0020] The upper contact hole metal of the head end NMOS tube of the low voltage NMOS half region is connected to the first pad;

[0021] The upper contact hole metal of the tail end PMOS tube of the low voltage PMOS half region is connected to the second bonding pad.

[0022] Preferably, the inter-gate film combined with the WAT test structure is formed on a dicing street of a wafer.

[0023] Preferably, the low-resistance silicide is nickel silicon.

[0024] Preferably, the lower contact hole of the tail end NMOS tube of the low voltage NMOS half region and the lower contact hole of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad.

[0025] In order to solve the above technical problems, the present invention provides a method for inspecting wafer products by using the above-mentioned inter-gate film merging WAT test structure, which measures the resistance value of the low-resistance silicide between the first pad and the second pad. If the resistance value of the low-resistance silicide is greater than the first set resistance value, the problem of inter-gate film merging occurs in the entire process of the wafer product. Otherwise, the problem of inter-gate film merging does not occur in the entire process of the wafer product.

[0026] Preferably, the lower contact hole of the tail end NMOS tube of the low voltage NMOS half region and the lower contact hole of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad;

[0027] Measuring the resistance value of the low-resistance silicide between the first pad and the third pad, if the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of thin film merging between NMOS tube gates occurs in the entire process of the wafer product, otherwise the problem of thin film merging between NMOS tube gates does not occur in the entire process of the wafer product;

[0028] The second set resistance value is less than or equal to the first set resistance value.

[0029] Preferably, the lower contact hole of the tail end NMOS tube of the low voltage NMOS half region and the lower contact hole of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad;

[0030] Measuring the resistance value of the low-resistance silicide between the second pad and the third pad, if the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of thin film merging between the gates of the PMOS tube occurs in the entire process of the wafer product, otherwise the problem of thin film merging between the gates of the PMOS tube does not occur in the entire process of the wafer product;

[0031] The second set resistance value is less than or equal to the first set resistance value.

[0032] The WAT test structure and detection method for gate-to-gate film merging of the present invention has a main structure of a group of chain resistor structures of AA-CT-M1, and each AA (Active Area) has a group of symmetrical gates (PO) with a spacing that is the minimum allowable spacing of the design rules, and half of the gate (PO) and the AA part outside the gate will be covered by SAB (silicide blocking layer) to prevent it from forming low-resistance silicide. During the test, by testing the resistance of the chain structure, it can be determined whether the problem of gate-to-gate film merging occurs in the wafer product during the entire process, which is convenient and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a schematic diagram of the merging of inter-gate thin films;

[0035] Figure 2 It is a schematic diagram of an embodiment of the inter-gate film combined WAT test structure of the present invention;

[0036] Figure 3 It is a schematic diagram of a low-resistance silicide normally formed on the active region of an embodiment of the inter-gate film combined WAT test structure of the present invention;

[0037] Figure 4 It is a schematic diagram of an embodiment of the inter-gate film combined WAT test structure of the present invention, in which a low-resistance silicide region cannot be normally formed on the active region. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Embodiment 1

[0040] like Figure 3As shown, the POLY SPACER MERGE WAT (Wafer Acceptance Test) test structure (testkey) includes a low voltage NMOS half area (LVN AREA) and a low voltage PMOS half area (LVPAREA);

[0041] The low voltage NMOS half region is used to form a plurality of NMOS tubes;

[0042] The low voltage PMOS half region is used to form a plurality of PMOS tubes;

[0043] STI (shallow trench isolation) is formed between each NMOS tube and PMOS tube;

[0044] For each NMOS tube and PMOS tube, two sections of PO (gate) are arranged symmetrically on the left and right sides of AA (Active Area), and sidewalls (SPACER) are formed on the left and right sides of each section of PO (gate). The left and right spacing (SPACE) between PO (gate) and PO (gate) is the minimum design rule;

[0045] Cover the AA (Active Area) and STI (shallow trench isolation) on the left side of the left PO (gate) with SAB (silicide barrier layer), and cover the AA (Active Area) and STI (shallow trench isolation) on the right side of the right PO (gate) with SAB (silicide barrier layer);

[0046] A low-resistance silicide is formed on the AA (Active Area) between the adjacent sidewalls of the two PO (gate) sections arranged symmetrically on the left and right;

[0047] A CT (contact hole) for connecting to the upper metal layer (M1) is formed at a position where AA (Active Area) exceeds the upper and lower ends of PO (gate) and passes through the symmetry axes of two PO (gate) sections arranged symmetrically on the left and right sides;

[0048] The CT (contact holes) of each NMOS tube in the low-voltage NMOS half area are connected in a chain-like manner by metal in sequence from head to tail;

[0049] The CTs (contact holes) of the PMOS tubes in the low-voltage PMOS half-area are connected in a chain-like manner from head to tail through metal;

[0050] The lower CT (contact hole) of the tail end NMOS tube of the low voltage NMOS half region is connected to the lower CT (contact hole) of the head end PMOS tube of the low voltage PMOS half region through metal;

[0051] The upper CT (contact hole) metal of the head end NMOS tube of the low voltage NMOS half region is connected to the first pad PAD1;

[0052] The upper CT (contact hole) metal of the tail end PMOS tube of the low voltage PMOS half region is connected to the second pad PAD2.

[0053] Preferably, the inter-gate film and the WAT test structure are combined to form scribe lines between dies on a wafer.

[0054] Preferably, the low-resistance silicide is nickel silicon (NISI), titanium silicide (TiSi2) or cobalt silicide (CoSi2).

[0055] Preferably, the lower CT (contact hole) of the tail end NMOS tube of the low voltage NMOS half region and the lower CT (contact hole) of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad PAD3.

[0056] The WAT test structure for the gate film merging of the first embodiment has a group of chain resistor structures of AA-CT-M1 as the main structure. There is a group of symmetrical gates (PO) on each AA (Active Area), and the spacing is the minimum allowable spacing of the design rules. Half of the gate (PO) and the AA part outside the gate will be covered by SAB (silicide barrier layer) to prevent it from forming low-resistance silicide. During the test, by testing the resistance of the chain structure, it can be determined whether the wafer product has the problem of gate film merging during the entire process. The WAT test structure can be used in all processes where the gate (PO) spacing is small and there is a concern about the problem of gate film merging (SPACER MERGE).

[0057] Embodiment 2

[0058] The method for inspecting the wafer product by using the WAT test structure of the first embodiment to measure the resistance value of the low-resistance silicide between the first pad PAD1 and the second pad PAD2, if the resistance value of the low-resistance silicide is greater than the first set resistance value, the problem of the SPACER MERGE occurs in the whole process of the wafer product (such as Figure 4 Otherwise, there is no problem of spacer merging in the entire process of the wafer product (as shown in Figure 3 shown).

[0059] Preferably, the lower CT (contact hole) of the tail end NMOS tube of the low voltage NMOS half region and the lower CT (contact hole) of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad PAD3;

[0060] The resistance value of the low-resistance silicide between the first pad PAD1 and the third pad PAD3 is measured. If the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of NMOS tube gate thin film merging (SPACER MERGE) occurs in the entire process of the wafer product. Otherwise, the problem of NMOS tube gate thin film merging (SPACER MERGE) does not occur in the entire process of the wafer product.

[0061] The second set resistance value is less than or equal to the first set resistance value.

[0062] Preferably, the lower CT (contact hole) of the tail end NMOS tube of the low voltage NMOS half region and the lower CT (contact hole) of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad PAD3;

[0063] Measure the resistance value of the low-resistance silicide between the second pad PAD2 and the third pad PAD3. If the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of PMOS tube gate thin film merging (SPACER MERGE) occurs in the entire process of the wafer product. Otherwise, the problem of PMOS tube gate thin film merging (SPACER MERGE) does not occur in the entire process of the wafer product.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A gate-to-gate thin film merged WAT test structure, characterized in that: forming a low voltage NMOS half region and a low voltage PMOS half region on the wafer; The low voltage NMOS half region is used to form a plurality of NMOS tubes; The low voltage PMOS half region is used to form a plurality of PMOS tubes; Shallow trench isolation is formed between each NMOS tube and PMOS tube; For each NMOS tube and PMOS tube, two gates are arranged symmetrically in the active area, and side walls are formed on the left and right sides of each gate. The left and right spacing between gates is the minimum design rule. A silicide barrier layer is covered on the active area on the left side of the middle of the left gate and the shallow trench isolation, and a silicide barrier layer is covered on the active area on the right side of the middle of the right gate and the shallow trench isolation; Forming low-resistance silicide on the active area between adjacent sidewalls of two gate sections arranged symmetrically on the left and right; A contact hole for connecting with an upper metal layer is formed in the active region beyond the upper and lower ends of the gate and through two gate symmetry axes arranged symmetrically on the left and right sides; The contact holes of each NMOS tube in the low-voltage NMOS half area are connected in a chain-like manner through metal in sequence from beginning to end; The contact holes of each PMOS tube in the low-voltage PMOS half area are connected in a chain-like manner through metal in sequence; The lower contact hole of the tail end NMOS tube of the low voltage NMOS half region is connected to the lower contact hole of the head end PMOS tube of the low voltage PMOS half region through metal; The upper contact hole metal of the head end NMOS tube of the low voltage NMOS half region is connected to the first pad; The upper contact hole metal of the tail end PMOS tube of the low voltage PMOS half region is connected to the second bonding pad.

2. The inter-gate thin film merged WAT test structure according to claim 1, characterized in that: The inter-gate film and the WAT test structure are formed on the dicing street of the wafer.

3. The inter-gate thin film merged WAT test structure according to claim 1, characterized in that: The low-resistance silicide is nickel silicon.

4. The inter-gate thin film merged WAT test structure according to claim 1, characterized in that: The lower contact hole of the tail end NMOS tube of the low voltage NMOS half region and the lower contact hole of the head end PMOS tube of the low voltage PMOS half region are both connected to the third pad.

5. A method for inspecting wafer products using the inter-film combined WAT test structure of claim 1, characterized in that: The resistance value of the low-resistance silicide between the first pad and the second pad is measured. If the resistance value of the low-resistance silicide is greater than the first set resistance value, the problem of inter-gate film merging occurs in the entire process of the wafer product. Otherwise, the problem of inter-gate film merging does not occur in the entire process of the wafer product.

6. The method according to claim 5, characterized in that The lower contact hole of the tail end NMOS tube of the low voltage NMOS half area and the lower contact hole of the head end PMOS tube of the low voltage PMOS half area are both connected to the third pad; Measuring the resistance value of the low-resistance silicide between the first pad and the third pad, if the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of thin film merging between NMOS tube gates occurs in the entire process of the wafer product, otherwise the problem of thin film merging between NMOS tube gates does not occur in the entire process of the wafer product; The second set resistance value is less than or equal to the first set resistance value.

7. The method according to claim 5, characterized in that The lower contact hole of the tail end NMOS tube of the low voltage NMOS half area and the lower contact hole of the head end PMOS tube of the low voltage PMOS half area are both connected to the third pad; Measuring the resistance value of the low-resistance silicide between the second pad and the third pad, if the resistance value of the low-resistance silicide is greater than the second set resistance value, the problem of thin film merging between the gates of the PMOS tube occurs in the entire process of the wafer product, otherwise the problem of thin film merging between the gates of the PMOS tube does not occur in the entire process of the wafer product; The second set resistance value is less than or equal to the first set resistance value.

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