Continuous bit-wise ordered binary-weighted multiplication accumulator

Abstract

Various arrangements for performing a continuous vector matrix multiplication can include performing a first vector matrix multiplication operation sequentially for each bit sequence of values in an input vector. The first vector matrix multiplication operation for each bit sequence can generate an analog output. For each analog output generated by the vector matrix multiplication operation, the analog output can be converted to one or more digital bit values, and the one or more digital bit values can be sent to a second vector matrix multiplication operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 907,419, filed September 27, 2019, and to U.S. Patent Application No. 16 / 688,782, filed November 19, 2019, both of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This disclosure generally relates to vector-matrix multiplication circuits for multiplier-accumulator operations. More particularly, it relates to circuits for sequentially performing vector-matrix multiplication operations to continuously generate digital outputs based on analog results. Background Technology

[0004] Vector-matrix multiplication can be defined as the sum of the products of a vector and a matrix. Specifically, Equation 1 can be used to define a vector-matrix multiplication operation in which the products are summed.

[0005] Equation 1

[0006] In equation 1, X i It is an input vector consisting of values ​​(which can be represented using binary bits in an electronic environment), while W ij This represents the matrix weights. Y is the output vector obtained by summing the product vectors. This function is used in various signal processing, image processing, and artificial intelligence applications, such as in the use of neural networks.

[0007] Performing this equation digitally consumes significant processing resources and / or energy. Known analog or hybrid digital-analog components may require a relatively large number of clock cycles and / or a relatively large physical area for implementation. Summary of the Invention

[0008] In some specific implementations, a method for performing a successive binary weighted digital-to-analog conversion may include: sequentially performing a first vector matrix multiplication operation on each bit-order of values ​​in an input vector, wherein the first vector matrix multiplication operation on each bit-order generates an analog output. The method may also include: for each analog output generated by the vector matrix multiplication operation, converting the analog output into one or more digital bit values, and sending the one or more digital bit values ​​to a second vector matrix multiplication operation.

[0009] In some specific embodiments, the vector matrix multiplier circuit may include multiple digital inputs, each of which can receive a binary-encoded input value of an input vector. The circuit may also include a vector matrix multiplier circuit that performs binary-encoded vector multiplication on a single bit sequence at a time using the binary-encoded input values. The circuit may further include a sequential binary-weighted analog-to-digital converter that sequentially receives analog outputs from the vector matrix multiplier circuit and sequentially converts each of the analog outputs into one or more digital bit values.

[0010] In some specific embodiments, the apparatus for performing vector-matrix multiplication may include means for receiving a plurality of digital inputs, wherein each digital input may receive an input value encoded in binary form of an input vector. The apparatus may also include means for sequentially performing vector-matrix multiplication on each bit sequence of the plurality of input vector values, wherein the vector-matrix multiplication for each bit sequence generates an analog output. The apparatus may further include means for converting each analog output into one or more digital bit values.

[0011] In any specific implementation, any or all of the following features may be included in any combination, and there are no limitations. The first vector-matrix multiplication operation may begin with the most significant bit (MSB) of each value in the input vector and may end with the least significant bit (LSB) of each value in the vector. Converting the analog output to one or more digital bit values ​​may include: comparing the analog output to a reference signal, wherein a first digital bit value among the one or more digital bit values ​​may represent logic 1 when the analog output is greater than the reference signal, and a first digital bit value may represent logic 0 when the analog output is less than the reference signal. Converting the analog output to one or more digital bit values ​​may further include: adjusting the reference signal when the first digital bit value represents logic 1. The analog output may correspond to the MSB of each value in the input vector, and the one or more digital bit values ​​may include the first digital bit value without a carry-over bit. Converting the analog output to one or more digital bit values ​​may further include: after adjusting the reference signal, comparing the analog output to the reference signal, wherein when the analog output is greater than the reference signal, a second digital bit value of the one or more digital bit values ​​may represent logic 1, and when the analog output is less than the reference signal, the second digital bit value may represent logic 0. A first digital bit value may represent the value corresponding to the current analog output, and a second digital bit value may represent the carry value to be added to the value corresponding to the previous analog output. Converting the analog output to one or more digital bit values ​​may further include: holding the reference signal when the first digital bit value represents logic 0. Converting the analog output to one or more digital bit values ​​may further include: after adjusting the reference signal, comparing the analog output to the reference signal, wherein when the analog output is greater than the reference signal, a second digital bit value of the one or more digital bit values ​​may represent logic 1, and when the analog output is less than the reference signal, the second digital bit value may represent logic 0. A two-cycle delay may exist between converting the analog output to one or more digital bit values ​​and sending the one or more digital bit values ​​to the second vector matrix multiplication operation. The continuous binary weighted analog-to-digital converter may also include a charge integration circuit with capacitors, where each analog output stores charge on the capacitors. Vector matrix multiplier circuits can also transmit an indication of the current bit order. Vector matrix multiplier circuits may also include a multiplexer that sends one or more digital bit values ​​to one of a plurality of registers, where the indication of the current bit order controls the multiplexer. A sequential binary weighted analog-to-digital converter may also include a plurality of binary weighting switches and capacitors, each of which stores a different analog output from the analog output.The circuit / device may further include a sequential binary-weighted analog-to-digital converter that sequentially receives analog outputs from means for sequentially performing vector-matrix multiplication operations and sequentially converts each of the analog outputs into at least one digital bit value. The device may also include means for converting multiple digital inputs into multiple analog signals, which are input to means for sequentially performing vector-matrix multiplication operations. The device may also include a reference voltage for comparing the analog outputs. The device may also include means for comparing the reference voltage with the analog outputs. Attached Figure Description

[0012] A further understanding of the nature and advantages of various specific embodiments can be achieved by referring to the following accompanying drawings. In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, components of the same type can be distinguished by adding a dash after the reference numeral and a second reference numeral to differentiate similar parts. If only the first reference numeral is used in the description, its description is applicable to any similar parts having the same first reference numeral, regardless of what the second reference numeral is.

[0013] Figure 1 A specific implementation of a vector matrix multiplier circuit is shown, in which analog components are used to perform vector multiplication on bit-ordered binary values.

[0014] Figure 2 A specific implementation of an analog vector matrix multiplier is shown.

[0015] Figure 3 A specific implementation of the analog summing circuit is shown.

[0016] Figure 4 A specific implementation of a method for performing vector-matrix multiplication is shown.

[0017] Figure 5 A specific implementation of a circuit in which vector multiplication is performed using analog components on binary encoded inputs is shown.

[0018] Figure 6 This illustrates how, according to some specific implementations, the input stream of individual bits is processed to produce a sequential output bit stream.

[0019] Figure 7 A specific process for generating a continuous binary weighted digital output is shown according to some specific implementations.

[0020] Figure 8 A specific process for generating a continuous binary weighted digital output is shown according to some specific implementations.

[0021] Figure 9Alternative processes for generating consecutive binary weighted digital outputs are shown according to some specific implementations.

[0022] Figure 10 A pipeline of sequential MAC operations is illustrated according to some specific embodiments, which can be sequentially layered and executed as bits are processed individually between each layer.

[0023] Figure 11 A flowchart is shown of a method for performing sequential binary weighted digital-to-analog conversion according to some specific embodiments. Detailed Implementation

[0024] Compared to known analog implementations, the implementation detailed herein allows for multiplier accumulator (MAC) operations to be performed in a shorter time frame (e.g., fewer clock cycles) without requiring decoding of the digital input signal. Instead, an input vector in binary-coded (or “bit-ordered”) value form can be received. Such values ​​are typically arranged from LSB to MSB or MSB to LSB (e.g., “1110” represents the value 14) and can be multiplied in the analog domain and then added in the analog or digital domain. The arrangement described in detail herein performs the analog conversion directly over the binary-coded values ​​and does not require converting the input vector into a series of pulses (e.g., fourteen pulses represent the value 14). Therefore, computations can be performed faster than known analog devices. More specifically, the number of operation cycles required to perform vector-matrix multiplication can be reduced. The additional two cycles indicated in the denominator in this equation can vary depending on the implementation. For example, the specific implementation detailed herein can perform vector-matrix multiplication on an 8-bit input vector, which can be accelerated by 25.6 times compared to known analog MAC designs.

[0025] Furthermore, the arrangement detailed in this paper saves significant space compared to known analog MAC designs. By using a one-bit digital-to-analog converter (DAC), less area is required compared to using multi-bit DACs that convert the received binary values ​​in parallel. Specifically, multiple one-bit DACs can be used to convert multiple binary-coded input vectors in parallel into multiple binary-coded analog voltage values. For example, for a four-bit input vector, four clock cycles are required to output the binary-coded analog voltage value from a one-bit DAC (one cycle for the LSB, one cycle for the second LSB, one cycle for the second MSB, and one cycle for the MSB). The number of one-bit DACs depends on the number of input vectors (X in Equation 1). i ).

[0026] Matrix multiplication can be performed sequentially on each bit order of the input vector values. The parallel output of each one-bit DAC can be input to the weighting component of the vector matrix multiplier circuit. The vector matrix multiplier circuit can have a bitwise AND operation corresponding to Equation 1 with respect to X. i W of multiplication ij Various weighting components of a matrix. A vector matrix multiplier circuit can perform multiplication operations on each bit sequence of an input vector. Therefore, if the input vector contains a value of length four bits, the vector matrix multiplier circuit can perform multiplication operations sequentially on each of the four bit sequences in the time domain. The output from the vector matrix multiplier circuit can be a sequential signal (e.g., a signal with current or some electrical characteristic indicating the multiplication result) that is output to a summing circuit.

[0027] After matrix multiplication has been performed, a summing circuit can be used to perform bit-order weighted summation. The summing circuit can operate in either the analog or digital domain. It can receive signals from the vector-matrix multiplication circuit, store instructions for each matrix multiplication operation, weight the elements correctly, and perform the summation to determine the output value Y.

[0028] Figure 1 A specific implementation of circuit 100 is shown, in which vector multiplication is performed using analog components on binary-encoded inputs. Circuit 100 may include: a one-bit DAC 114, an analog vector-matrix multiplier 122, and a summing component 132. Circuit 100 can be understood as being divided into three parts. Part 110 receives a binary-encoded digital signal (representing the input vector) and converts the binary-encoded digital signal into a binary-encoded analog signal. Part 120 receives the binary-encoded analog signal and outputs a binary-encoded product indicating the multiplication between the binary-encoded analog signal and a predefined matrix (e.g., a weighted matrix). Part 130 performs bit-order weighted summation to sum the binary-encoded product, taking into account the bit-order weighting of the binary-encoded signal. Therefore, the correct bit order of each bit of the binary-encoded input signal is preserved, allowing the sum to be correctly determined. Part 130 can use analog components to efficiently sum the product output of part 120. Part 130 can also operate in the digital domain.

[0029] Specifically, in section 110, multiple digital input signals 112 can be received in parallel. Each digital input signal 112 represents a binary encoded value, and each digital input signal 112 can represent a vector X as shown in Equation 1. iThe binary bits of input signal 112 can be represented by voltage levels (e.g., high level = 1, low level = 0), pulses (e.g., one pulse = 1, no pulse = 0), or time (e.g., a pulse of a first duration represents 1, a pulse of a second duration represents 0). As shown, four digital input signals (112-1, 112-2, 112-3, and 112-4) can be received in parallel. Each of these input signals can receive a separate value of the input vector. In other specific embodiments, it is possible to receive values ​​higher than... Figure 1 The diagram illustrates a smaller or more number of digital input signals. Each digital input signal 112 can be binary-coded. Therefore, for each clock cycle of the digital portion of the circuit, bits for a specific bit order can be received as digital input signals 112. For example, if four-bit binary values ​​are input via each digital input signal 112, four clock cycles can be used for each bit of the binary value to be received and converted in parallel to the analog domain. The digital input signals 112 can be binary-coded such that the bit order of each value is from least significant bit (LSB) to most significant bit (MSB), from MSB to LSB, or in any predetermined pattern.

[0030] Digital input signal 112 can be input to a single-bit DAC 114. Again, as shown, there are four single-bit DACs 114 (114-1, 114-2, 114-3, and 114-4). In other embodiments, fewer or more single-bit DACs 114 may be present. A single single-bit DAC may be present for each binary-encoded digital input signal 112. Each single-bit DAC 114 can output an analog signal indicating the received digital value. Therefore, binary-encoded analog signals 116 (116-1, 116-2, 116-3, and 116-4) can represent the analog-to-analog conversion of digital input signal 112.

[0031] In part 120, the analog vector matrix multiplier 122 can receive the binary-encoded analog signal 116. The analog vector matrix multiplier 122 can perform multiplication operations sequentially for each bit sequence of the input value (e.g., the first clock cycle for the LSB, the second clock cycle for the second LSB, the third clock cycle for the second MSB, etc.). Therefore, a separate multiplication operation can be performed for each bit sequence of the received binary-encoded analog signal 116. The following is in conjunction with... Figure 2 Further details are provided regarding possible specific implementations of the analog vector-matrix multiplier 122. The binary-encoded multiplication result signal 124 can be output to the summing unit 132.

[0032] The summing unit 132 can be understood as performing a bit-order weighted summation function. The summing unit 132 can correctly consider the bit order of the bits currently being evaluated by the analog vector matrix multiplier 122, store the output such that this bit order is considered, and perform the summation function. As detailed herein, bit-order weighting can be performed by the summing unit 132, thereby allowing the input value to retain its binary encoding when evaluated by the vector matrix multiplication circuit.

[0033] In a possible analog implementation of the summing circuit, charge accumulation and redistribution can be used to perform passive bit-order weighted summation. When a binary-encoded signal is received from the analog vector matrix multiplier 122, the summing unit 132 can use charge accumulation to accumulate a partial sum. Once all bit sequences (e.g., the four bit sequences of an input vector with four bit values) have been multiplied by the analog vector matrix multiplier 122, and the summing unit 132 has stored the partial sum (e.g., using charge accumulation), the charge can be redistributed and a voltage representing the final sum can be output. The following... Figure 3 Further details of possible specific implementations of a simulation implementation of the summing component 132 are given in the document.

[0034] Figure 2 A specific implementation 200 of an analog vector matrix multiplier is shown, whose evaluation has been converted into a single bit order of an analog input vector. Analog vector matrix multiplier 201 can represent... Figure 1 A specific implementation of the analog vector matrix multiplier 122 is described. However, it should be understood that specific implementation 200 is merely an example. Figure 2 In the binary vector input X i Will with W ij Multiplication. The analog vector matrix multiplier 201 may include multiple weighting elements (202, 204, 206, 208, 210, 212, 214, and 216). Each weighting element can receive a binary-encoded analog signal 116 from a single-bit DAC. In this example, the weighting element can output current based on the voltage of the received binary-encoded analog signal and the weighting value of a specific weighting element. For example, each weighting element can be implemented using various conductivities. By changing the conductivity of the weighting element, the current output amount, which depends on the input voltage, can be changed. For example, if the voltage is 1 V and the conductivity of the weighting module is 8 µS, an output of 8 µA can be obtained. This value can be further weighted based on the bit order of this value. Thus, for the least significant bit, the multiplier will be 1, for the second LSB, the multiplier will be 2, and so on. In some specific embodiments, the weighting used by each weighting element may be predetermined and fixed at manufacturing time. In other embodiments, the weighting of each weighting element is configurable after manufacturing and reconfigurable during use of embodiment 200.

[0035] The output of each weighting element (202, 204, 206, 208, 210, 212, 214, and 216) can be an electrical characteristic, such as current. The currents output from weighting elements connected to the same current output can be summed. Therefore, current output 220 can include the sum of the currents output by weighting elements 202, 204, 206, and 208; and current output 222 can include the sum of the currents output by weighting elements 210, 212, 214, and 216.

[0036] Each value of the input vector is evaluated one bit at a time (and the analog vector matrix multiplier 201 does not consider bit order). For example, for an input vector with four four-bit values, the MSB of each value can be evaluated first, then the second MSB of each value, then the second LSB, and finally the LSB of each value (thus corresponding to four clock cycles of binary encoded data output by a one-bit DAC). In other specific implementations, the evaluation can be performed from LSB to MSB or in any other predefined arbitrary order. As detailed later herein, the output of the analog vector matrix multiplier 201 can be weighted by a summing circuit to take into account the bit order of the bits being multiplied by the vector matrix multiplier.

[0037] The number of columns in the weighting element is arbitrary and can be based on the weighting matrix multiplied by the input vector. Therefore, although two columns exist in embodiment 200, fewer or more columns may exist in other elements. The number of rows in the weighting element can correspond to the number of values ​​present in the input vector. For example, Equation 2 can represent the current output of the analog vector matrix multiplier 201:

[0038] Equation 2

[0039] Continuing this example, current outputs (e.g., current outputs 220, 222) can be connected together to create a binary-encoded multiplication result signal 124. The summing unit 132 correctly weights, stores, and then sums each bit sequence to obtain the correct final sum.

[0040] Figure 3 A specific implementation 300 of the analog summing circuit is shown. It should be understood that various types of circuits can be used to accumulate and redistribute signals, which can be in the form of voltage, current, charge, or some other electrical characteristic. A key aspect of the analog summing circuit is that it applies the correct bit weighting to the received output of the analog vector matrix multiplier 201. For example, when the analog vector matrix multiplier 201 outputs an output corresponding to the second LSB of the input vector, the bit weighting applied by the analog summing circuit is twice that of the LSB and half that of the third LSB. Specific implementation 300 can be represented as... Figure 1 The summing component 132. Input 301 represents the binary-coded multiplication result signal 124 from the analog vector matrix multiplier. Input 301 is fed to the sense amplifier 310. The sense amplifier 310 outputs a voltage based on the current received at input 301. Specifically, embodiment 300 may use passive charge sharing and redistribution. Such an arrangement can help reduce power consumption and decrease the impact of thermal noise on the output value.

[0041] Specific implementation 300 includes a capacitor switch array 302. The capacitors can be bit-sequence weighted, meaning that the capacitance of each capacitor can be selected to passively store a charge weighted for a specific bit sequence. For example, to output a four-bit value, four capacitors are needed. Capacitor 316-1 can be used to store the charge corresponding to the LSB. Therefore, the capacitance of capacitor 316-1 can be C (where C is a unit value). Capacitor 316-2 can be used to store the charge corresponding to the second LSB. Therefore, the capacitance of capacitor 316-2 can be 2C (which represents twice the weight of C, thus corresponding to the second LSB in binary bit sequence). Capacitor 316-3 can be used to store the charge corresponding to the second MSB. Therefore, the capacitance of capacitor 316-3 can be 4C. Capacitor 316-4 can be used to store the charge corresponding to the MSB. Therefore, the capacitance of capacitor 316-4 can be 8C. Each capacitor has a capacitance corresponding to its bit sequence, which will be used to store the charge representing the output of the analog vector matrix multiplier. The capacitance can be calculated according to Equation 3, where C is the unit value and N is the number of bits in the input vector value.

[0042] Equation 3

[0043] Switch control logic 330 (which can be digital and connected to the same clock as part 110) controls whether switches 312, 314-1, 314-2, 314-3, 314-4, and 314-5 are open or closed. For simplicity, in Figure 3 The communication between switch control logic 330 and switches 312 and 314 is not shown. Switch control logic 330 may be a dedicated logic circuit or may be integrated as part of a processing system. Switch control logic 330 may initially close switches 314-1, 314-2, 314-3, 314-4, and 314-5, while opening switch 312. Switch 314-5 may be used as a reset to discharge the charge present in capacitors 316-1, 316-2, 316-3, and 316-4 to ground 320.

[0044] Switch control logic 330 can then control the switches such that a capacitor having capacitance associated with the current bit order being evaluated by analog vector matrix multiplier 122 is connected to the binary-encoded multiplication result signal 124. Switch control logic 330 can close switch 312 and open switches 314-2, 314-3, 314-4, and 314-5. Thus, only switch 314-1 can remain closed, thereby connecting capacitor 316-1 to the output of sense amplifier 310. During this clock cycle, analog vector matrix multiplier 122 can output the binary-encoded multiplication result signal corresponding to the LSB. For the next clock cycle, switch control logic 330 can keep switch 312 closed, open switch 314-1, and close switch 314-2. During this clock cycle, analog vector matrix multiplier 122 can output the binary-encoded multiplication result signal corresponding to the second LSB. Since the capacitance of capacitor 316-2 is twice that of capacitor 316-1, the correct bit weighting is passively applied to the stored charge. For the next clock cycle, switch control logic 330 can keep switch 312 closed, open switch 314-2, and close switch 314-3. During this clock cycle, analog vector matrix multiplier 122 can output the multiplication result signal corresponding to the binary code of the second MSB. Since the capacitance of capacitor 316-3 is twice that of capacitor 316-2, the correct bit weighting is passively applied to the stored charge. For the next clock cycle, switch control logic 330 can keep switch 312 closed, open switch 314-3, and close switch 314-4. During this clock cycle, analog vector matrix multiplier 122 can output the multiplication result signal corresponding to the binary code of the MSB. Since the capacitance of capacitor 316-4 is twice that of capacitor 316-3, the correct bit weighting is passively applied to the stored charge. In this stage, the switched capacitor array 302 stores the binary-coded multiplication result as charge in the bit-order weighted capacitors.

[0045] At this point, each of capacitors 316-1, 216-2, 316-3, and 316-4 stores a charge (Q) corresponding to a specific bit order of the capacitor. For a given bit order number N, the amount of charge stored on a particular capacitor can be defined by Equation 4.

[0046] Equation 4

[0047] Therefore, the charge is equal to the capacitance of the capacitor multiplied by the voltage output of the readout amplifier 310. As described in detail with respect to Equation 3, for each larger bit order, the capacitance increases by 2. N-1 times.

[0048] During the next clock cycle, switch control logic 330 can open switch 312, keep switch 314-5 open, and close switches 314-1, 314-2, 314-3, and 314-4. This step can be understood as a charge redistribution step. Since the amount of charge stored in each capacitor corresponds to its bit sequence, during the charge redistribution phase, the charge in each capacitor is distributed among capacitors 316-1, 316-2, 316-3, indicating the final sum. Once redistribution has occurred, the sum is represented as the voltage value on the top plate of capacitor 316, which is output via sum output 134. Equation 5 represents the voltage value output via sum output 134 based on the charge stored in each capacitor.

[0049] Equation 5

[0050] In Equation 5, the charge of each capacitor is based on the capacitor's associated positional order towards V. Out The correct weighting is contributed as the summation output 134, which represents the final weighted sum of the simulated vector-matrix multiplication.

[0051] In summary, when the input vector includes a four-bit value, the summation process may take six clock cycles until a valid sum of 134 is output. More specifically, the summation process may require a reset clock cycle, a reallocation clock cycle, and a clock cycle for each bit of the value.

[0052] although Figure 3 Four capacitors are shown, but it should be understood that this embodiment is for illustrative purposes only. The number of capacitors can be increased or decreased to accommodate different bit depths of the input vector values. In an alternative embodiment, a differential summing circuit can be implemented to eliminate common-mode interference from the summing output 134. Furthermore, other embodiments may use alternative passive analog components to store and sum charges to determine the summing output 134. In other embodiments, digital circuitry can be used to implement the summing circuit.

[0053] It can be used Figures 1 to 3 The system and circuits described in detail are used to perform various methods. Figure 4 A specific implementation of a method 400 for performing vector-matrix multiplication is shown. It can be used... Figures 1 to 3 The circuit or an alternative version of such a circuit is used to perform method 400. In other words, it should be understood that, such as Figures 2 to 3 Specific examples of those circuits are Figure 1 How the circuit is constructed and Figure 4 Examples of how this method is implemented. In some specific implementations, a digital summing circuit can be used.

[0054] In box 410, the bit order of a binary-coded signal can be converted into a binary-coded analog signal. To perform this function, multiple one-bit DACs can be used in parallel. Therefore, each DAC can convert a given bit-ordered digital signal into an analog signal in parallel. Each DAC can receive a binary-coded digital signal indicating a specific bit order of the input vector. Each vector can have N bits. Therefore, for a one-bit DAC, converting a binary-coded digital signal into an analog signal may require N clock cycles. For example, if the binary-coded digital signal is "10011", a one-bit DAC may require five clock cycles to output this binary-coded value (assuming the rightmost digit is an LSB, representing a value of 19). The analog voltage output by each one-bit DAC can depend on the power voltage supplied to each one-bit DAC.

[0055] At block 420, vector-matrix multiplication is performed sequentially for the bit order of the received binary-encoded analog signal. Block 420 can be performed for a specific bit order of the input vector received from a single-bit DAC. In other words, block 420 can be performed first for each LSB of the input vector value (then, during the next iteration of block 420, the second LSB can be evaluated). Typically, the first bit evaluated will be either the MSB or LSB of the input vector value. Vector-matrix multiplication can be performed by a method similar to... Figure 2 The specific implementation of the circuit in embodiment 200 is as follows. It should be understood that other specific implementations of the analog multiplication circuit are also possible. The vector matrix multiplier may include weighting components, each weighting component generating a weighted current quantity indicating the analog input value and the weighted product. Such current, or some other electrical characteristic, may be output to the summing circuit.

[0056] At block 430, for the given bit order in which the vector matrix multiplier performs its multiplication function at block 420, the output of the vector matrix multiplier (which can be in the form of current or voltage) can be stored with the correct bit order weights. The indication of the received signal is weighted according to the bit order of the bits evaluated and stored by the analog vector matrix multiplier. For example, if the evaluation performed by the analog vector matrix multiplier is from LSB to MSB, then when stored by the summing circuit, the weight of each subsequent bit can be doubled compared to the previous bit. As an example only, the sense amplifier can convert the current received from the analog vector matrix multiplier into a voltage. In some examples of the summing circuit, the voltage can be used to charge a specific capacitor (with a capacitance corresponding to the bit order performed at block 420). Thus, for example, when evaluating an LSB, the output of the analog matrix multiplier can be used to charge a capacitor with capacitance C; when evaluating a second LSB, the output of the analog matrix multiplier can be used to charge a capacitor with capacitance 2C, and so on.

[0057] At box 435, if no additional bit orders have been evaluated, method 400 can return to box 410 and execute for the next bit order of the input vector. Thus, each bit order is evaluated sequentially by an analog vector matrix multiplier, and the corresponding outputs are stored sequentially by a summing circuit, with weights corresponding to their bit orders. If multiplication has been performed for all bit orders at box 420 and the multiplication is stored at box 430, method 400 can proceed to box 440. Therefore, if each value of the input vector has four bits, boxes 420 and 430 are executed four times: once for each bit of the value.

[0058] At box 440, the summation can be determined, for example, by performing an accumulation. In some specific implementations, the summation is determined in the analog domain. Various bit-order weighted values ​​stored at box 430 can be added together. As an example only, if a switched capacitor array is used, the charge of the capacitors can be redistributed among the capacitors used to accumulate the total charge, and bit-weighted by the capacitance value of each capacitor corresponding to a specific bit order. For this purpose, the switches can be turned off to isolate the switched capacitor array, and all switches directly connected to the capacitors (e.g., Figure 3 Capacitors 314-1, 314-2, 314-3, and 314-4 are configured to be closed. The charge of each capacitor can be redistributed among the capacitor's domains. However, the total charge will remain constant, and the total charge will be correctly weighted according to bit order due to the capacitance differences between the capacitors. In other specific embodiments, as an alternative to using a capacitor array, another form of analog or digital circuitry can be used to determine the final sum using the correct bit order of each multiplication result.

[0059] In box 450, an indication of the summation is output. In some specific embodiments, the indication of the summation is output as an analog electrical characteristic, such as voltage amplitude. For example, as... Figure 3 As shown, the voltage on the top plate of the capacitor array can represent the sum of a vector matrix multiplication. This voltage can be measured and used to determine a value. For example, a separate circuit (e.g., an ADC) can use this output voltage to convert the voltage back to the digital domain.

[0060] Continuous MAC

[0061] In some implementations, the digitized MAC result can be used once the binary-weighted MAC operation is complete. These implementations can improve upon the above... Figures 1 to 4The bit-ordered binary weighted multiply-accumulator described herein provides a MAC-digitized output data available after eight MAC cycles and eight SAR ADC cycles for an eight-bit wide data input. These specific implementations make the MSB of the MAC data available at the end of the second cycle, and the remaining seven MAC output bits available at the end of each consecutive cycle. This reduces the latency of the MAC operation by a factor of eight.

[0062] In some implementations, the ADC can be integrated within the MAC. Successive MAC and ADC operations can be performed from the most significant bit to the least significant bit. At the end of each MAC cycle, a digitized MAC data bit can be available. Because data can be immediately fed into the next layer of the multiply-accumulate, the latency of the bit-ordered binary weighted multiply-accumulate is reduced. This shortens the latency of each layer. By directly feeding data to the next layer, eliminating the need to transfer data back and forth between the MAC array and the processor unit, power consumption is saved and latency is reduced.

[0063] In some implementations, MAC can be performed from the most significant bit (LSB) to the least significant bit (LSB). Therefore, the integrated ADC and MAC can also operate from LSB to LSB. A problem may arise involving residual analog data that wasn't digitized in higher bits, which could become carry bits in the LSB. This residual problem can be eliminated by outputting the LSB first, as carry-over bits should not be added back to the LSB. Some implementations address this by generating two MAC output bits at the end of each MAC cycle. One bit represents the carry bit, and the other represents the current bit. The carry bit may have the same binary weight as a higher significant bit. In this way, it's not necessary to shift the carry bit up to a higher bit. Each bit of MAC data can then be represented by two MAC data outputs. One could be the carry from the next MAC cycle, and the other could be the current bit of the current MAC cycle. The next MAC layer can receive the two data bits with the correct weights. These two data bits can be converted to a three-level input data driver. If both the carry and current bits are 1, the input data level may be 2. If a single MAC data bit is 1, the input data level can be 1; if all MAC data bits are not 1, the input data level can be 0.

[0064] Figure 5 A specific implementation of circuit 500 is shown, in which vector multiplication is performed using analog components on binary-encoded inputs. Circuit 500 is similar to... Figure 1The circuit 100 differs in that the output of the analog vector matrix multiplier 122 is fed into a series of binary-weighted ADCs 504. As previously mentioned, circuit 100 may include a one-bit DAC 114, an analog vector matrix multiplier 122, and a summing unit 132. Circuit 100 can still be understood as being divided into three parts. Part 110 can receive binary-encoded digital signals, each of which can represent a value in the input vector. Part 100 can also convert the binary-encoded digital signals into binary-encoded analog signals 116. Part 120 can receive the binary-encoded analog signals 116 and output a binary-encoded product 124 indicating the multiplication between the binary-encoded analog signals and a predefined matrix (e.g., a weighting matrix). When receiving individual bits from part 120, part 502 can sequentially receive bit-ordered outputs from part 120 and incrementally perform binary-weighted analog-to-digital conversion. In some implementations, circuit 500 may use a predefined bit order, wherein the MSB of each digital input signal 112 is received first, followed by MSB-1 bits, and so on up to the LSB. Section 502 may sequentially provide a plurality of digital output signals 506, which are immediately available when processed by section 502. For example, one of the plurality of digital output signals 506 representing the MSB may be output, followed by one of the digital output signals 506 representing the MSB-1 bit, and so on.

[0065] For example, multiple digital input signals 112 can be received in parallel by a portion 110. The digital input signals 112 can represent binary encoded values, and each digital input signal 112 can represent a vector X according to Equation 1. i The value X i (i = 0, 1, 2, ...). The binary bits of the input signal 112 can be represented by voltage levels (e.g., high for 1, low for 0), pulses (e.g., one pulse for 1, no pulse for 0), or time (e.g., a pulse of a first duration represents 1, a pulse of a second duration represents 0). As shown, four digital input signals (112-1, 112-2, 112-3, and 112-4) are received in parallel. Each of these input signals receives a single value of the input vector. In other embodiments, fewer or more digital input signals can be received. Each digital input signal 112 can be binary encoded. Thus, for each clock cycle of the digital portion of the circuit, bits for a specific bit sequence are received as digital input signal 112. For example, if four binary values ​​are input via each digital input signal, four clock cycles can be used to receive and convert them in parallel to the binary values ​​in the analog domain. The digital input signal 112 can be binary encoded such that the bit sequence of each value can be received from MSB to LSB.

[0066] Digital input signal 112 can be input to a one-bit DAC 114. The four existing one-bit DACs 114 (114-1, 114-2, 114-3, and 114-4) are used only as examples. In other embodiments, fewer or more one-bit DACs 114 may exist. For example, other embodiments may use similar representations of eight-bit, 16-bit, 32-bit, 64-bit, 128-bit, and / or data. In this disclosure, for ease of illustration, a four-bit data value may be used as a representative example. However, the operations described below for bits between the MSB and LSB can be multiplied and repeated for data of any value width. Regardless of the number of bits, one one-bit DAC may exist for each binary-encoded digital input signal 112. Each one-bit DAC 114 can output an analog signal indicating the received digital value. Therefore, binary-encoded analog signals 116 (116-1, 116-2, 116-3, and 116-4) can represent the analog conversion of digital input signal 112.

[0067] In part 120, the analog vector matrix multiplier 122 can receive a binary-encoded analog signal 116. The analog vector matrix multiplier 122 can perform multiplication operations sequentially for each bit sequence of the input value (e.g., the first clock cycle for MSB, the second clock cycle for MSB-1, the third clock cycle for MSB-2, etc.). Therefore, a separate multiplication operation can be performed for each bit sequence of the received binary-encoded analog signal 116. (The above is combined with...) Figure 2 Further details are provided regarding possible specific implementations of the analog vector matrix multiplier 122.

[0068] The sequential binary weighted ADC 504 in section 502 can receive the multiplication result signal 124 output from the analog vector matrix multiplier 122. For example, when the analog vector matrix multiplier 122 processes each bit of the binary-encoded analog signal 116 (starting with the MSB), the result can be immediately passed to the sequential binary weighted ADC 504. Subsequently, the sequential binary weighted ADC 504 can perform an analog-to-digital conversion on each analog bit received from the analog vector matrix multiplier 122. This can produce a digital output signal 506 provided by this increment as the analog vector matrix multiplier 122 processes each analog bit. Additionally, between each bit represented by the digital output signal 506, the sequential binary weighted ADC 504 can also provide carry bits that can be used to construct the final digital representation of the result.

[0069] In some specific embodiments, portion 502 of circuit 500 may further include Figure 1All or part of section 130 of circuit 100 in the circuit. For example, some embodiments may include charge integration circuitry, charge accumulation and redistribution circuitry, and / or other parts of summing component 132 for generating the final simulation results of the matrix multiplication process at this stage.

[0070] Figure 6 This illustrates how, according to some specific implementations, the input stream of individual bits is processed to produce a sequential output bit stream. The input vector X in Equation 1... i It can be provided as multiple bit streams 602 (Ip_0…Ip_N). For example, for an 8-bit data representation, each value in the input vector can be represented using an 8-bit sequence. Each bit stream 602 can be ordered such that the MSB is provided first, and then each lower-order bit is provided sequentially down to the LSB. In some specific implementations, as described above, the bit stream 602 can be continuously routed through a 1-bit DAC.

[0071] The analog value generated from each bit in bit stream 602 can be provided to MAC unit array 601 one at a time. Array 601 can be similar to that described above. Figure 2 The analog vector matrix multiplier 201. The weight values ​​in array 601 can represent W in equation 2. ij The matrix value. As described above, array 601 can accept bits from specific positions in bit stream 602 and process these bits together to generate an analog output that can be passed to binary weighted ADC 504. In some specific embodiments, array 601 may also provide a value indicating the bit position of the processed bit. For example, the first bit received by array 601 may be the MSB of each bit stream 602. Each MSB can be converted to an analog value and multiplied with a matrix value in array 601. This can produce an analog current output from array 601, which is provided to binary weighted ADC 504. This output may include one bit or MSB of 8 bits of data at index 7 (e.g., Op_b). <7> This value can be described as being used to control the output of subsequent circuit elements in the data path.

[0072] The binary weighted ADC 504 can receive each bit provided from array 601. Figure 3 In contrast to specific implementations, once processed by array 601, these implementations can begin providing digital output 604 from binary weighted ADC 504. For example, instead of waiting to provide from array 601... Figure 3The summation of the analog values ​​on each capacitor in the array 601, and then the subsequent analog-to-digital conversion of the final analog value, are implemented in these specific embodiments to perform incremental analog-to-digital conversion on each analog value as analog values ​​are provided from the array 601. The binary weighted ADC 504 can generate the MSB of the digital output 604 as the array 601 processes the MSB of the bit stream 602 and the carry value from MSB-1.

[0073] After processing each bit in bit stream 602, the binary weighted ADC 504 can provide a digital output indicating a digital representation of the result of Equation 1. However, as Figure 6 As shown, digital output 604 may include an additional N-1 bits for N-bit data. Specifically, between each bit value, digital output 604 may also include a carry bit, which represents the carry value from the bit stream to be added to the next bit after the previous bit. For example, digital output 608 may include the result of bit 7, the result of bit 6, the carry result of bit 6 to be added to the result of bit 7, and so on. This can result in digital output 604 with 2N-1 bits for N-bit data.

[0074] Figure 7 This illustration shows a specific process for generating a series of binary weighted digital outputs, according to some specific embodiments. This particular embodiment uses a charge integration circuit 704 to store the sequential outputs from the multiplication matrix. The following example again uses 8-bit data values ​​as an example. However, the principles used to process bits 6 through 0 can be copied / removed to increase / decrease the number of bits used to represent each data value. The following description will step-by-step describe the processing involved for each bit in the 8-bit value.

[0075] MAC operations performed by the simulated multiplication matrix are Figure 7 The operation flow is shown on the left. Starting at operation 701 from the MSB (e.g., bit 7), the MAC operation can output a current corresponding to the product of the MSB from each input data value and the weights in the multiplication matrix. The current from the MAC operation can be passed to the charge integration circuit 704. The charge integration circuit 704 may include a capacitor that receives the current from the MAC operation and stores the analog value as charge on the capacitor. The charge integration circuit 704 may also include circuitry that scales the current as it is passed to the capacitor, such that it corresponds to the bit-significance of the current operation. For example, when the MSB is received from the MAC operation, the charge integration circuit 704 may allow the entire current (unscaled) to be stored on the capacitor.

[0076] Next, comparator 705 can receive the voltage across the capacitor as an input. Another input can be received from voltage reference circuit 710. Initially, the output of voltage reference circuit 710 can be set to a voltage level between the full-scale outputs of MAC operation. If the capacitor voltage is higher than the reference voltage, the output of comparator 705 will be logic 1. If the capacitor voltage is lower than the reference voltage, the output of comparator 705 will be logic 0.

[0077] As described above, the MAC operation can also provide the current bit value to the charge integrating circuit 704 as an output. The current bit value can be used to scale the current to the correct level based on the current bit value. The current bit value can also be used as a selection signal for multiplexer 708, which routes the output of comparator 705 to a specific register. For example, multiplexer 708 can be coupled to multiple output registers 712. The current bit value can be used to select one of the output registers 712 corresponding to the current bit being processed. For MSB, "msb" can be selected. <7> The “bit reg” register, and the output of comparator 705 can be latched in this register.

[0078] When the current value is latched in the corresponding register 712, an output signal 714 can be generated, allowing subsequent stages in the processing pipeline to begin using those bit outputs to process subsequent multiplication operations. At this stage, "msb" can be... <7> The bit o / p (i.e., the output of the most significant bit 7) is provided for subsequent consecutive MAC operations, similar to the above. Figure 1 and Figure 2 The multiplication operation described in [the document]. The output can represent the current number of binary bits for the current bit and can be referred to as the bit value, or the "first bit value" related to the current bit being processed by the MAC operation.

[0079] At each stage, the value of the reference voltage 710 provided by the reference voltage circuit can be adjusted. Continuing with the MSB (bit 7) as an example, if the output of comparator 705 is logic 1, a new increment DVref7 = (1 / 2)Vref_msb can be provided for the voltage reference 710, where Vref_msb represents the original voltage reference used to process the MSB. On the other hand, if the output of comparator 705 is logic 0, the reference voltage can remain at Vref_msb without any additional increment. The reference voltage can combine at least two elements. One element can represent the basic reference voltage, and its value can be determined by the bit-level significance. For the charge integration specific implementation, this can be expressed in Equation 5 below.

[0080] Equation 5

[0081] Bits with the same valid bits can have the same basic reference voltage; for example, bit... <7> and co <6> They can have the same basic reference voltage. If the comparator output is logic 1, the second element can include all the additional adjustments for the accumulation. For the specific implementation of charge integration, such adjustments for the accumulation can be formulated as shown in List A.

[0082] After processing the MSB (bit 7), the multiplication operation outputs the result of the next most significant bit or MSB-1 (bit 6). Following the same processing described above, the analog value provided by the multiplication operation can be scaled by 0.5 to reflect the lower bit order of MSB-1 (bit 6), and the corresponding charge can be stored on the capacitor of the charge integration circuit 704. The resulting voltage on the capacitor can be provided to the comparator 705 along with the reference voltage 710. The signal provided by the voltage reference 710 can correspond to a voltage reference one bit higher than the current bit level. In this example, the comparator can receive the Vref_msb signal level used by the MSB as described above.

[0083] In the previous cycle, the output of comparator 705 produced the digital value of MSB. However, in the first cycle for the next MSB-1, the output of comparator 705 can produce a carry (e.g., co). <6> If the voltage across the capacitor in the charge integrating circuit 704 is higher than the reference voltage 710, then logic 1 can be stored in "co". <6> The carry bit is stored in the "bit reg" register. When the carry bit is logic 1, a new increment DVref6c = (1 / 2)Vref_msb can be provided to the voltage reference 710, making it (3 / 2)Vref_msb for the next comparator operation. Alternatively, if the voltage across the capacitor of the charge integrating circuit 704 is lower than the reference voltage 710, logic 0 can be stored in the "co" register. <6> This bit is stored in the “bit reg” register. This bit representation can be added to the MSB as part of the standard arithmetic operations described below. <7> Carry-over position.

[0084] The analog output of the MSB-1 bit multiplication operation can be used for two different comparison operations: one to generate the MSB-1 carry bit (or the "second digital bit value" mentioned above), and another to generate the MSB-1 binary valid bit (or the "first digital bit value") for the MSB-1 MAC operation. To generate the MSB-1 binary valid bit, the comparator can again compare the voltage across the capacitor with a reference level of Dvref6s + (1 / 2)Vref_msb, where DVref6s is the sum of all accumulated DVref values. For an MSB-1 bit, DVref6s = DVref7 + DVref6c. If the capacitor voltage is higher, the bit output is 1; if the capacitor voltage is lower, the bit output is 0. Finally, if the bit value is 1, the reference level can receive another increment, DVref6 = (1 / 4)Vref_msb.

[0085] In a general sense, each bit after the MSB can generate a carry bit by using the reference voltage of the previous bit. For any bit after the MSB, the Nth carry bit can be generated using a comparator as described above, using the reference signal of the higher-order bit-level significant bit. If the higher-order significant output bit is logic 1, the comparator reference level is increased by DVrefNc, where N is the Nth carry bit, and DVrefNc = 1 / 2. M-(N+1) Vref_msb, where M is the MSB bit (Mth = MSB), Vref_msb is the MSB bit reference level, and N is the Nth bit operated on from the Mth bit (MSB) to the 0th bit (LSB). For each Nth carry bit, the reference level is VrefNc = VrefNcb + DvrefNcs, where VrefNcb = 1 / 2 M-(N+1) Vref_msb is the reference level for the Nth carry bit (i.e., the reference level for the (N+1)th bit), DvrefNcs = It is the cumulative sum of the Vref increments before the Nth position.

[0086] Similarly, the Nth bit comparator operation, which uses the current for the currently valid bit, employs a reference level. If the integrated charge level is higher than the reference level, the current binary output bit is 1, and the comparator reference level is increased by DVrefN = 1 / 2. M -N + 1 Vref_msb. For each Nth bit, the reference level is VrefN = VrefNb + DvrefNs, where VrefNb = 1 / 2 M-N * Vref_msb is the fundamental reference level for the Nth bit, DVrefNs = The sum of the Vref increments preceding the Nth carry bit. This general process can be repeated for each bit in the sequence until the LSB. As described below, each binary output has a carry bit and a regular bit for the current bit level. These two bits can be directly fed into subsequent layers of the MAC operation. For example, list A completes... Figure 7 The operation shown is the same as the diagram of the specific implementation of charge integration using 8-bit data.

[0087] Figure 8 This illustrates a specific process for generating a continuous binary weighted digital output, according to some specific embodiments. The circuit is similar to... Figure 7 The circuit shown. However, unlike the charge integrating circuit 704, this circuit uses a multiplexer to receive different outputs from the multiplication function. Instead of scaling the analog outputs from the multiplication function and adding the charges associated with those outputs to a single integrating capacitor, this circuit can select different outputs from the multiplication function and provide them to the comparator. This function is as described above regarding... Figure 7 The ground operation, except that the reference voltage 710 can be scaled accordingly.

[0088] Figure 9 Alternative processing for generating a continuous binary-weighted digital output, according to some specific embodiments, is illustrated. Specifically, the circuit may include a transimpedance (TIA) or sense amplifier 906, and multiple binary-weighted switches and / or capacitors 905. This can be similar to the above described in... Figure 3 The arrangement is shown in the diagram. The analog output from the multiplication function can be stored separately on dedicated capacitors separated by multiple switches. The binary sequence control 902 can be provided to the binary weighting switch and / or capacitor 905 to control the switches so that the analog output of the multiplication function is stored on the correct capacitor.

[0089] As described above, the MSB can be processed once by comparator 705, and each consecutive bit after the MSB can be processed twice by comparator 705. The MSB can generate the first numeric bit value (e.g., "msb"). <7> The reference voltage 710 can be scaled based on the binary weight of the corresponding bit (e.g., a carry bit). Therefore, a binary weighted reference scaling circuit 910 can be included on the output of the voltage reference 710. The reference voltage 710 can be scaled using a voltage divider, a capacitive voltage divider, and / or any other method that selectively scales the voltage.

[0090] The following description details the MSB (Maximum Segment Size) used to process 8-bit data and the operations on each bit after the MSB. First, the MSB bits can be processed using the TIA 906. <7> The MAC current is converted into a voltage, which can charge the associated MSB capacitor 905 to that voltage. Comparator 705 can compare this voltage with an MSB reference level, which can be Vref_msb7 = Vref_msb. If the voltage is higher than Vref_msb7, the MSB output bit can be 1, and the reference level can be increased by DVref7 = (1 / 2)Vref_msb7.

[0091] For operations targeting the MSB-1 bit (e.g., bit 6), the output current of the multiplication operation can be converted to a voltage by TIA 906 and stored on the associated capacitor 905. This capacitor can be half the size of the MSB capacitor described above. Next, the MSB-1 capacitor can be connected to the MSB capacitor via a switch to redistribute the charge. The reference voltage 710 can be adjusted to compensate for the increased capacitance effect using a ratio RVC6 = 1 / (1 + 1 / 2) = 2 / 3. <6> The reference level can be Vref6c = (Vref_msb + DVref6cs) × RVC6 = 2 / 3 × Vref_msb, where DVref6cs = DVref7. The comparator can then compare the redistributed voltage across the capacitor with (2 / 3)Vref_msb. After the comparison, if the redistributed voltage level is higher than the reference value, then co... <6> It can be set to logic 1, otherwise co <6> It can be set to logic 0. If co <6> = 1, then the reference voltage level will be increased by the ratio of the capacitors that will be applied correctly, DVref6c = (1 / 2)Vref_msb.

[0092] Next, the second half of the operation on the MSB-1 bits can be performed. The first half of the above operation generates the carry bit, while the second half generates the bit-level significant bits for the MSB-1 multiplication operation. Comparator 705 can receive bits. <6> The reference level is Vref6 = RVC6((1 / 2)Vref_msb + DVref6s), where DVref6s = DVref7 + DVref6c. If the bit level is higher than the reference level, then the bit... <6> The output can be logic 1, otherwise, the bit... <6> The output can be logical 0. For example, list B is completed. Figure 9 The operation shown is for a specific implementation of TIA using 8-bit data.

[0093] Figure 10A pipeline of sequential MAC operations is illustrated according to some specific embodiments. The pipeline can be layered and executed sequentially as multiple bits are processed individually between each layer. The pipeline may include a first stage, which includes the above-described... Figure 6 The diagram shows a MAC unit array 601 and a binary weighted ADC 504. The output of the first stage of the pipeline can include a stream of sequentially generated bits 604 as described above. The sequentially generated bit stream 604 can include bit levels valid as, where the bit level valid as is referred to as the "first digital bit value" and in... Figure 10 The example shown is in the 8-bit data example. <7> , <6> ... <0> The continuously generated bitstream 604 can also include carry bits, which are referred to as "second bit values" and are... Figure 10 The text is incomplete and contains several grammatical errors and inconsistencies. A proper translation is not possible without the full context and complete sentences. <6> ...co <0> When each bit in a stream of 604 bits generated consecutively from the output of the binary weighted ADC 504, these bits can be made available as input to subsequent stages.

[0094] The pipeline may also include a second stage comprising a second MAC unit array 1001 and a second binary weighted ADC 1004. The second MAC unit array 1001 may receive a stream of continuously generated bits 604 from the output of the first binary weighted ADC 504 in the first stage of the pipeline. In some embodiments, the entire bit stream may be provided directly to the MAC unit array 1001, such that it includes both a first digital bit value and a second digital bit value (e.g., a bit-level valid bit and a carry bit). In other embodiments, the carry bit may be combined with the bit-level valid bit, such that the bit stream input to the second MAC unit array 1001 has the same width (e.g., 8 bits) as the remainder of the data path. These bits can be combined by adding the carry bit to a previous bit-level valid bit. This may result in some bit values ​​being a "2", represented by twice the voltage / current, as a logic 1 signal on the input.

[0095] Figure 10 This illustrates one of the advantages offered by a continuously weighted binary ADC at the output of a MAC operation. Specifically, instead of waiting for the first MAC stage in the pipeline to process all bits, the second MAC stage in the pipeline can begin processing bits as soon as they are output. As mentioned earlier, both MAC cell arrays 201 and 1001 use multiple one-bit DACs to continuously receive bits at the input. Therefore, the second stage can begin performing a 1-bit DAC operation while the first stage provides a single bit. After a two-cycle delay, a bit can be provided at the output of the first binary weighted ADC 504. <7> and co <6> These bits can then be immediately received by the second MAC unit array 1001 without waiting for the first stage of the pipeline to provide them. <6> The first bit and any subsequent bits.

[0096] although Figure 10 Only two stages of the MAC pipeline are shown, but other implementations may include many more not shown. Figure 10 The additional stages are explicitly described in this disclosure. Prior to this disclosure, each additional stage would require at least N additional clock cycles, where N represents the number of bits in the data path. However, using the methods described herein and... Figure 10 The specific implementation described herein requires only an additional 2 clock cycles as a delay to prepare the first two bits of the output from each stage.

[0097] Figure 11 A flowchart of a method 1100 for performing sequential binary-weighted digital-to-analog conversion according to some specific embodiments is shown. Each step in method 1100 can be as described above. Figures 1 to 10 Perform as described above. Specifically, any of the operations, features, and / or circuits described above can be used to perform these operations.

[0098] The method may include performing a first vector matrix multiplication operation (1102) sequentially for each bit sequence of values ​​in the input vector. The first vector matrix multiplication operation for each bit sequence can generate an analog output. For example, as described above, a MAC cell array can be used to receive each consecutive digital bit from the values ​​in the input vector. These values ​​can be continuously converted into analog signals by a one-bit DAC and processed by an analog multiplication matrix. The analog output may include an analog current representing the result of the multiplication / accumulation operation represented by the matrix.

[0099] The method may also include converting the analog output from the MAC operation into one or more digital bit values ​​(1104). This conversion can be performed by providing a voltage reference as an input to the comparator. As another input to the comparator, some implementations may provide a voltage of the analog output based on a vector matrix multiplication operation. For example, a transimpedance amplifier can convert an analog current into a voltage, which can be stored on an integrating capacitor or on individual capacitors representing the number of bits per bit level. In some implementations, each analog output representing the output of a single multiplication operation can be converted into one or more digital bit values. For example, the MSB can be converted into a single bit level significant bit, which may be referred to as the first digital bit value. For the bits that fall down to the LSB after the MSB, each bit can be converted into a bit level significant bit and a carry bit referred to as the second digital bit value. The terms "first" and "second" do not imply order or importance, but simply distinguish these two terms from each other in operation. Depending on the specific implementation, different methods may be used to adjust the reference signal provided to the comparator when the first digital bit value represents logic 1. Conversely, when the comparator output is logic 0, the reference signal can remain the same as the reference voltage for the current bit level (i.e., no additional reference voltage adjustment is required for the current bit level, even though the basic reference voltage may differ for each consecutive bit level). These different methods of adjusting the reference signal are described in detail above, as well as in Lists A and B.

[0100] The method may further include sending one or more digital bit values ​​to a second vector matrix multiplication operation (1106). In some implementations, this operation may be optional and may be included for use in pipelines comprising multiple MAC-level architectures, where the output of one MAC level feeds the input of a subsequent MAC level. There may be a two-cycle delay between each MAC level to generate the MSB bit and the first carry bit of the previous stage.

[0101] The methods, systems, and devices discussed above are examples. Various configurations may appropriately omit, substitute, or add various processes or components. For example, in alternative configurations, methods may be performed in a different order than those described, and / or stages may be added, omitted, and / or combined. Moreover, features described for certain configurations may be combined in various other configurations. Different aspects and elements of configurations may be combined in a similar manner. Furthermore, technology is evolving; therefore, many elements are illustrative and do not limit the scope of this disclosure or the scope of the patent applications.

[0102] Specific details are provided in the specification to offer a thorough understanding of the example configurations, including implementations. However, the configurations can be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary details to avoid obscuring the configurations. This specification provides only example configurations and does not limit the scope, applicability, or configuration of the claims. Rather, the prior description of the configurations will provide those skilled in the art with a feasible description for implementing the described techniques. Various changes can be made to the function and arrangement of the elements without departing from the spirit or scope of this disclosure.

[0103] Furthermore, the configuration can be described as a process depicted as a flowchart or block diagram. Although each operation can be described as being processed sequentially, many operations can be executed in parallel or simultaneously. Additionally, the order of operations can be rearranged. A process may have additional steps not included in the diagram.

[0104] Several example configurations have been described, and various modifications, alternative constructions, and equivalents may be used without departing from the spirit of this disclosure. For example, the above elements may be components of a larger system, where other rules may take precedence over or otherwise modify the application of the invention. Similarly, numerous steps may be taken before, during, or after considering the above elements.

[0105] List A

[0106] Charge integration mechanism

[0107] 1. The charge is integrated from the MSB to the LSB input bits using a binary weighted method.

[0108] 2. Perform binary weighting of capacitor charging by scaling the MAC current.

[0109] 3. After integrating / charging the charge for each binary bit, perform two comparator checks in sequence.

[0110] 1. The Nth carry-bit comparator checks the higher-order valid reference level. If the integrated charge level is high, the higher valid output bit is 1, and the comparator reference level is increased by DVrefNc, where N is the Nth carry-bit. This higher valid output bit is the borrow bit. DVrefNc = 1 / 2 M-N * Vref_msb, where M is the MSB bit at Mth = 0, and Vref_msb is the reference level for the MSB bit. N is the Nth bit from the Mth bit (MSB) to the 0th bit (LSB).

[0111] 2. The Nth (current) bit comparator checks the current binary reference level. If the integrated charge level is high, the current binary output bit is 1, and the comparator reference level is increased by DVrefN = 1 / 2. M-N + 1 * Vref_msb

[0112] 4. For each Nth carry-in bit, the reference level is VrefNc = VrefNcb + DvrefNcs, where VrefNcb is the fundamental reference level for the Nth carry-in bit, i.e., the fundamental reference level for the (N+1)th bit. VrefNcb = 1 / 2 M -（N + 1） * Vref_msb. DvrefNcs is the cumulative sum of the Nth ascending Vref. DvrefNcs=

[0113] 5. For each Nth bit, the reference level is VrefN = VrefNb + DvrefNs, where VrefNb is the basic reference level for the Nth bit. VrefNb = 1 / 2 M-N * Vref_msb. DVrefNs is the sum of Vrefs up to the Nth carry. DVrefNs =

[0114] 6. Continue to the LSB bit.

[0115] 7. The reference level adjustment can be obtained from the DAC circuit.

[0116] 8. Each binary output has a borrow bit and its own bit. These two bits are fed directly to the next layer of the MAC operation.

[0117] 9. In the input driver (e.g., DL driver), check the binary bits of the carry bit for each current bit and the next significant bit.

[0118] 1. If either the current bit or the carry bit is 1, the input strength (e.g., voltage level) is 1.

[0119] 2. If the current bit or the carry bit is both 1, the input strength (e.g., voltage level) will be doubled.

[0120] 3. This can reduce the charge integration time by half.

[0121] 4. This operation requires a three-stage DL driver / DAC.

[0122] Example operation mechanism for charge integration using 8-bit MAC

[0123] 1. The MSB bit MAC current charges the integrating capacitor.

[0124] 1. The comparator checks the capacitor voltage against the MSB reference level (Vref_msb).

[0125] 1. If the capacitor voltage is higher, then MSB <7> The output of a bit is 1 if it is 1, otherwise it is 0.

[0126] 2. If <7> = 1, then the reference level is increased by Dvref7 = 1 / 2 * Vref_msb.

[0127] 2. Bit <6> The bit MAC current charges the integrating capacitor at a current ratio of 0.5 (compared to the MSB MAC).

[0128] 1. The comparator checks the capacitor voltage against the MSB reference level Vref_msb.

[0129] 1. If the capacitor voltage is higher, then co <6> The bit output is 1, otherwise co <6> = 0. Here, co <6> It is a carry position <7> .

[0130] 2. If co <6> If the value is 1, the reference level is increased by DVref6c = 1 / 2 * Vref_msb, thus increasing to 3 / 2 * Vref_msb.

[0131] 2. Comparator checks capacitor voltage pair <6> Reference level, <6> The reference level is Dvref6s + 1 / 2 * Vref_msb. DVref6s is the sum of all accumulated DVrefs. DVref6s = DVref7 + DVref7c.

[0132] 1. If the capacitor voltage is higher, then <6> The bit output is 1, otherwise <6> = 0.

[0133] 2. If <6> If the value is 1, then the reference level will be increased by DVref6 = 1 / 4 * Vref_msb.

[0134] 3. Bit <5> The bit MAC current charges the integrating capacitor at a current ratio of 0.25 (compared to the MSB MAC).

[0135] 1. Comparator checks capacitor voltage pair <6> Bit reference level, <6> The bit reference level is Dvref5cs + 1 / 2 * Vref_msb. Dvref5cs = DVref7 + DVref6c + DVref6.

[0136] 1. If the capacitor voltage is higher, then co <5> The output of the bit is 1, otherwise co <5> = 0.

[0137] 2. If co <5> = 1, then the reference level is increased by DVref5c = 1 / 4 * Vref_msb.

[0138] 2. Comparator checks capacitor voltage pair <5> Reference level, <5> The reference level is Dvref5s + 1 / 4 * Vref_msb. Dvref5s = DVref7 + DVref6c + DVref6 + DVref5c.

[0139] 1. If the capacitor voltage is higher, then <5> The bit output is 1, otherwise <5> = 0.

[0140] 2. If <5> = 1, then the reference level is increased by 1 / 8 * Vref_msb

[0141] 4. Bit <4> The bit MAC current charges the integrating capacitor at a 1 / 8 current ratio (compared to the MSB MAC).

[0142] 1. Comparator checks capacitor voltage pair <5> Reference level, <5> The reference level is Dvref4cs + 1 / 4 * Vref_msb. Dvref4cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5.

[0143] 1. If the capacitor voltage is higher, then MSB co <4> The bit output is 1, otherwise co <4> = 0.

[0144] 2. If co <4> = 1, then the reference level is increased by DVref4c = 1 / 8 × Vref_msb.

[0145] 2. Comparator checks capacitor voltage pair <4> Reference level, <4> The reference level is Dvref4s + 1 / 8 * Vref_msb. Dvref4s = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c.

[0146] 1. If the capacitor voltage is higher, then <4> The bit output is 1, otherwise <4> = 0.

[0147] 2. If <4> = 1, then the reference level is increased by DVref4 = 1 / 16 * Vref_msb

[0148] 5. Bit <3> The bit MAC current charges the integrating capacitor at a current ratio of 1 / 16 (compared to the MSB MAC).

[0149] 1. Comparator checks capacitor voltage pair <4> Bit reference level, <4> The bit reference level is Dvref3cs + 1 / 8 * Vref_msb. Dvref3cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + Dvref4.

[0150] 1. If the capacitor voltage is higher, then co <3> The bit output is 1 or co <3> =0.

[0151] 2. If co <3> = 1, then the reference level is increased by DVref3c = 1 / 16 * Vref_msb.

[0152] 2. Comparator checks capacitor voltage pair <3> Reference level, <3> The reference level is Dvref3s + 1 / 16 *Vref_msb. Dvref3s = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + Dvref4 + DVref3c.

[0153] 1. If the capacitor voltage is higher, then <3> The bit output is 1, otherwise <3> = 0.

[0154] 2. If <3> = 1, then the reference level will be increased by DVref3 = 1 / 32 * Vref_msb.

[0155] 6. Bit <2> The bit MAC current charges the integrating capacitor at a current ratio of 1 / 32 (compared to the MSB MAC).

[0156] 1. Comparator checks capacitor voltage pair <3> Bit reference level, <3> The bit reference level is Dvref2cs + 1 / 16 * Vref_msb. Dvref2cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + Dvref4 + DVref3c + DVref3.

[0157] 1. If the capacitor voltage is higher, then co <2> The bit output is 1, otherwise co <2> = 0.

[0158] 2. If co <2> = 1, then the reference level is increased by DVref2c = 1 / 32 * Vref_msb.

[0159] 2. Comparator checks capacitor voltage pair <2> Reference level, <2> The reference level is Dvrefs + 1 / 32 *Vref_msb. Dvref2s = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c +Dvref4 + DVref3c + DVref3 + DVref2c.

[0160] 1. If the capacitor voltage is higher, then <2> The bit output is 1, otherwise <2> = 0.

[0161] 2. If <2> = 1, then the reference level is increased by DVref2 = 1 / 64 * Vref_msb.

[0162] 7. Bit <1> The bit MAC current charges the integrating capacitor at a current ratio of 1 / 64 (compared to the MSB MAC).

[0163] 1. Comparator checks capacitor voltage pair <2> Bit reference level, <2> The bit reference level is Dvref1cs + 1 / 32* Vref_msb. Dvref1cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + Dvref4 + DVref3c + DVref3 + DVref2c + DVref2.

[0164] 1. If the capacitor voltage is higher, then co <1> The output of the bit is 1, otherwise co <1> = 0.

[0165] 2. If co <1> = 1, then the reference level is increased by DVref1c = 1 / 64 * Vref_msb.

[0166] 2. Comparator checks capacitor voltage pair <1> Reference voltage, <1> The reference voltage is Dvrefs + 1 / 64 *Vref_msb. Dvref1s = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c +Dvref4 + DVref3c + DVref3 + DVref2c + DVref2 + DVref1c.

[0167] 1. If the capacitor voltage is higher, then <1> The bit output is 1, otherwise <1> = 0.

[0168] 2. If <1> = 1, then the reference level is increased by DVref1 = 1 / 128 * Vref_msb.

[0169] 8. Bit <0> The bit MAC current charges the integrating capacitor at a current ratio of 1 / 128 (compared to the MSB MAC).

[0170] 1. Comparator checks capacitor voltage pair <1> Bit reference level, <1> The bit reference level is Dvrefs + 1 / 64 *Vref_msb. Dvref0cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c +Dvref4 + DVref3c + DVref3 + DVref2c + DVref2 + DVref1c + DVref1.

[0171] 1. If the capacitor voltage is higher, then co <0> The output of the bit is 1, otherwise co <0> = 0.

[0172] 2. If co <0> = 1, then the reference level is increased by DVref0c = 1 / 128 * Vref_msb.

[0173] 2. Comparator checks capacitor voltage pair <0> Reference voltage, <0> The reference voltage is Dvrefs + 1 / 64 *Vref_msb. Dvref1s = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c +Dvref4 + DVref3c + DVref3 + DVref2c + DVref2 + DVref1c + DVref1 + DVref0c.

[0174] If the capacitor voltage is higher, then <0> The bit output is 1, otherwise <0> = 0.

[0175] List B

[0176] It has an operating mechanism of transimpedance amplifier, capacitor and switch.

[0177] 1. MAC from MSB to LSB input bits using a binary weighting method

[0178] 2. TIA converts the MAC current for each binary bit into a voltage and stores the voltage in a binary weighted capacitor.

[0179] 1. From MSB to LSB, each binary bit has its own binary weighted capacitor to store the TIA output voltage.

[0180] 2. When storing the TIA output voltage, the storage capacitor is connected to other capacitors associated with the higher significant bits. This adds new binary charge (expressed as voltage and capacitance) and redistributes the total charge.

[0181] 3. For the added capacitor, the reference level needs to be adjusted. The adjusted reference level ratio is RVCN = After the charge is redistributed, this ratio will be applied to each binary step.

[0182] 3. After redistributing the charge of each binary bit, the comparator check will be performed twice in sequence.

[0183] 1. The carry-bit comparator checks with the reference level one bit higher. If the redistributed capacitor level is higher, the carry-bit is 1, and the comparator reference level is increased by DVrefNc = 1 / 2. M-N * Vref_msb, where M is the MSB bit at Mth = MSB, and Vref_msb is the reference level for the MSB bit. N is the Nth bit from the Mth bit (MSB) to the 0th bit (LSB).

[0184] 2. The Nth (current) bit comparator checks the current binary reference level. If the integrating charge level is higher, the current binary output bit is 1, and the comparator reference level is increased by DVrefN = 1 / 2. M-N + 1 * Vref_msb

[0185] 4. For each Nth carry-in bit, the reference level is VrefNc = (VrefNcb + DvrefNcs) * RVCN, where VrefNcb is the basic reference level for the Nth carry-in bit, i.e., the basic reference level for the (N+1)th bit. VrefNcb = 1 / 2 M-（N + 1） * Vref_msb. DvrefNcs is the sum of the first N improved Vrefs. DvrefNcs =

[0186] 5. For each Nth bit, the reference level is VrefN = (VrefNb + DvrefNs) * RVCN, where VrefNb is the basic reference level for the Nth bit. VrefNb = 1 / 2 M-N* Vref_msb. DVrefNs is the cumulative sum of the raised Vrefs before the Nth carry. DVrefNs =

[0187] 6. Continue to the LSB bit.

[0188] 7. Each binary output has a borrow bit and its own bit. These two bits are directly fed into the next layer of the MAC operation.

[0189] Example operation mechanism of TIA using 8-bit data

[0190] 1. MSB bit <7> The MAC current is converted from TIA to V. <7> And the associated MSB capacitor is charged to V <7> .

[0191] 1. The comparator checks this V. <7> The MSB reference level is Vref_msb7 = Vref_msb.

[0192] 1. If V <7> If the value is higher than Vref_msb7, the MSB output bit will be 1.

[0193] 2. If <7> = 1, then the reference level will be increased by DVref7 = 1 / 2 * Vref_msb7.

[0194] 2. Position <6> The MAC current is converted from TIA to V. <6> And related positions <6> The capacitor (half the size of the MSB capacitor) is charged to V. <6> .

[0195] 1. <6> Capacitor connected to <7> Capacitors redistribute charge.

[0196] 2. Adjust the reference level by a ratio RVC6 = 1 / (1 + 1 / 2) = 2 / 3 to account for the increased capacitance effect.

[0197] 3. co <6> The reference level is Vref6c = (Vref_msb + DVref6cs) × RVC6 = 2 / 3 × Vref_msb. Where DVref6cs = DVref7.

[0198] 1. The comparator checks the redistributed level pair 2 / 3 * Vref_msb.

[0199] 2. If the redistributed level is higher, then co <6> = 1, otherwise co <6> = 0.

[0200] 3. If co <6> = 1, then the reference level will be increased by DVref6c = 1 / 2 × Vref_msb using the correctly applied capacitance ratio.

[0201] 4. Comparator using bits <6> The reference level Vref6 = RVC6 * (1 / 2 * Vref_msb + DVref6s) is used for checking. Where DVref6s = DVref7 + DVref6c.

[0202] 1. If the level is higher, then the bit... <6> The output is 1 if the value is 1, otherwise the bit is 1. <6> The output is 0.

[0203] 2. If <6> = 1, then the reference level will be increased by DVref6 = 1 / 4 * Vref_msb using the correctly applied capacitance ratio.

[0204] 3. Position <5> The MAC current is converted from TIA to V. <5> And related positions <5> The capacitor (one-quarter the size of the MSB capacitor) is charged to V. <5> .

[0205] 1. <5> Capacitor connected to <7> and <6> Capacitors redistribute charge.

[0206] 2. Adjust the reference level to accommodate the increased capacitance effect by a ratio RVC5 = 1 / (1 + 1 / 2 + 1 / 4) = 4 / 7.

[0207] 3. co <5> The reference level is Vref5c = (1 / 2 × Vref_msb + DVref5cs) × RVC5 = 4 / 7 × (1 / 2 × Vref_msb + Dvref5s). Where DVref5cs = DVref7 + DVref6c + DVref6.

[0208] 1. The comparator checks the redistributed level pair Vref5c.

[0209] 2. If the redistributed level is higher, then co <5> = 1, otherwise co <5> = 0.

[0210] 3. If co <5> = 1, then the reference level will be increased by DVref5c = 1 / 4 × Vref_msb using the correctly referenced capacitance ratio.

[0211] 4. Comparator using bits <5> The reference level Vref5 = RVC5 * (1 / 4 * Vref_msb + DVref5) is used for checking. DVref5 = DVref7 + DVref6c + DVref6 + DVref5c.

[0212] 1. If the level is higher, then the bit... <5> The output is 1 if the value is 1, otherwise the bit is 1. <5> The output is 0.

[0213] 2. If <5> = 1, then the reference level will be increased by DVref5 = 1 / 8 * Vref_msb using the correctly applied capacitance ratio.

[0214] 4. Position <4> The MAC current is converted from TIA to V. <4> And related positions <4> The capacitor (one-eighth the size of an MSB capacitor) is charged to V. <4> .

[0215] 1. <4> Capacitor connected to <7> , <6> and <5> Capacitors redistribute charge.

[0216] 2. Adjust the reference level to accommodate the increased capacitance effect using the ratio RVC4 = 1 / (1 + 1 / 2 + 1 / 4 + 1 / 8) = 8 / 15.

[0217] 3. co <4> The reference level is Vref4c = (1 / 4 × Vref_msb + DVref4cs) × RVC4 = 8 / 15 × (1 / 4 × Vref_msb + DVref4cs). Where DVref4cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5.

[0218] 1. The comparator checks the redistributed level pair Vref4c.

[0219] 2. If the redistributed level is higher, then co <4> = 1, otherwise co <4> = 0.

[0220] 3. If co <4> = 1, then the reference level will be increased by DVref4c = 1 / 8 × Vref_msb using the correctly applied capacitance ratio.

[0221] 4. Comparator using bits <4> The reference level Vref4 = RVC4 * (1 / 8 * Vref_msb + DVref4) is used for checking. DVref4 = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c.

[0222] 1. If the level is higher, then the bit... <4> The output is 1 if the value is 1, otherwise the bit is 1. <4> The output is 0.

[0223] 2. If <4> = 1, then the reference level will be increased by DVref4 = 1 / 16 * Vref_msb using the correctly applied capacitance ratio.

[0224] 5. Position <3> The MAC current is converted from TIA to V. <3> And related positions <3> The capacitor (one-sixteenth the size of an MSB capacitor) is charged to V. <3> .

[0225] 1. <3> Capacitor connected to <7> , <6> , <5> and <4> Capacitors redistribute charge.

[0226] 2. Adjust the reference level to accommodate the increased capacitance effect using the ratio RVC3 = 1 / (1 + 1 / 2 + 1 / 4 + 1 / 8 + 1 / 16) = 16 / 31.

[0227] 3. co <3> The reference level is Vref3c = (1 / 8 * Vref_msb + DVref3cs) * RVC3 = 16 / 31 * (1 / 8 * Vref_msb + DVref3cs). Where DVref3cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4.

[0228] 1. The comparator checks the redistributed level pair Vref3c.

[0229] 2. If the redistributed level is higher, then co <3> = 1, otherwise co <3> = 0.

[0230] 3. If co <3> = 1, then the reference level will be increased by DVref3c = 1 / 16×Vref_msb using the correctly applied capacitance ratio.

[0231] 4. Comparator using bits <3> The reference level Vref3 = RVC3 * (1 / 16 * Vref_msb + DVref3) is checked. DVref3 = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4 + DVref3c.

[0232] 1. If the level is higher, then the bit... <3> The output is 1 if the value is 1, otherwise the bit is 1. <3> The output is 0.

[0233] 2. If <3> = 1, then using the correct applied capacitance ratio will increase the reference level by DVref3 = 1 / 32 * Vref_msb.

[0234] 6. <2> The MAC current is converted from TIA to V. <2> And related positions <2> The capacitor (1 / 32 the size of the MSB capacitor) is charged to V. <2> .

[0235] 1. <2> Capacitor connected to <7> , <6> , <5> , <4> and <3> Capacitors redistribute charge.

[0236] 2. Adjust the reference level to accommodate the increased capacitance effect using the ratio RVC2 = 1 / (1 + 1 / 2 + 1 / 4 + 1 / 8 + 1 / 16 + 1 / 32) = 32 / 63.

[0237] 3. co <2> The reference level is Vref2c = (1 / 16 × Vref_msb + DVref2cs) × RVC2 = 32 / 63 × (1 / 16 × Vref_msb + DVref2cs). Where DVref2cs = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3.

[0238] 1. The comparator checks the redistributed level pair Vref2c.

[0239] 2. If the redistributed level is higher, then co <2> = 1, otherwise co <2> = 0.

[0240] 3. If co <2> = 1, then the reference level will be increased by DVref2c = 1 / 32×Vref_msb using the correctly applied capacitance ratio.

[0241] 4. Comparator using bits <2> The reference level Vref2 = RVC2 * (1 / 32 * Vref_msb + DVref2) is checked. DVref2 = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3 + DVref2c.

[0242] 1. If the level is higher, then the bit... <2> The output is 1 if the value is 1, otherwise the bit is 1. <2> The output is 0.

[0243] 2. If <2> = 1, then using the correctly applied capacitance ratio will increase the reference level by DVref2 = 1 / 64 * Vref_msb.

[0244] 7. Position <1> The MAC current is converted from TIA to V. <1> And related positions <1> The capacitor (1 / 64th the size of an MSB capacitor) is charged to V. <2> .

[0245] 1. <1> Capacitor connected to <7> , <6> , <5> , <4> , <3> and <2> Capacitors redistribute charge.

[0246] 2. Adjust the reference level to accommodate the increased capacitance effect using the ratio RVC2 = 1 / (1 + 1 / 2 + 1 / 4 + 1 / 8 + 1 / 16 + 1 / 32 + 1 / 64) = 64 / 127.

[0247] 3. co <1> The reference level is Vref1c = (1 / 32 × Vref_msb + DVref1cs) × RVC1 = 64 / 127 × (1 / 32 × Vref_msb + Dvref1cs). Among them, DVref1cs = DVref7 + DVref6c + DVref6 +DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3 + DVref2c + DVref2.

[0248] 1. The comparator checks the redistributed level pair Vref1c.

[0249] 2. If the redistributed level is higher, then co <1> = 1, otherwise co <1> = 0.

[0250] 3. If co <1> = 1, then the reference level will be increased by DVref1c = 1 / 64×Vref_msb using the correctly applied capacitance ratio.

[0251] 4. Comparator using bits <1> The reference level Vref1 = RVC1 * (1 / 64 * Vref_msb + DVref1) is checked. DVref1 = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3 + DVref2c + DVref2 + DVref1c.

[0252] 1. If the level is higher, then the bit... <1> The output is 1 if the value is 1, otherwise the bit is 1. <1> The output is 0.

[0253] 2. If <1> = 1, then using the correctly applied capacitance ratio will increase the reference level by DVref1 = 1 / 128 * Vref_msb.

[0254] 8. <0> The MAC current is converted from TIA to V. <0> And related positions <0> The capacitor (1 / 128th the size of the MSB capacitor) is charged to V. <0> .

[0255] 1. <0> Capacitor connected to <7> , <6> , <5> , <4> , <3> , <2> and <1> Capacitors redistribute charge.

[0256] 2. Adjust the reference level to accommodate the increased capacitance effect using the ratio RVC0 = 1 / (1 + 1 / 2 + 1 / 4 + 1 / 8 + 1 / 16 + 1 / 32 + 1 / 64 + 1 / 128) = 128 / 255.

[0257] 3. co <0> The reference level is Vref0c = (1 / 64 * Vref_msb + DVref0cs) * RVC0 = 128 / 255 * (1 / 64 * Vref_msb + Dvref0cs). Where DVref0cs = DVref7 + DVref6c + DVref6 +DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3 + DVref2c + DVref2 +DVref1c + DVref1.

[0258] 1. The comparator checks the redistributed level for Vref0c.

[0259] 2. If the redistributed level is higher, then co <0> = 1, otherwise co <0> = 0.

[0260] 3. If co <0> = 1, then the reference level will be increased by DVref0c = 1 / 128×Vref_msb using the correctly applied capacitance ratio.

[0261] 4. Comparator using bits <0> The reference level Vref0 = RVC0 * (1 / 128 * Vref_msb + DVref0) is checked. DVref0 = DVref7 + DVref6c + DVref6 + DVref5c + DVref5 + DVref4c + DVref4 + DVref3c + DVref3 + DVref2c + DVref2 + DVref1c + DVref1 + DVref0c.

[0262] 1. If the level is higher, then the bit... <0> The output is 1 if the value is 1, otherwise the bit is 1. <0> The output is 0.

Claims

1. A method for performing continuous binary weighted digital-to-analog conversion, the method comprising the following steps: The first vector matrix multiplication operation is performed sequentially for each position of the values ​​in the input vector, wherein the first vector matrix multiplication operation for each position generates a simulated output; For each simulation output generated by the vector-matrix multiplication operation: Convert the analog output into one or more digital bit values; Send one or more numeric bit values ​​to the second vector matrix multiplication operation.

2. The method of claim 1, wherein the first vector matrix multiplication operation is performed starting with the most significant bit (MSB) of each value in the input vector and ending with the least significant bit (LSB) of each value in the input vector.

3. The method of claim 1, wherein the step of converting the analog output into the one or more digital bit values ​​comprises the following steps: The analog output is compared with a reference signal, wherein when the analog output is greater than the reference signal, a first digital bit value among the one or more digital bit values ​​represents logic 1, and when the analog output is less than the reference signal, the first digital bit value represents logic 0.

4. The method of claim 3, wherein the step of converting the analog output into the one or more digital bit values ​​further comprises the following steps: When the first digital bit value represents logic 1, the reference signal is adjusted.

5. The method according to claim 3, wherein: The simulated output corresponds to the MSB of each value in the input vector; and The one or more digital bit values ​​include the first digital bit value without a carry bit.

6. The method of claim 4, wherein the step of converting the analog output into the one or more digital bit values ​​further comprises the following steps: After adjusting the reference signal, the analog output is compared with the reference signal, wherein when the analog output is greater than the reference signal, the second digital bit value among the one or more digital bit values ​​represents logic 1, and when the analog output is less than the reference signal, the second digital bit value represents logic 0.

7. The method according to claim 6, wherein: The first digital bit value represents the value corresponding to the current analog output; and The second digital bit value represents the carry value that will be added to the value corresponding to the previous analog output.

8. The method of claim 3, wherein the step of converting the analog output into the one or more digital bit values ​​further comprises the following steps: The reference signal is maintained when the first digital bit value represents logic 0.

9. The method of claim 8, wherein the step of converting the analog output into the one or more digital bit values ​​further comprises the following steps: After adjusting the reference signal, the analog output is compared with the reference signal, wherein when the analog output is greater than the reference signal, the second digital bit value among the one or more digital bit values ​​represents logic 1, and when the analog output is less than the reference signal, the second digital bit value represents logic 0.

10. The method of claim 1, wherein there is a two-cycle delay between the step of converting the analog output into the one or more digital bit values ​​and the step of sending the one or more digital bit values ​​to the second vector matrix multiplication operation.

11. A vector-matrix multiplier circuit, comprising: Multiple numeric inputs, where each numeric input receives an input value encoded in binary form of an input vector; A vector matrix multiplier circuit that performs binary-encoded vector multiplication on a single bit sequence at a time using the binary-encoded input value; A sequential binary weighted analog-to-digital converter, wherein the sequential binary weighted analog-to-digital converter receives analog outputs sequentially from the vector matrix multiplier circuit and sequentially converts each of the analog outputs into one or more digital bit values.

12. The vector matrix multiplier circuit according to claim 11, wherein the continuous binary weighted analog-to-digital converter comprises: A charge integration circuit, the charge integration circuit including a capacitor, wherein each of the analog outputs stores charge on the capacitor.

13. The vector matrix multiplier circuit of claim 11, wherein the vector matrix multiplier circuit further transmits an indication of the current bit order.

14. The vector matrix multiplier circuit of claim 13, further comprising a multiplexer that sends the one or more digital bit values ​​to one of a plurality of registers, wherein the indication of the current bit order controls the multiplexer.

15. The vector matrix multiplier circuit of claim 11, wherein the continuous binary weighted analog-to-digital converter comprises: Multiple binary weighted switches and capacitors, each of which stores a different analog output from the analog output.

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