A GGNMOS structure

Abstract

The present invention provides a GGNMOS structure, comprising a first high-voltage P-well located in a P-type substrate region; a first N-well in the first high-voltage P-well; a first N-type drift region; a first N-type heavily doped region; a second N-well is provided on both sides of the first high-voltage P-well; a second N-type heavily doped region is provided on one of the second N-wells; a P-well is provided on one side of the second N-well; a first P-type heavily doped region is provided on the P-well; a second high-voltage P-well is provided on one side of the P-well; a second N-type drift region and a P-type drift region are provided in the second high-voltage P-well; a third N-type heavily doped region is provided on the second N-type drift region; a second P-type heavily doped region is provided on the P-type drift region; a gate structure is provided on the second high-voltage P-well between the second N-type drift region and the P-well; the doping concentration of the N-well of the present invention is higher than that of the N-type drift region, and the avalanche breakdown point is effectively transferred from the N-type drift region and the high-voltage P-well to the N-well and the high-voltage P-well, thereby effectively reducing the trigger voltage. The trigger uniformity is effectively improved without significantly increasing the area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a GGNMOS structure. Background Art

[0002] The ESD protection design of high-voltage devices is particularly important due to the weak robustness of HV NMOS (high trigger voltage and low holding voltage). In addition, the lower holding voltage will introduce a higher latchup or quasi-latchup risk in the IC circuit. On the other hand, high-voltage ESD GGNMOS often has a larger layout area, but its uneven triggering problem will result in the inability to exert the protection limit of a large size. Therefore, reducing the trigger voltage of HV GGNMOS, increasing its holding voltage and uniform conduction, has great application significance.

[0003] In order to increase the holding voltage and reduce the turn-on voltage, a substrate-triggered NMOS structure (STNMOS) was proposed, but it requires a large layout area. In addition, it has been reported that the holding voltage can be effectively increased by embedding PMOS, but the layout area will also increase significantly. Since the multi-finger structure of HV GGNMOS itself has a large layout area, it is of practical application value to improve its performance without significantly increasing its occupied area.

[0004] For the multi-finger structure, the original intention of its design is to have a larger width to withstand ESD current, thereby improving the ESD resistance of the protection circuit. However, most studies have shown that ESD current tends to be conducted along a certain local part, and as the current increases, the local resistance value shows a trend of first increasing and then decreasing. When entering the negative resistance area, the further increase in current will further lead to a decrease in resistance value, resulting in the current being concentrated in the local area and eventually leading to thermal breakdown. Therefore, the non-uniform conduction of high-voltage ESD devices will greatly weaken the ESD resistance expected during the design. Solving the problem of uniform conduction of high-voltage ESD devices has a significant impact on improving the ESD current resistance of the protection circuit.

[0005] While improving the non-uniform conduction problem of high-voltage ESD GGNMOS, reducing the trigger voltage and increasing the holding voltage is one of the current challenges of ESD. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a GGNMOS structure for solving the problem that the GGNMOS in the prior art has a high trigger voltage and a low holding voltage and cannot play an effective protective role.

[0007] To achieve the above objectives and other related objectives, the present invention provides a GGNMOS structure, comprising at least:

[0008] A P-type substrate; a first high-voltage P-well (HVPW) located in the P-type substrate region; a first N-well (Nwell) formed in the first high-voltage P-well; a first N-type drift region (NDF) formed on the first N-well; a first N-type heavily doped region (N+) formed on the first N-type drift region;

[0009] A second N-well (NW) is provided on both sides of the first high-voltage P-well; a second N-type heavily doped region is provided on one of the second N-wells; a P-well (PW) is provided on the side of the second N-well away from the first high-voltage P-well; a first P-type heavily doped region is provided on the P-well; a second high-voltage P-well is provided on the side of the P-well away from the second N-well;

[0010] A second N-type drift region (NDF) and a P-type drift region (PDF) are provided in the second high-voltage P-well; a third N-type heavily doped region is provided on the second N-type drift region; and a second P-type heavily doped region is provided on the P-type drift region;

[0011] A gate structure is provided on the upper surface of the second high-voltage P-well between the second N-type drift region and the P-well;

[0012] An STI region is provided between the P-type drift region and the second N-type drift region, an STI region is provided in the second high-voltage P-well between the second N-type drift region and the gate structure, and an STI region is provided between the second high-voltage P-well and the P-well; an STI region is provided between the P-well and the second N-well; and an STI region is provided between the second N-well and the first high-voltage P-well.

[0013] Preferably, the first N-type heavily doped region is led out from the electrode to form a drain.

[0014] Preferably, the drain is connected to a power supply voltage VDD.

[0015] Preferably, the third N-type heavily doped region is led out from the electrode to form a source.

[0016] Preferably, the second P-type heavily doped region is led out from the electrode to form a base.

[0017] Preferably, the gate structure is led out from the electrode to form a gate.

[0018] Preferably, the base, source, gate and the first P-type heavily doped region are connected to each other at a ground voltage.

[0019] Preferably, the doping concentration of the first N-well is higher than the doping concentration of the first and second N-type drift regions.

[0020] As described above, the GGNMOS structure of the present invention has the following beneficial effects: the doping concentration of the N-well of the present invention is higher than that of the N-type drift region, which effectively transfers the avalanche breakdown point from the N-type drift region and the high-voltage P-well to the N-well and the high-voltage P-well, thereby effectively reducing the trigger voltage. The N-well can use the N-well of the medium-voltage MV device or the low-voltage LV device without adding an additional mask. Compared with embedding the P-well, embedding the N-well can effectively increase the holding voltage, thereby reducing the risk of latchup. Forcing the trigger current to flow into the P substrate can effectively increase the V of the parasitic BJT. be (the voltage difference between the base and emitter junctions), the trigger uniformity can be effectively improved without significantly increasing the layout area. After the trigger uniformity is improved, it helps to achieve the expected ESD resistance by changing the size of the HV GGNMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic diagram of the GGNMOS structure of the present invention. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] See also Figure 1 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] The present invention provides a GGNMOS structure, comprising at least:

[0025] A P-type substrate; a first high-voltage P-well (HVPW) located in the P-type substrate region; a first N-well (Nwell) formed in the first high-voltage P-well; a first N-type drift region (NDF) formed on the first N-well; a first N-type heavily doped region (N+) formed on the first N-type drift region;

[0026] A second N-well (NW) is provided on both sides of the first high-voltage P-well; a second N-type heavily doped region is provided on one of the second N-wells; a P-well (PW) is provided on the side of the second N-well away from the first high-voltage P-well; a first P-type heavily doped region is provided on the P-well; a second high-voltage P-well is provided on the side of the P-well away from the second N-well;

[0027] A second N-type drift region (NDF) and a P-type drift region (PDF) are provided in the second high-voltage P-well; a third N-type heavily doped region is provided on the second N-type drift region; and a second P-type heavily doped region is provided on the P-type drift region;

[0028] A gate structure is provided on the upper surface of the second high-voltage P-well between the second N-type drift region and the P-well;

[0029] An STI region is provided between the P-type drift region and the second N-type drift region, an STI region is provided in the second high-voltage P-well between the second N-type drift region and the gate structure, and an STI region is provided between the second high-voltage P-well and the P-well; an STI region is provided between the P-well and the second N-well; and an STI region is provided between the second N-well and the first high-voltage P-well.

[0030] Furthermore, in the present invention, the first N-type heavily doped region of this embodiment is led out by an electrode to form a drain.

[0031] Furthermore, in the present invention, the drain electrode of this embodiment is connected to a power supply voltage VDD (internal operating voltage of the circuit).

[0032] Furthermore, in the present invention, the third N-type heavily doped region of this embodiment is led out by an electrode to form a source.

[0033] Furthermore, in the present invention, the second P-type heavily doped region of this embodiment is led out by an electrode to form a base.

[0034] Furthermore, in the present invention, the gate structure of this embodiment is led out by an electrode to form a gate.

[0035] The present invention further provides that the base, source, gate and the first P-type heavily doped region of this embodiment are connected to a ground voltage.

[0036] Furthermore, in the present invention, the doping concentration of the first N-well in this embodiment is higher than the doping concentration of the first and second N-type drift regions.

[0037] like Figure 1 As shown, Figure 1It is a schematic diagram of the GGNMOS structure of the present invention. The GGNMOS structure in this embodiment at least includes: a P-type substrate (P-sub); a first high-voltage P-well (HVPW) 01 located in the P-type substrate (P-sub) region; a first N-well (Nwell) 05 formed in the first high-voltage P-well 01; a first N-type drift region (NDF) 06 formed on the first N-type drift region 05; a first N-type heavily doped region (N+) 07 formed on the first N-type drift region 06;

[0038] A second N-well (NW) 03 is provided on both sides of the first high-voltage P-well 01; a second N-type heavily doped region 14 is provided on one of the second N-wells 03; a P-well (PW) 04 is provided on the side of the second N-well 03 away from the first high-voltage P-well 01; a first P-type heavily doped region 13 is provided on the P-well; a second high-voltage P-well 02 is provided on the side of the P-well away from the second N-well;

[0039] A second N-type drift region (NDF) 08 and a P-type drift region (PDF) 09 are provided in the second high-voltage P-well 02; a third N-type heavily doped region 10 is provided on the second N-type drift region; and a second P-type heavily doped region 11 is provided on the P-type drift region 09;

[0040] A gate structure 12 is provided on the upper surface of the second high-voltage P-well between the second N-type drift region 08 and the P-well 04;

[0041] An STI region 15 is provided between the P-type drift region and the second N-type drift region, an STI region is provided in the second high-voltage P-well between the second N-type drift region and the gate structure, and an STI region is provided between the second high-voltage P-well and the P-well; an STI region is provided between the P-well and the second N-well; and an STI region is provided between the second N-well and the first high-voltage P-well.

[0042] The first N-type heavily doped region is led out by an electrode to form a drain. The drain is connected to the power supply voltage VDD (internal working voltage of the circuit). The third N-type heavily doped region of this embodiment is led out by an electrode to form a source. The second P-type heavily doped region of this embodiment is led out by an electrode to form a base. The gate structure of this embodiment is led out by an electrode to form a gate.

[0043] The base, source, gate and the first P-type heavily doped region of this embodiment are connected to a ground voltage. The doping concentration of the first N-well of this embodiment is higher than the doping concentration of the first and second N-type drift regions.

[0044] The multi-finger structure of the existing 32V GGNMOS is difficult to trigger evenly, which results in its failure to exert its maximum protection function and often causes thermal breakdown in some areas.

[0045] The present invention achieves the function of adjusting the trigger voltage and the holding voltage by placing an N-well (NWE11) with a concentration slightly higher than that of the N-type drift region NDF at the interface between the N-type drift region NDF and the high-voltage P-well HVPW.

[0046] By placing an adjacent P-well (Pwell) and N-well (Nwell) between the drain and the gate, a reverse biased PN junction is formed, so that the trigger current flows into the substrate. Since the parasitic resistance of the substrate is higher than the parasitic resistance of the HVPW, the voltage difference V between the base and the emitter junction is BE Higher, the emitter junction of the parasitic BJT can be effectively turned on, thereby achieving the purpose of uniformly turning on the multi-finger GGNMOS.

[0047] The doping concentration of Nwell in the present invention is higher than that of NDF, which effectively transfers the avalanche breakdown point from NDF / HVPW to Nwell-HVPW, thereby effectively reducing the trigger voltage. Nwell can use MV devices or LV Nwell without adding additional masks. Compared with embedded Pwell, embedded Nwell can effectively increase the holding voltage, thereby reducing the risk of latchup. Forcing the trigger current to flow into psub can effectively increase the V of the parasitic BJT. be , without significantly increasing the layout area, the trigger uniformity can be effectively improved. After the trigger uniformity is improved, it helps to achieve the expected ESD resistance by changing the size of HVGGNMOS.

[0048] In summary, the doping concentration of the N-well of the present invention is higher than that of the N-type drift region, which effectively transfers the avalanche breakdown point from the N-type drift region and the high-voltage P-well to the N-well and the high-voltage P-well, thereby effectively reducing the trigger voltage. The N-well can use the N-well of the medium-voltage MV device or the low-voltage LV device without adding an additional mask. Compared with embedding the P-well, embedding the N-well can effectively increase the holding voltage, thereby reducing the risk of latchup. Forcing the trigger current to flow into the P substrate can effectively increase the V of the parasitic BJT. be (the voltage difference between the base and the emitter junction), without significantly increasing the layout area, the trigger uniformity can be effectively improved. After the trigger uniformity is improved, it is helpful to achieve the expected ESD resistance by changing the size of the HV GGNMOS. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A GGNMOS structure, characterized in that: At least: P-type substrate; A first high-voltage P-well located in the P-type substrate region; a first N-well formed in the first high-voltage P-well; a first N-type drift region formed on the first N-well; a first N-type heavily doped region formed on the first N-type drift region; A second N well is provided on both sides of the first high-voltage P well; a second N-type heavily doped region is provided on one of the second N wells; a P well is provided on the side of the second N well away from the first high-voltage P well; a first P-type heavily doped region is provided on the P well; a second high-voltage P well is provided on the side of the P well away from the second N well; A second N-type drift region and a P-type drift region are provided in the second high-voltage P-well; a third N-type heavily doped region is provided on the second N-type drift region; and a second P-type heavily doped region is provided on the P-type drift region; A gate structure is provided on the upper surface of the second high-voltage P-well between the second N-type drift region and the P-well; An STI region is provided between the P-type drift region and the second N-type drift region, an STI region is provided in the second high-voltage P-well between the second N-type drift region and the gate structure, and an STI region is provided between the second high-voltage P-well and the P-well; an STI region is provided between the P-well and the second N-well; and an STI region is provided between the second N-well and the first high-voltage P-well.

2. The GGNMOS structure according to claim 1, characterized in that: The first N-type heavily doped region is led out from the electrode to form a drain.

3. The GGNMOS structure according to claim 2, characterized in that: The drain is connected to a power supply voltage.

4. The GGNMOS structure according to claim 3, characterized in that: The third N-type heavily doped region is led out from the electrode to form a source.

5. The GGNMOS structure according to claim 4, characterized in that: The second P-type heavily doped region is led out from the electrode to form a base.

6. The GGNMOS structure according to claim 5, characterized in that: The gate structure is led out from the electrode to form a gate.

7. The GGNMOS structure according to claim 5, characterized in that: The base, source, gate and the first P-type heavily doped region are connected to a ground voltage.

8. The GGNMOS structure according to claim 1, characterized in that: The doping concentration of the first N-well is higher than the doping concentrations of the first and second N-type drift regions.

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