Display device

Abstract

A display device is provided. The display device includes a light emitting element, a first transistor, a second transistor, and a diode. The first transistor can control a drive current flowing to the light emitting element according to a voltage applied to a gate electrode of the first transistor. The second transistor is electrically connected between the gate electrode of the first transistor and a first electrode of the first transistor. A first electrode of the diode is electrically connected to a first electrode of the second transistor. A second electrode of the diode is electrically connected to the gate electrode of the first transistor.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0156175, filed with the Korean Intellectual Property Office on November 20, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The technical field relates to display devices. Background Technology

[0003] The display device can display images based on input signals. Display devices are included in various electronic devices such as smartphones, tablets, digital cameras, laptops, navigators, and televisions. A display device includes one or more display panels for displaying images.

[0004] Organic light-emitting display panels use organic light-emitting elements (OLEDs) that emit light through the recombination of electrons and holes to display images. OLED display devices include transistors that control the flow of driving current to the organic light-emitting elements. Summary of the Invention

[0005] The implementation may involve a display device including pixels that can minimize or prevent current leakage in a high-speed driving environment while adequately compensating for threshold voltage deviations of the driving transistors.

[0006] An embodiment of the display device includes a light-emitting element, a first transistor that controls the driving current flowing to the light-emitting element according to the voltage applied to the gate electrode, a second transistor disposed between the gate electrode of the first transistor and the first electrode of the first transistor, and a diode including a first electrode connected to the first electrode of the second transistor and a second electrode connected to the gate electrode of the first transistor.

[0007] An embodiment of the display device includes a light-emitting element, a first transistor that controls a drive current flowing to the light-emitting element according to a voltage applied to a gate electrode, a second transistor disposed between the gate electrode of the first transistor and a first electrode of the first transistor, and a third transistor connected to the gate electrode of the first transistor and having an initialization voltage applied thereto, wherein the active layer of the first transistor and the active layer of the second transistor comprise polysilicon, and the active layer of the third transistor comprises an oxide semiconductor.

[0008] An embodiment of the display device includes a substrate, a first semiconductor layer disposed on the substrate and including an active layer of a first transistor, a first gate insulating layer disposed on the first semiconductor layer, a first conductive layer disposed on the first gate insulating layer and including a gate electrode of the first transistor, a second gate insulating layer disposed on the first conductive layer, a first electrode of a diode disposed on the second gate insulating layer, a first interlayer insulating layer disposed on the first electrode of the diode, a second semiconductor layer disposed on the first interlayer insulating layer and including an active layer of a second transistor and a second electrode of the diode, a second interlayer insulating layer disposed on the second semiconductor layer, and a second conductive layer disposed on the second interlayer insulating layer and including a first electrode and a second electrode of the first transistor, wherein the first semiconductor layer includes polysilicon and the second semiconductor layer includes an oxide semiconductor.

[0009] The implementation may relate to a display device. The display device may include a light-emitting element, a first transistor, a second transistor, and a diode. The first transistor may control the drive current flowing to the light-emitting element based on the voltage applied to its gate electrode. The second transistor may be electrically connected between the gate electrode of the first transistor and a first electrode of the first transistor. The first electrode of the diode may be electrically connected to the first electrode of the second transistor. The second electrode of the diode may be connected to the gate electrode of the first transistor.

[0010] The first electrode of a diode may include a metal. The second electrode of a diode may include an oxide semiconductor.

[0011] In a diode, current can flow from the first electrode to the second electrode.

[0012] Each of the active layer of the first transistor and the active layer of the second transistor may include polysilicon.

[0013] The display device may further include a third transistor electrically connected to the gate electrode of the first transistor and receiving an initialization voltage. The active layer of the third transistor may include an oxide semiconductor.

[0014] The first and second transistors can be PMOS transistors. The third transistor can be an NMOS transistor.

[0015] The material of the second electrode of the diode can be the same as the material of the active layer of the third transistor.

[0016] The display device may also include an insulator and a capacitor. The first electrode of the capacitor may be electrically connected to the gate electrode of the first transistor. The second electrode of the capacitor may overlap with the first electrode of the capacitor. The first electrode of the diode and the second electrode of the capacitor may be directly disposed on the same surface of the insulator.

[0017] The display device may also include a fourth transistor electrically connected to the second electrode of the first transistor and receiving data voltage.

[0018] The display device may also include scan lines that are electrically connected to both the gate electrode of the second transistor and the gate electrode of the fourth transistor without passing through an intermediary transistor.

[0019] The implementation may relate to a display device. The display device may include: a light-emitting element; a first transistor that controls a drive current flowing to the light-emitting element based on a voltage applied to the gate electrode of a first transistor; a second transistor electrically connected between the gate electrode of the first transistor and a first electrode of the first transistor; and a third transistor electrically connected to the gate electrode of the first transistor without an intermediary transistor and receiving an initialization voltage. Each of the active layer of the first transistor and the active layer of the second transistor may include polysilicon. The active layer of the third transistor may include an oxide semiconductor.

[0020] The display device may also include a diode electrically connected between the first electrode of the second transistor and the gate electrode of the first transistor.

[0021] The first electrode of a diode may include a metal. The second electrode of a diode may include an oxide semiconductor.

[0022] The material of the second electrode of the diode can be the same as the material of the active layer of the third transistor.

[0023] The display device may also include an insulator and a capacitor. The first electrode of the capacitor may be electrically connected to the gate electrode of the first transistor. The second electrode of the capacitor may overlap with the first electrode of the capacitor. The first electrode of the diode and the second electrode of the capacitor may be directly disposed on the same surface of the insulator.

[0024] The display device may also include a fourth transistor electrically connected to the second electrode of the first transistor and receiving data voltage.

[0025] The display device may also include scan lines that are electrically connected to both the gate electrode of the second transistor and the gate electrode of the fourth transistor without passing through an intermediary transistor.

[0026] The display device may include a substrate, a first transistor, a second transistor, a diode, a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer. The first gate insulating layer may be disposed between the gate electrode of the first transistor and the active layer of the first transistor. The active layer of the first transistor may be disposed between the gate electrode of the first transistor and the substrate. The second gate insulating layer may be disposed between the first electrode of the diode and the substrate. The gate electrode of the first transistor may be disposed between the second gate insulating layer and the substrate. The first interlayer insulating layer may be disposed between the second electrode of the diode and the substrate. The first electrode of the diode may be disposed between the first interlayer insulating layer and the substrate. The first interlayer insulating layer may be disposed between the active layer of the second transistor and the substrate. The second interlayer insulating layer may be disposed between the first electrode of the first transistor and the substrate, and may also be disposed between the second electrode of the first transistor and the substrate. Each of the second electrode of the diode and the active layer of the second transistor may be disposed between the second interlayer insulating layer and the substrate. The active layer of the first transistor may include polysilicon. Each of the active layer of the second transistor and the second electrode of the diode may include an oxide semiconductor.

[0027] The display device may also include a connecting member that electrically connects the first electrode of the first transistor and the first electrode of the diode.

[0028] The connecting member can be connected to the first electrode of the first transistor through a first contact hole passing through the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

[0029] The connecting member can be connected to the first electrode of the diode through a second contact hole passing through the second interlayer insulation layer and the first interlayer insulation layer.

[0030] The display device may also include a capacitor. A first electrode of the capacitor may be electrically connected to the gate electrode of a first transistor. A second electrode of the capacitor may overlap the first electrode of the capacitor. A second gate insulating layer may be disposed between the second electrode of the capacitor and the substrate.

[0031] The material of the first electrode of the diode can be the same as the material of the second electrode of the capacitor.

[0032] According to the embodiment of the display device, even when a pixel is placed in a high-speed driving environment, current leakage can be minimized or prevented and the threshold voltage deviation of the driving transistor can be adequately compensated. Attached Figure Description

[0033] Figure 1 This is a plan view of a display device according to an embodiment.

[0034] Figure 2 According to the implementation method Figure 1 A side view of the display device.

[0035] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0036] Figure 4 This is a layout diagram of a pixel of a display device according to an embodiment.

[0037] Figure 5 According to the implementation method Figure 4 The layout diagram of the first and second semiconductor layers.

[0038] Figure 6 This is a cross-sectional view of a display device according to an embodiment.

[0039] Figure 7 This is a cross-sectional view of a display device according to an embodiment.

[0040] Figure 8 According to the implementation method Figure 7 The diagram of region A in the image.

[0041] Figure 9 An energy band diagram of a leakage prevention diode according to an embodiment is shown.

[0042] Figure 10 This is a graph showing the change in current of the leakage prevention diode relative to the bias voltage according to an embodiment.

[0043] Figure 11 This includes a graph showing the variation of the leakage protection diode's current relative to the bias voltage, depending on process conditions.

[0044] Figure 12 This is a cross-sectional view of the display panel of the display device according to the embodiment.

[0045] Figure 13 This is a cross-sectional view of the display panel of the display device according to the embodiment.

[0046] Figure 14 This is a layout diagram of a pixel of a display device according to an embodiment.

[0047] Figure 15 This is a cross-sectional view of the display panel according to the embodiment. Detailed Implementation

[0048] Exemplary embodiments are described with reference to the accompanying drawings. Actual embodiments may be implemented in different forms and should not be construed as being limited to the exemplary embodiments.

[0049] When an element is referred to as being "on" a layer, the element may be directly on the layer or indirectly on the layer, wherein one or more intervening items exist between the element and the layer. The same reference numerals may indicate the same parts or similar elements. In the figures, sizes may be enlarged for clarity.

[0050] While terms such as "first," "second," etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Without departing from the teachings of one or more embodiments, a first element may be referred to as a second element. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first," "second," etc., can be used to distinguish different categories or groups of elements. For the sake of brevity, the terms "first," "second," etc., may respectively represent "first class (or first group)," "second class (or second group)," etc.

[0051] The word "connected" can mean "electrically connected" or "electrically connected without an intermediary transistor." The word "insulated" can mean "electrically insulated" or "electrically isolated." The word "conducted" can mean "conductive." The word "drive" can mean "operation" or "control." The word "comprises" can mean "composed of." The word "compensate" can mean "adjust." The word "part" can mean "section." The word "extend" can mean "having its longitudinal direction" or "is longitudinal." The word "pattern" can mean "component." The word "plan view" can mean "plan view of a display device."

[0052] Figure 1 This is a plan view of the display device 1 according to the embodiment. Figure 2 This is a side view of the display device 1 according to the embodiment. Figure 2 The display device 1 is shown in a bent state.

[0053] Display device 1 can display moving or still images according to input signals. Display device 1 can be used as a display screen for a variety of products such as televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs).

[0054] The display device 1 may have a substantially rectangular shape in the plan view. The display device 1 may have rounded corners in the plan view.

[0055] In the accompanying drawings, the first direction DR1 indicates the horizontal direction in the plan view of the display device 1, the second direction DR2 indicates the vertical direction in the plan view of the display device 1, and the third direction DR3 indicates the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 may be perpendicular to each other, and the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0056] Unless otherwise specified, the terms “upper,” “upper surface,” and “upper side” may be based on the third-party direction of DR3 toward the display surface of display panel 10, and the terms “lower,” “lower surface,” and “lower side” may be based on the third-party direction of DR3 toward the side of display panel 10 opposite to the display surface of display panel 10.

[0057] The display device 1 may have a short side and a long side. The short side of the display device 1 may extend in a first direction DR1. The long side of the display device 1 may extend in a second direction DR2. In the plan view of the display device 1, the display device 1 may have one or more of the following shapes: circular, elliptical, and others.

[0058] The display device 1 may include a display panel 10. The display panel 10 may include a flexible substrate, wherein the flexible substrate includes a flexible polymer material, such as polyimide. Therefore, the display panel 10 may be warped, bent, folded, or rolled.

[0059] Display panel 10 may be / include an organic light-emitting display panel. Display panel 10 may be / include one or more of liquid crystal display (LCD) panels, quantum dot organic light-emitting display (QD-OLED) panels, quantum dot liquid crystal display (QD-LCD) panels, quantum nano-light-emitting display panels, and micro light-emitting diodes.

[0060] The display panel 10 may include a display area DA on which an image is displayed according to an input signal, and may also include a non-display area NDA on which no image is displayed according to an input signal. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may form a border.

[0061] The display area DA may have a rectangular shape with right-angled corners or rounded corners. The display area DA may have a short side and a long side. The short side of the display area DA may extend in a first direction DR1. The long side of the display area DA may extend in a second direction DR2. The display area DA may have a circular shape, an elliptical shape, and / or other shapes.

[0062] The display area DA may include multiple pixels. The pixels may be arranged in a matrix. Each pixel may include an emissive layer and a circuit layer that controls the amount of light emitted from the emissive layer. The circuit layer may include lines, electrodes, and at least one transistor. The emissive layer may include an organic light-emitting material. The emissive layer may be sealed by an encapsulation layer.

[0063] The non-display area NDA can be arranged adjacent to the short and long sides of the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can exist on fewer than four sides of the display area DA.

[0064] The display panel 10 may include a main region MA and a curved region BA connected to one side of the main region MA in a second direction DR2. The display panel 10 may also include a sub-region SA connected to one side of the curved region BA in the second direction DR2 and (after the curved region BA has been curved) overlapping the main region MA in a third direction DR3.

[0065] The display area DA may be located within the main area MA. The non-display area NDA may include a portion of the main area MA located at the edge of the display area DA, and may also include portions located within the curved area BA and the sub-area SA.

[0066] The main area MA may have a shape similar to the planar appearance of the display device 1. The main area MA may be substantially flat. The main area MA may include one or more bent surfaces and / or one or more curved structures.

[0067] In the main region MA, if at least one of the edges (other than the edge connected to the curved region BA) is curved, the display region DA may extend to the curved region and / or a portion of the non-display region NDA may be arranged at the curved region.

[0068] The non-display area NDA of the main area MA can extend from the outer boundary of the display area DA to the edge of the display panel 10. In the main area MA, signal lines or drive circuits for applying signals to the display area DA can be arranged in the non-display area NDA.

[0069] The curved region BA can be connected to a short side of the main region MA. The width of the curved region BA in the first direction DR1 can be smaller than the width of the main region MA in the first direction DR1. The connection between the main region MA and the curved region BA can have an L-shaped cutout to reduce the width of the border.

[0070] The curved area BA can be curved at a certain curvature. After the display panel 10 has been curved at the curved area BA, the main area MA can overlap with the sub-area SA.

[0071] Sub-region SA may overlap with main region MA in the thickness direction (e.g., third direction DR3) of display panel 10. Sub-region SA may overlap with a portion of non-display region NDA and a portion of display region DA near the edge of main region MA. The width of sub-region SA in the first direction DR1 may be the same as the width of curved region BA in the first direction DR1.

[0072] Pads (not shown) may be arranged on a sub-region SA of the display panel 10. One or more external devices may be mounted (or attached) to the pads (not shown). Examples of the external devices may include a driver chip 20 and a driver substrate 30, such as a flexible or rigid printed circuit board. Wire connection films, connectors, etc., may be mounted on the pads. The driver chip 20 may be substantially arranged on the sub-region SA of the display panel 10, and the driver substrate 30 may partially overlap with and be attached to an end of the sub-region SA. The display panel 10 may include both pads connected to the driver chip 20 and pads connected to the driver substrate 30. The driver chip 20 may be mounted on a film, and the film may be attached to the sub-region SA of the display panel 10.

[0073] The driver chip 20 can be mounted on a surface of the display panel 10 that is coplanar with the display surface of the display panel 10 before the display panel 10 is bent. After the bending region BA is bent, the surface on which the driver chip 20 is mounted can be opposite the display surface of the display panel 10.

[0074] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive film or by ultrasonic bonding. The driver chip 20 may be narrower than the display panel 10 in the first direction DR1. The driver chip 20 may be arranged at the center of the sub-region SA in the first direction DR1, and the left and right edges of the driver chip 20 may be spaced apart from the left and right edges of the sub-region SA, respectively.

[0075] The driver chip 20 may include an integrated circuit that drives the display panel 10. The integrated circuit may be a data driver integrated circuit that generates and provides data signals. The driver chip 20 may be connected to line pads (not shown) provided in a pad group of the display panel 10 to provide data signals to the line pads (not shown). Lines connected to the line pads (not shown) may extend to the display area DA to apply data signals to the pixels in the display area DA.

[0076] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0077] Reference Figure 3 The circuitry for one pixel of an organic light-emitting display device includes an organic light-emitting diode (OLED), multiple transistors T1 to T7, a capacitor Cst, and a leakage prevention diode LD. Data signals DATA, GW (first scan signal), GI (second scan signal), GB (third scan signal), EM (light emission control signal), ELVDD (first power supply voltage), ELVSS (second power supply voltage), and VINT (initialization voltage) are applied to the circuitry of one pixel via corresponding wires.

[0078] An organic light-emitting diode (OLED) includes an anode (or a first electrode) and a cathode (or a second electrode). A capacitor (Cst) includes a first electrode and a second electrode. A leakage-prevention diode (LD) includes a first electrode (or an anode) and a second electrode (cathode).

[0079] Each of transistors T1 to T7 includes a gate electrode, a first source / drain electrode (or a first electrode), and a second source / drain electrode (or a second electrode). One of the first source / drain electrode and the second source / drain electrode is a source electrode, and the other is a drain electrode.

[0080] Each of transistors T1 through T7 can be a thin-film transistor. Each of transistors T1 through T7 can be either a PMOS transistor or an NMOS transistor. Each of the following transistors can be a PMOS transistor: the first transistor T1 (driving transistor), the second transistor T2 (data transmission transistor), the third transistor T3 (compensation transistor), the fifth transistor T5 (first light emission control transistor), the sixth transistor T6 (second light emission control transistor), and the seventh transistor T7 (second initialization transistor). The fourth transistor T4 (first initialization transistor) can be an NMOS transistor.

[0081] The gate electrode of the first transistor T1 is connected to each of the first electrode of the capacitor Cst and the second electrode of the leakage prevention diode LD. The first source / drain electrode of the first transistor T1 is connected to the first power supply voltage ELVDD terminal / line through the fifth transistor T5. The second source / drain electrode of the first transistor T1 is connected to the anode of the organic light-emitting diode OLED through the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2 and supplies drive current to the organic light-emitting diode OLED.

[0082] The gate electrode of the second transistor T2 is connected to the first scan signal GW terminal / line. The first source / drain electrode of the second transistor T2 is connected to the data signal DATA terminal / line. The second source / drain electrode of the second transistor T2 is connected to the first source / drain electrode of the first transistor T1, and is connected to the first power supply voltage ELVDD terminal / line through the fifth transistor T5. The second transistor T2 is turned on according to the first scan signal GW to perform a switching operation to send the data signal DATA to the first source / drain electrode of the first transistor T1.

[0083] The gate electrode of the third transistor T3 is connected to the first scan signal GW terminal / line. The first source / drain electrode of the third transistor T3 is connected to the second source / drain electrode of the first transistor T1, and is connected to the anode of the organic light-emitting diode (OLED) through the sixth transistor T6. The second source / drain electrode of the third transistor T3 is connected to the first electrode of the leakage prevention diode LD. The second source / drain electrode of the third transistor T3 is connected to the first electrode of the capacitor Cst, the first source / drain electrode of the fourth transistor T4, and the gate electrode of the first transistor T1 through the leakage prevention diode LD.

[0084] The third transistor T3 is turned on by the first scan signal GW to connect the gate electrode and the second source / drain electrode of the first transistor T1, thereby connecting the first transistor T1 as a diode. Therefore, a voltage difference may occur between the first electrode and the gate electrode of the first transistor T1 due to the threshold voltage of the first transistor T1, and the threshold voltage compensation / adjustment data signal DATA can be supplied to the gate electrode of the first transistor T1 to compensate for the threshold voltage deviation of the first transistor T1.

[0085] Since the third transistor T3 is a PMOS transistor, it can have a higher electron mobility than an NMOS transistor. Therefore, even in high-speed driving environments of 120Hz or higher, the threshold voltage deviation of the first transistor T1 can be easily compensated.

[0086] The gate electrode of the fourth transistor T4 is connected to the second scan signal GI terminal / line. The second source / drain electrode of the fourth transistor T4 is connected to the initialization voltage VINT terminal / line. The first source / drain electrode of the fourth transistor T4 is connected to each of the first electrode of the capacitor Cst, the second electrode of the leakage prevention diode LD, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on according to the second scan signal GI to send the initialization voltage VINT to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

[0087] Since the fourth transistor T4 is an NMOS transistor with relatively excellent turn-off characteristics, leakage of drive current during the light emission period of the organic light-emitting diode (OLED) can be minimized or prevented, and leakage of current sent to the gate electrode of the first transistor T1 can also be minimized or prevented.

[0088] The gate electrode of the fifth transistor T5 is connected to the optical emission control signal EM terminal / line. The first source / drain electrode of the fifth transistor T5 is connected to the first power supply voltage ELVDD terminal / line. The second source / drain electrode of the fifth transistor T5 is connected to the first source / drain electrode of the first transistor T1 and the second source / drain electrode of the second transistor T2.

[0089] The gate electrode of the sixth transistor T6 is connected to the light emission control signal EM terminal / line. The first source / drain electrode of the sixth transistor T6 is connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the third transistor T3. The second source / drain electrode of the sixth transistor T6 is connected to the anode of the organic light-emitting diode (OLED).

[0090] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM, and thus, the driving current flows through the organic light-emitting diode OLED.

[0091] The gate electrode of the seventh transistor T7 is connected to the third scan signal GB terminal / line. The first source / drain electrode of the seventh transistor T7 is connected to the anode of the organic light-emitting diode (OLED). The second source / drain electrode of the seventh transistor T7 is connected to the initialization voltage VINT terminal / line. The seventh transistor T7 is turned on according to the third scan signal GB to initialize the anode of the OLED.

[0092] In some embodiments, the gate electrode of the seventh transistor T7 may receive a third scan signal GB. In some embodiments, the gate electrode of the seventh transistor T7 may receive a first scan signal from another pixel.

[0093] The second electrode of capacitor Cst is connected to the first power supply voltage ELVDD terminal / line. The first electrode of capacitor Cst is connected to each of the gate electrode of the first transistor T1, the second electrode of the leakage prevention diode LD, and the first source / drain electrode of the fourth transistor T4. The cathode of the organic light-emitting diode OLED is connected to the second power supply voltage ELVSS terminal / line. The organic light-emitting diode OLED receives the drive current from the first transistor T1 and emits light for the display device to display an image.

[0094] The first electrode of the leakage prevention diode LD is connected to the second source / drain electrode of the third transistor T3. The second electrode of the leakage prevention diode LD is connected to each of the gate electrode of the first transistor T1, the first electrode of the capacitor Cst, and the first source / drain electrode of the fourth transistor T4. Because the leakage prevention diode LD is connected between the second source / drain electrode of the third transistor T3 and the gate electrode of the first transistor T1, leakage of the drive current during the light emission period of the organic light-emitting diode OLED can be minimized or prevented, and leakage of the current sent to the gate electrode of the first transistor T1 can also be minimized or prevented.

[0095] Figure 4 This is a layout diagram of a pixel of a display device according to an embodiment. Figure 5 According to the implementation method Figure 4 The layout diagram of the first and second semiconductor layers. Figure 6 and Figure 7 Each of these is a cross-sectional view of a display device according to an embodiment. Figure 6 An embodiment is shown. Figure 4 The cross-sections of the first transistor T1 and the third transistor T3, and Figure 7 An embodiment is shown. Figure 4 The cross-section of the fourth transistor T4 and the leakage prevention diode LD.

[0096] Reference Figures 3 to 7 The pixels include transistors T1 to T7, storage capacitor Cst, and organic light-emitting diodes (OLEDs).

[0097] Each of transistors T1 to T7 includes a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. Each of transistors T1 to T7 may be a top-gate transistor with its gate electrode disposed above the semiconductor layer. The semiconductor layers of PMOS transistors T1, T2, T3, T5, T6, and T7 may be arranged closer to or further away from the substrate SUB than the semiconductor layer of NMOS transistor T4, and may include materials different from those of the semiconductor layer of NMOS transistor T4.

[0098] A storage capacitor (Cst) includes conductive layers forming electrodes and insulating layers disposed between the conductive layers. An organic light-emitting diode (OLED) includes conductive layers forming an anode and a cathode, and an organic light-emitting layer disposed between the two electrodes. A leakage-prevention diode (LD) includes conductive layers forming a first electrode and a second electrode, and an insulating layer disposed between the two electrodes.

[0099] Electrical connections of components can be performed via a set of wiring made of one or more conductive layers and / or a set of vias made of one or more conductive materials. The aforementioned conductive materials, conductive layers, semiconductor layers, insulating layers, organic light-emitting layers, etc., are arranged on the substrate SUB.

[0100] The pixel layers can be arranged in the following order: substrate (SUB), barrier layer (BA), buffer layer (BF), first semiconductor layer (100), first gate insulating layer (GI1), first conductive layer (200), second gate insulating layer (GI2), second conductive layer (300), first interlayer insulating layer (ILD1), second semiconductor layer (400), third gate insulating layer (GI3), third conductive layer (500), second interlayer insulating layer (ILD2), fourth conductive layer (600), first via layer (VIA1), fifth conductive layer (700), second via layer (VIA2), anode (ANO) of the organic light-emitting diode (OLED), pixel defining layer (PDL), light-emitting layer (EL), and cathode (CAT) of the organic light-emitting diode (OLED). Each of the above layers can be a single layer or a stack of multiple layers. One or more additional layers may also be arranged between the layers.

[0101] The substrate SUB supports the aforementioned layers. When the display device is a rear-emitting or double-sided light-emitting display device, a transparent substrate can be used. When the display device is a front-emitting display device, not only a transparent substrate but also a translucent or opaque substrate can be used.

[0102] The substrate SUB can be made of an insulating material such as glass, quartz, or polymer resin. Examples of polymer resins include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. The substrate SUB may also include metallic materials.

[0103] The substrate SUB can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. An example of a material constituting a flexible substrate is polyimide (PI).

[0104] The barrier layer BA can be disposed on the substrate SUB. The barrier layer BA prevents the diffusion of impurity ions, prevents the penetration of moisture or outside air, and performs surface planarization. The barrier layer BA may include silicon nitride, silicon oxide, or silicon oxynitride. The barrier layer BA may be optional depending on the type of substrate SUB or process conditions.

[0105] A buffer layer (BF) may be disposed on the barrier layer (BA). The buffer layer (BF) can planarize the upper part of the substrate (SUB) and improve the adhesion of components disposed on the buffer layer (BF). The buffer layer (BF) may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The buffer layer (BF) may be optional depending on the type of substrate (SUB) or process conditions.

[0106] A first semiconductor layer 100 may be disposed on a buffer layer BF. The first semiconductor layer 100 may include an active layer providing channels for a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first semiconductor layer 100 may include an active layer ACT1 for the first transistor T1 and an active layer ACT3 for the third transistor T3. The first semiconductor layer 100 may include active layers for the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0107] A first semiconductor layer 100 included in one pixel may be separable from a first semiconductor layer 100 included in another pixel. The first semiconductor layer 100 may have a specific pattern in a planar view. For example, the first semiconductor layer 100 may include a first vertical portion 110, a second vertical portion 120, and a third vertical portion 160 extending substantially in a second direction DR2; and may include a first horizontal portion 130, a second horizontal portion 140, and a third horizontal portion 150 extending substantially in a first direction DR1. The first vertical portion 110, the second vertical portion 120, the third vertical portion 160, the first horizontal portion 130, the second horizontal portion 140, and the third horizontal portion 150 may be physically connected to each other.

[0108] The first vertical portion 110 may be arranged adjacent to / close to the left side of the pixel, and the second vertical portion 120 may be arranged adjacent to / close to the right side of the pixel. The first vertical portion 110 and the second vertical portion 120 may be spaced apart from each other. In the second direction DR2, the first vertical portion 110 may be longer than the second vertical portion 120.

[0109] The first horizontal portion 130 can connect to the first vertical portion 110 and the second vertical portion 120. The first horizontal portion 130 can connect the first vertical portion 110 and the second vertical portion 120 with the shortest possible length. The first horizontal portion 130 may include a first curved portion 131 on the left side of the first horizontal portion 130 and a second curved portion 132 on the right side of the first horizontal portion 130. The total length of the first horizontal portion 130 can be increased by including more curves in the first horizontal portion 130.

[0110] The upper portion 111 of the first vertical portion 110 and the upper portion 121 of the second vertical portion 120 may be positioned further away from the bending region BA than the first horizontal portion 130. The lower portion 112 of the first vertical portion 110 and the lower portion 122 of the second vertical portion 120 may be positioned closer to the bending region BA than the first horizontal portion 130.

[0111] The second horizontal portion 140 may extend from the lower portion 112 of the first vertical portion 110 in the first direction DR1. The third horizontal portion 150 may extend from the lower portion 122 of the second vertical portion 120 in the first direction DR1. The second horizontal portion 140 and the third horizontal portion 150 may face each other and be substantially aligned with each other. The third vertical portion 160 may extend from the third horizontal portion 150 in the second direction DR2. The third vertical portion 160 may protrude from the third horizontal portion 150 toward the curved region BA.

[0112] The channel of the first transistor T1 can be arranged in the first horizontal portion 130. The channel of the second transistor T2 can be arranged in the upper portion 111 of the first vertical portion 110, and the channel of the fifth transistor T5 can be arranged in the lower portion 112 of the first vertical portion 110. The channel of the third transistor T3 can be arranged in the upper portion 121 of the second vertical portion 120, and the channel of the sixth transistor T6 can be arranged in the lower portion 122 of the second vertical portion 120. The channel of the seventh transistor T7 can be arranged in the third vertical portion 160.

[0113] The first semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon can be formed by crystallizing amorphous silicon. Examples of crystallization methods may include rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and sequential lateral solidification (SLS). The first semiconductor layer 100 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, etc.

[0114] In the first semiconductor layer 100, each source / drain region (source / drain region) connected to each of transistors T1, T2, T3, T5, T6, and T7 may be doped with impurity ions (e.g., p-type impurity ions for each PMOS transistor). For example, a trivalent dopant such as boron (B) may be used as a p-type impurity ion.

[0115] The active layer ACT3 of the third transistor T3 and the active layer ACT1 of the first transistor T1 can be directly disposed on the same surface (or face) of the buffer layer BF, and can be included in the first semiconductor layer 100. Since the active layer ACT3 of the third transistor T3 is part of the first semiconductor layer 100, the active layer ACT3 of the third transistor T3 can include polysilicon.

[0116] The third transistor T3 may have a higher electron mobility than transistors including oxide semiconductors, and may smoothly compensate for the threshold voltage deviation of the first transistor T1 even when a pixel is operating in a high-speed driving environment of 120Hz or higher.

[0117] A first gate insulating layer GI1 may be disposed on the first semiconductor layer 100 and may be disposed over the entire surface of the substrate SUB. The first gate insulating layer GI1 may be a gate insulating layer used to insulate the gate electrode from the active layer.

[0118] The first gate insulating layer GI1 may include silicon compounds, metal oxides, etc. For example, the first gate insulating layer GI1 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide, used alone or in combination.

[0119] The first conductive layer 200 is disposed on the first gate insulating layer GI1. The first conductive layer 200 may include a first scan line 210 for transmitting a first scan signal GW, a first optical emission control line 220 for transmitting an optical emission control signal EM, a third scan line 230 for supplying a third scan signal GB, and a gate electrode 240 of the first transistor T1.

[0120] The first scan line 210 includes the gate electrode of the second transistor T2 and the gate electrode GAT3 of the third transistor T3. The first light emission control line 220 may include the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. The third scan line 230 may include the gate electrode of the seventh transistor T7.

[0121] Each of the first scan line 210, the first light emission control line 220, and the third scan line 230 may extend in the first direction DR1. Each of the first scan line 210, the first light emission control line 220, and the third scan line 230 may extend beyond the pixel boundary to an adjacent pixel in the first direction DR1.

[0122] The first scan line 210 may be located at / near the center of the pixel. The first scan line 210 may overlap with the upper portion 111 of the first vertical portion 110 and the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100, and the gate electrode of the second transistor T2 and the gate electrode GAT3 of the third transistor T3 may be formed at the corresponding overlapping portions.

[0123] A first portion of the first vertical portion 110 of the first semiconductor layer 100 may be positioned further away from the curved region BA than the overlap between the first scan line 210 and the upper portion 111 of the first vertical portion 110, and may be the first electrode region of the second transistor T2. A second portion of the first vertical portion 110 of the first semiconductor layer 100 may be positioned closer to the curved region BA than the overlap between the first scan line 210 and the upper portion 111 of the first vertical portion 110, and may be the second electrode region of the second transistor T2. A first portion of the second vertical portion 120 of the first semiconductor layer 100 may be positioned closer to the curved region BA than the overlap between the first scan line 210 and the upper portion 121 of the second vertical portion 120, and may be the first electrode region of the third transistor T3. A second portion of the second vertical portion 120 of the first semiconductor layer 100 may be positioned further away from the curved region BA than the overlap between the first scan line 210 and the upper portion 121 of the second vertical portion 120, and may be the second electrode region of the third transistor T3.

[0124] The first light emission control line 220 can be positioned closer to the curved region BA than the first scan line 210, and can overlap with the lower part 112 of the first vertical portion 110 of the first semiconductor layer 100 and the lower part 122 of the second vertical portion 120 of the first semiconductor layer 100.

[0125] The first light emission control line 220 may form the gate electrode of the fifth transistor T5 at the portion overlapping with the lower portion 112 of the first vertical portion 110 of the first semiconductor layer 100. A portion of the first vertical portion 110 of the first semiconductor layer 100 may be positioned further away from the bending region BA than the overlapping portion and may be the second electrode region of the fifth transistor T5. A portion of the first vertical portion 110 of the first semiconductor layer 100 may be closer to the bending region BA than the overlapping portion and may be the first electrode region of the fifth transistor T5.

[0126] The first light emission control line 220 may form the gate electrode of the sixth transistor T6 at the portion overlapping with the lower portion 122 of the second vertical portion 120 of the first semiconductor layer 100. A portion of the second vertical portion 120 of the first semiconductor layer 100 may be positioned further away from the bending region BA than the overlapping portion and may be the first electrode region of the sixth transistor T6. A portion of the second vertical portion 120 of the first semiconductor layer 100 may be positioned closer to the bending region BA than the overlapping portion and may be the second electrode region of the sixth transistor T6.

[0127] The third scan line 230 may be positioned closer to the curved region BA than the first light emission control line 220. The third scan line 230 may overlap with the third vertical portion 160 of the first semiconductor layer 100. The third scan line 230 may form the gate electrode of the seventh transistor T7 at the portion overlapping with the third vertical portion 160 of the first semiconductor layer 100. A portion of the third vertical portion 160 of the first semiconductor layer 100 may be positioned further away from the curved region BA than the overlapping portion, and may constitute the first electrode region of the seventh transistor T7. A portion of the third vertical portion 160 of the first semiconductor layer 100 may be positioned closer to the curved region BA than the overlapping portion, and may constitute the second electrode region of the seventh transistor T7.

[0128] The gate electrode 240 of the first transistor T1 may be located at / near the center of the pixel. In a plan view, the gate electrode 240 of the first transistor T1 may be located between the first scan line 210 and the first light emission control line 220. The gate electrodes 240 of the first transistor T1 for different pixels may be spaced apart from each other.

[0129] The gate electrode 240 of the first transistor T1 overlaps with the first horizontal portion 130 of the first semiconductor layer 100. A portion of the first horizontal portion 130 of the first semiconductor layer 100 may be positioned closer to the first vertical portion 110 than the overlapping portion, and may be the first electrode region of the first transistor T1. A portion of the first horizontal portion 130 of the first semiconductor layer 100 may be positioned closer to the second vertical portion 120 than the overlapping portion, and may be the second electrode region of the first transistor T1.

[0130] The first conductive layer 200 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0131] The second gate insulating layer GI2 may be disposed on the first conductive layer 200 and may be disposed over the entire surface of the substrate SUB. The second gate insulating layer GI2 may insulate the first conductive layer 200 from the second conductive layer 300. The second gate insulating layer GI2 may be an interlayer insulating layer. The second gate insulating layer GI2 may comprise a material substantially the same as the first gate insulating layer GI1.

[0132] The second conductive layer 300 is disposed directly on the second gate insulating layer GI2. The second conductive layer 300 may include the first electrode 310 of the leakage prevention diode LD and the second electrode 320 of the storage capacitor Cst.

[0133] The first electrode 310 of the leakage prevention diode LD can be positioned further away from the bending region BA than the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100. In a plan view, the first electrode 310 of the leakage prevention diode LD can be located on the right side of the pixel. The first electrodes 310 of the leakage prevention diodes LD of different pixels can be spaced apart from each other.

[0134] The second electrode 320 of the storage capacitor Cst may be located at / near the center of the pixel. In a plan view, the second electrode 320 of the storage capacitor Cst may be located between the first scan line 210 and the first light emission control line 220. The second electrodes 320 of the storage capacitors Cst of different pixels may be spaced apart from each other.

[0135] The second electrode 320 of the storage capacitor Cst may overlap with the gate electrode 240 of the first transistor T1 on the third-direction DR3. The gate electrode 240 of the first transistor T1 may extend from a region overlapping with the first semiconductor layer 100 to form a first electrode of the storage capacitor Cst that overlaps with the second electrode 320 of the storage capacitor Cst on the third-direction DR3. The gate electrode 240 of the first transistor T1 may be directly connected to the first electrode of the storage capacitor Cst. The first electrode of the storage capacitor Cst may be a portion of the gate electrode 240 of the first transistor T1, or it may be a portion extending from the upper portion 111. The second electrode 320 of the storage capacitor Cst may include an opening that partially exposes the gate electrode 240 of the first transistor T1.

[0136] A first interlayer insulating layer ILD1 may be disposed on the second conductive layer 300 to cover the second conductive layer 300. The first interlayer insulating layer ILD1 may be disposed over the entire surface of the substrate SUB. The first interlayer insulating layer ILD1 may insulate the second conductive layer 300 from the second semiconductor layer 400. The first interlayer insulating layer ILD1 may be an interlayer insulating layer. The thickness of the first interlayer insulating layer ILD1 on the third-direction DR3 may be less than or equal to 100 nm. For example, the thickness of the first interlayer insulating layer ILD1 may be in the range of 1 nm to 100 nm, in the range of 20 nm to 80 nm, or in the range of 40 nm to 60 nm.

[0137] The first interlayer insulating layer ILD1 may include silicon compounds, metal oxides, etc. The first interlayer insulating layer ILD1 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide, used alone or in combination.

[0138] A second semiconductor layer 400 is disposed on the first interlayer insulating layer ILD1. The second semiconductor layer 400 may include an active layer ACT4 that provides a channel for a fourth transistor T4.

[0139] The second semiconductor layer 400 may include an oxide semiconductor. For example, the second semiconductor layer 400 may include a two-component compound (AB) comprising one or more of indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and magnesium (Mg). x ), three-component compound (AB) x C y ) and four-component compounds (AB) x C y D z In an embodiment, the second semiconductor layer 400 may include ITZO (an oxide comprising indium, tin, and titanium) or IZO (an oxide comprising indium, gallium, and tin).

[0140] Most of the second semiconductor layer 400 may be doped with impurity ions (e.g., n-type impurity ions for NMOS transistors). For example, trivalent dopants such as phosphorus (P) can be used as n-type impurity ions. Therefore, most of the second semiconductor layer 400 doped with n-type impurity ions can have low resistance and high conductivity, and thus behave like a conductive material. In the second semiconductor layer 400, the channel region of the fourth transistor T4 may be undoped, or may have a relatively small doping concentration.

[0141] The second semiconductor layers 400 for different pixels may be spaced apart from each other. In a plan view, the second semiconductor layers 400 may be arranged further away from the curved region BA than the first semiconductor layer 100. The second semiconductor layers 400 may have a specific pattern / structure in the plan view. For example, the second semiconductor layer 400 may include a horizontal portion 410 extending in the first direction DR1, and may include a vertical portion 420 extending from one end of the horizontal portion 410 in the second direction DR2.

[0142] The channel of the fourth transistor T4 may be the portion of the vertical portion 420 of the second semiconductor layer 400 that overlaps with the gate electrode of the fourth transistor T4. The horizontal portion 410 of the second semiconductor layer 400 may overlap with the first electrode 310 of the leakage prevention diode LD on the third-direction DR3. The portion of the horizontal portion 410 of the second semiconductor layer 400 that overlaps with the first electrode 310 of the leakage prevention diode LD may include / be the second electrode 411 of the leakage prevention diode LD. The first interlayer insulating layer ILD1 may be located between the first electrode 310 and the second electrode 411 of the leakage prevention diode LD.

[0143] Figure 8 According to the implementation method Figure 7 An enlarged view of region A in the image. Figure 8 A cross-sectional view of a leakage prevention diode LD is shown.

[0144] Reference Figure 8The display panel 10 may further include an interface layer IF. The interface layer IF may be disposed between the second semiconductor layer 400 and the first interlayer insulating layer ILD1. The interface layer IF controls the movement of electrons in the second semiconductor layer 400 to the first electrode 310 of the leakage prevention diode LD. The thickness of the interface layer IF may be less than or equal to 15 nm. For example, the thickness of the interface layer IF may be in the range of 1 nm to 15 nm, or in the range of 10 nm to 12 nm.

[0145] The interface layer IF can be formed by heat treatment or ultraviolet treatment of the second semiconductor layer 400. For example, the temperature for performing heat treatment can be in the range of 25°C to 350°C, or in the range of 200°C to 350°C. When the heat treatment temperature is 25°C or higher or 200°C or higher, the interface layer IF can be easily formed, and when the heat treatment temperature is 350°C or lower, the device will not degrade even if heat treatment is performed. For example, in ultraviolet treatment, ultraviolet light with wavelength bands of 185nm and 245nm can be mixed and used.

[0146] Through heat treatment or ultraviolet treatment, metal elements in the second semiconductor layer 400 can migrate towards the interface layer IF, and oxygen in the second semiconductor layer 400 can migrate in the opposite direction to the interface layer IF. As the metal elements approach the interface layer IF, the concentration of the metal elements in the second semiconductor layer 400 increases, and the metal concentration at and near the interface layer IF can be relatively high. The oxygen concentration in the second semiconductor layer 400 can decrease as it approaches the interface layer IF.

[0147] A leakage prevention diode (LD) may include a first electrode 310, a first interlayer insulating layer (ILD1), an interface layer (IF), and a second electrode 411. In the leakage prevention diode LD, rectification characteristics occur between the first interlayer insulating layer (ILD1) and the second semiconductor layer 400 (or the second electrode 411). For example, when a positive (+) voltage is applied to the second semiconductor layer 400 and a negative (-) voltage is applied to the first interlayer insulating layer (ILD1), no current flows; however, when a negative (-) voltage is applied to the second semiconductor layer 400 and a positive (+) voltage is applied to the first interlayer insulating layer (ILD1), current flows to exhibit rectification characteristics.

[0148] In a leakage-prevention diode (LD), electrons can move via Fowler-Nordheim tunneling. Fowler-Nordheim tunneling is one of the tunneling mechanisms by which electrons can move from a metal-insulator-metal layer to an upper / lower metal layer. It refers to the movement of electrons from the upper metal layer to the lower metal layer through a shorter path because the thickness of the insulator becomes thinner when an electric field of a certain magnitude or greater is applied to the insulator. The first electrode 310 of the leakage-prevention diode LD comprises metal, and the second electrode 411 comprises an oxide semiconductor. The tunneling mechanism can be applied to the second electrode 411 of the leakage-prevention diode LD because it is doped with n-type impurity ions and has high conductivity.

[0149] Figure 9 An energy band diagram of a leakage prevention diode according to an embodiment is shown.

[0150] Reference Figure 9 The interface layer IF can be formed by heat treatment or ultraviolet treatment. When heat treatment or ultraviolet treatment is performed, an interface layer IF with a smaller bandgap energy than the first interlayer insulating layer ILD1 is formed between the first interlayer insulating layer ILD1 and the second electrode 411 of the leakage prevention diode LD.

[0151] In a leakage prevention diode (LD), because the offset OFS is reduced by the interface layer IF, current can flow from the first electrode 310 to the second electrode 411 of the leakage prevention diode LD when a voltage is applied. The magnitude of the offset OFS between the first interlayer insulating layer ILD1 and the second electrode 411 of the leakage prevention diode LD can be reduced by the interface layer IF, and therefore electrons in the second electrode 411 of the leakage prevention diode LD can move to the first electrode 310 of the leakage prevention diode LD.

[0152] Depending on the degree of electron trapping, the offset OFS between the interface layer IF and the first interlayer insulating layer ILD1 can range from 0.6 eV to 1.5 eV. For example, the offset OFS between the interface layer IF and the first interlayer insulating layer ILD1 can be 0.6 eV. The interface layer IF can have an electron affinity of 1.5 eV, the first interlayer insulating layer ILD1 can have an electron affinity of 0.9 eV, the first electrode 310 of the leakage prevention diode LD can have an electron affinity of 4.5 eV, and the second electrode 411 of the leakage prevention diode LD can have an electron affinity of 4.4 eV. The offset (not shown) between the second electrode 411 of the leakage prevention diode LD and the interface layer IF can be 2.9 eV.

[0153] Therefore, since the offset OFS between the first interlayer insulating layer ILD1 and the second electrode 411 of the leakage prevention diode LD is reduced to 0.6 eV by the interface layer IF, electrons can easily move to the first electrode 310 of the leakage prevention diode LD when a voltage is applied, due to the small barrier height of 0.6 eV. The offset OFS between the interface layer IF and the first interlayer insulating layer ILD1 can have a value between the value associated with the second electrode 411 of the leakage prevention diode LD and the value associated with the first interlayer insulating layer ILD1.

[0154] The leakage prevention diode LD may have a metal-semiconductor-insulator-metal (MSIM) structure, and the interface layer IF facilitates electron movement under positive bias conditions. The interface layer IF enables / facilitates direct tunneling and / or FN tunneling. Furthermore, by changing the thickness and material of the first interlayer insulating layer ILD1 and the second electrode 411 of the leakage prevention diode LD, the movement of electrons from the second electrode 411 of the leakage prevention diode LD to the first electrode 310 of the leakage prevention diode LD can be controlled.

[0155] Figure 10 This is a graph showing the change in current of a leakage prevention diode relative to a bias voltage according to an embodiment, wherein the first interlayer insulating layer ILD1 may comprise silicon oxide (SiO2). x ), and the first interlayer insulating layer ILD1 may have a thickness of 60 nm and 40 nm. Figure 10 The solid line in the figure corresponds to the thickness of the first interlayer insulating layer ILD1, which is 60 nm. Figure 10 The dashed line in the figure corresponds to the thickness of the first interlayer insulating layer ILD1, which is 40 nm.

[0156] Reference Figure 10 When a positive bias (negative bias) based on 0V is applied to the second electrode 411 of the leakage prevention diode LD, the second electrode 411 is in an "accumulation" state, such that electrons are collected between the insulating layer (first interlayer insulating layer ILD1) and the second electrode 411 of the leakage prevention diode LD, and the collected electrons overflow the barrier of the insulating layer (first interlayer insulating layer ILD1) through the interface layer IF and move to the first electrode 310 (resulting in a conduction current from the first electrode 310 to the second electrode 411).

[0157] When a reverse bias (forward bias) based on 0V is applied to the second electrode 411 of the leakage prevention diode LD, the second electrode 411 is in a "depleted" state. Unlike the forward bias state, when electrons move from the first electrode 310 to the second electrode 411, there is no interface layer IF between the first electrode 310 and the insulating layer (first interlayer insulating layer ILD1), which prevents electron flow based on the resistance state of the insulating layer (first interlayer insulating layer ILD1) and the second electrode 411 of the leakage prevention diode LD in the depleted state (resulting in a minimum turn-off current from the second electrode 411 to the first electrode 310).

[0158] As the thickness of the insulating layer (first interlayer insulating layer ILD1) increases, the current value increases, resulting in an increase in the absolute value of Von (the voltage at which the diode is turned on), while simultaneously reducing the on / off current of the leakage prevention diode LD. The on / off current of the leakage prevention diode LD can be adjusted by configuring the thickness of the insulating layer (first interlayer insulating layer ILD1).

[0159] In the leakage prevention diode LD, current can flow only in one direction from the first electrode 310 of the leakage prevention diode LD toward the second electrode 411. Since the leakage prevention diode LD is arranged between the second source / drain electrode of the third transistor T3 and the gate electrode of the first transistor T1, leakage of the drive current during the light emission period of the organic light-emitting diode OLED can be minimized or prevented, and leakage of current intended for the gate electrode of the first transistor T1 can also be minimized or prevented. Therefore, even when the active layer ACT3 of the third transistor T3 includes a portion of the first semiconductor layer 100, the leakage prevention diode LD can minimize or prevent current leakage together with the fourth transistor T4.

[0160] Since the active layer ACT3 of the third transistor T3 includes a portion of the first semiconductor layer 100, the threshold voltage deviation of the first transistor T1 can be easily compensated even when the period during which the charging threshold voltage can be reduced in a high-speed driving environment of 120Hz or higher is shortened. Therefore, it is possible to minimize or prevent the display device 1 (refer to) operating in a high-speed driving environment of 120Hz or higher from being affected by the threshold voltage deviation. Figure 1 The brightness of the displayed image may be defective. Even when the active layer ACT3 of the third transistor T3 is part of the first semiconductor layer 100, current leakage can be more easily minimized or prevented by further providing a leakage prevention diode LD.

[0161] Leakage prevention diodes (LDs) can be driven under excessive reverse bias conditions, and LDs can also be used as electrostatic discharge (ESD) protection diodes.

[0162] The characteristics of the leakage prevention diode LD can be adjusted depending on the process conditions for forming the second semiconductor layer 400, the thickness of the insulating layer (first interlayer insulating layer ILD1), and the thickness of the second electrode 411 of the leakage prevention diode LD.

[0163] Figure 11 This includes graphs showing the variation of the leakage protection diode's current relative to the bias voltage, depending on process conditions. Figure 11 In the middle, curve Figure X Each of Y and Z relates to a leakage prevention diode LD with a thickness of 40 nm for the second electrode 411 (i.e., the thickness of the second semiconductor layer 400).

[0164] Reference Figure 11 For example, the second semiconductor layer 400 can be formed by physical vapor deposition (PVD) such as sputtering. The sputtering power can be maintained or changed during the stacking of the second semiconductor layer 400.

[0165] curve Figure X The diagram illustrates the case where the sputtering power is maintained at 40W during the stacking of the second semiconductor layer 400. Graph Y shows the case where the sputtering power increases from 20W to 40W during the stacking of the second semiconductor layer 400, and graph Z shows the case where the sputtering power decreases from 40W to 20W during the stacking of the second semiconductor layer 400. Graph Y shows the case where the lower portion of the second semiconductor layer 400 (with a thickness of 10nm) is formed by sputtering power of 20W, and the remaining upper portion of the second semiconductor layer 400 (with a thickness of 30nm) is formed by sputtering power of 40W. Graph Z shows the case where the lower portion of the second semiconductor layer 400 (with a thickness of 30nm) is formed by sputtering power of 40W, and the remaining upper portion of the second semiconductor layer 400 (with a thickness of 10nm) is formed by sputtering power of 20W.

[0166] curve Figure X Curve Z and curve Z generally tend to be significantly similar to each other / close to each other, but curve Y tends to be similar to curve Z. Figure X The curve Z is significantly different from / far away from the curve Y. Figure X The curve Z is negatively shifted. When the second electrode 411 of the leakage prevention diode LD is formed by sputtering, the on-off characteristics of the leakage prevention diode LD can be adjusted according to the sputtering power during the process of forming the portion of the second electrode 411 that is in direct contact with the first interlayer insulating layer ILD1 as an insulator. During the initial deposition of the second electrode 411 of the leakage prevention diode LD, the on-off characteristics of the leakage prevention diode LD can be adjusted according to the sputtering power.

[0167] Refer again Figures 4 to 7A third gate insulating layer GI3 is disposed on the second semiconductor layer 400. Unlike the first gate insulating layer GI1, the third gate insulating layer GI3 may only overlap the substrate SUB portion. The third gate insulating layer GI3 may cover the channel region of the fourth transistor T4 and may expose the first source / drain region and the second source / drain region of the fourth transistor T4 as well as the side surface of the second semiconductor layer 400. In a plan view, the third gate insulating layer GI3 may have a pattern shape substantially the same as that of the third conductive layer 500. The third gate insulating layer GI3 may comprise a material substantially the same as that of the first gate insulating layer GI1.

[0168] The third conductive layer 500 is disposed on the third gate insulating layer GI3. The third conductive layer 500 may include a transmit initialization voltage VINT (in Figure 3 The initialization line 510 and the sending of the second scan signal GI (in the middle) Figure 3 The second scan line 520 in the middle.

[0169] The initialization line 510 and the second scan line 520 may each extend along the first direction DR1. The initialization line 510 and the second scan line 520 may extend across the boundary between pixels along the first direction DR1 to adjacent pixels. The second scan line 520 may not overlap with the first semiconductor layer 100.

[0170] In a plan view, initialization line 510 may be positioned further away from the curved region BA than the first semiconductor layer 100. In a plan view, initialization line 510 may be positioned further away from the curved region BA than the first scan line 210. Within a pixel, initialization line 510 may include spaced-apart segments, and in a plan view, vertical portions 420 of the second semiconductor layer 400 may be positioned between the spaced segments of initialization line 510. Within a pixel, the spaced segments of initialization line 510 may be electrically connected via overlapping fifth data patterns / components 650.

[0171] The initialization line 510 may overlap with the third vertical portion 160 of the first semiconductor layer 100 on the third direction DR3. The third vertical portion 160 of the first semiconductor layer 100 may extend toward the curved region BA and may overlap with each of the third scan line 230 and the initialization line 510.

[0172] In the region where the initialization line 510 overlaps with the third vertical portion 160 of the first semiconductor layer 100 in the thickness direction (third direction DR3), the initialization line 510 can contact the third vertical portion 160 of the first semiconductor layer 100 through a contact hole CNT15 that passes through the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the third vertical portion 160 of the first semiconductor layer 100, or it can be contacted by the third vertical portion 160 of the first semiconductor layer 100. The initialization line 510 can be electrically connected to the third vertical portion 160 of the first semiconductor layer 100 through the contact hole CNT15.

[0173] In the plan view, the second scan line 520 can be positioned further away from the curved region BA than the first scan line 210. A portion of the second scan line 520 can overlap with the vertical portion 420 of the second semiconductor layer 400 and can form the gate electrode GAT4 of the fourth transistor T4. Based on the overlapping portion of the second scan line 520 and the vertical portion 420 of the second semiconductor layer 400, a portion of the vertical portion 420 of the second semiconductor layer 400 positioned further away from the curved region BA than the overlapping portion can become the second electrode region of the fourth transistor T4, and a portion of the vertical portion 420 of the second semiconductor layer 400 positioned closer to the curved region BA than the overlapping portion can become the first electrode region of the fourth transistor T4.

[0174] The third conductive layer 500 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0175] The second interlayer insulating layer ILD2 may be disposed on the third conductive layer 500 and may substantially / completely cover the surface of the third conductive layer 500. The second interlayer insulating layer ILD2 may substantially / completely overlap with the surface of the substrate SUB. The second interlayer insulating layer ILD2 may insulate the third conductive layer 500 from the fourth conductive layer 600. The second interlayer insulating layer ILD2 may be an interlayer insulating layer. The second interlayer insulating layer ILD2 may comprise a material substantially the same as the first interlayer insulating layer ILD1.

[0176] A fourth conductive layer 600 may be disposed on the second interlayer insulating layer ILD2. The fourth conductive layer 600 may include a first data pattern / component (or connection pattern / component) 610, a second data pattern / component (or connection pattern / component) 620, a third data pattern / component (or connection pattern / component) 630, a fourth data pattern / component (or connection pattern / component) 640, a fifth data pattern / component (or connection pattern / component) 650, and a sixth data pattern / component (or connection pattern / component) 660. The first data pattern / component 610, the second data pattern / component 620, the third data pattern / component 630, the fourth data pattern / component 640, the fifth data pattern / component 650, and the sixth data pattern / component 660 are physically spaced apart from each other. The first data pattern / component 610, the second data pattern / component 620, the third data pattern / component 630, the fourth data pattern / component 640, the fifth data pattern / component 650, and the sixth data pattern / component 660 may electrically connect the spaced-apart portions.

[0177] The fourth conductive layer 600 may include a first electrode and a second electrode for each of transistors T1 to T7. As an example, the fourth conductive layer 600 includes a first electrode SD11 and a second electrode SD12 for the first transistor T1, a first electrode SD31 and a second electrode SD32 for the third transistor T3, and a first electrode SD41 and a second electrode SD42 for the fourth transistor T4. Some of the data patterns / components may constitute at least one first electrode or a second electrode for each of transistors T1 to T7.

[0178] The first data pattern / component 610 may overlap with the gate electrode 240 of the first transistor T1. The first data pattern / component 610 may be electrically connected to the gate electrode 240 of the first transistor T1 through a contact hole CNT1 in the overlapping area. The contact hole CNT1 may be located in the opening of the second electrode 320 of the storage capacitor Cst. A portion of the first data pattern / component 610 inside the contact hole CNT1 may be insulated from the second electrode 320 of the storage capacitor Cst through the second interlayer insulating layer ILD2.

[0179] The first data pattern / component 610 may extend along the second direction DR2 from the overlapping region with the gate electrode 240 of the first transistor T1, may be insulated from the first scan line 210, may intersect the first scan line 210, and may overlap with and be insulated from the horizontal portion 410 of the second semiconductor layer 400. In the overlapping region, the first data pattern / component 610 may be electrically connected to the horizontal portion 410 of the second semiconductor layer 400 through a contact hole CNT2 that passes through the second interlayer insulating layer ILD2 and exposes the second semiconductor layer 400.

[0180] The second data pattern / component 620 may overlap with the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100. In the overlap region, the second data pattern / component 620 may be electrically connected to the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100 through a contact hole CNT3 that passes through the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the second gate insulating layer GI2 and the first gate insulating layer GI1 and exposes the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100.

[0181] The second data pattern / component 620 may extend in the second direction DR2 from the overlapping region with the upper portion 121 of the second vertical portion 120 of the first semiconductor layer 100, and may overlap with the first electrode 310 of the leakage prevention diode LD. In the overlapping region with the first electrode 310, the second data pattern / component 620 may be electrically connected to the first electrode 310 of the leakage prevention diode LD through a contact hole CNT4 that passes through the second interlayer insulating layer ILD2 and the first interlayer insulating layer ILD1 and exposes the first electrode 310 of the leakage prevention diode LD.

[0182] Therefore, the first semiconductor layer 100 can be electrically connected to the first electrode 310 of the leakage prevention diode LD via the second data pattern / component 620.

[0183] The third data pattern / component 630 may overlap with the upper portion 111 of the first vertical portion 110 of the underlying first semiconductor layer 100. In the overlap region, the third data pattern / component 630 may be electrically connected to the upper portion 111 of the first vertical portion 110 of the first semiconductor layer 100 through a contact hole CNT5 that passes through the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the second gate insulating layer GI2 and the first gate insulating layer GI1 and exposes the upper portion 111 of the first vertical portion 110 of the first semiconductor layer 100.

[0184] The third data pattern / component 630 may overlap with the overlying data line 720. In the overlap area, the data line 720 may be electrically connected to the third data pattern / component 630 through a contact hole CNT6 that passes through the first via layer VIA1 and exposes the third data pattern / component 630.

[0185] Therefore, the upper portion 111 of the first vertical portion 110 of the first semiconductor layer 100 can be electrically connected to the data line 720 via the third data pattern / component 630.

[0186] The fourth data pattern / component 640 may overlap with the second electrode 320 of the underlying storage capacitor Cst. In the overlap area, the fourth data pattern / component 640 may be electrically connected to the second electrode 320 of the storage capacitor Cst through a contact hole CNT7 that passes through the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1 and exposes the second electrode 320 of the storage capacitor Cst.

[0187] The fourth data pattern / component 640 may extend along the second direction DR2 from the overlapping region with the second electrode 320, may be insulated from the first light emission control line 220, and may intersect with the first light emission control line 220. The fourth data pattern / component 640 may overlap with the second horizontal portion 140 of the underlying first semiconductor layer 100. In the overlapping region, the fourth data pattern / component 640 may be electrically connected to the second horizontal portion 140 of the first semiconductor layer 100 through a contact hole CNT8 that passes through the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 and exposes the second horizontal portion 140 of the first semiconductor layer 100.

[0188] The fourth data pattern / component 640 may overlap with the overlying first power supply voltage line 710. In the overlap area, the fourth data pattern / component 640 may be electrically connected to the first power supply voltage line 710 through a contact hole CNT9 that passes through the first via layer VIA1 and exposes the fourth data pattern / component 640.

[0189] Therefore, each of the second electrode 320 of the storage capacitor Cst and the second horizontal portion 140 of the first semiconductor layer 100 can be electrically connected to the first power supply voltage line 710 via the fourth data pattern / component 640.

[0190] The fifth data pattern / component 650 may overlap with the vertical portion 420 of the underlying second semiconductor layer 400. In the overlap area, the fifth data pattern / component 650 may be electrically connected to the vertical portion 420 of the second semiconductor layer 400 through a contact hole CNT10 that passes through the second interlayer insulating layer ILD2 and exposes the vertical portion 420 of the second semiconductor layer 400.

[0191] The fifth data pattern / component 650 may extend in the first direction DR1 from the overlapping area with the vertical portion 420 and may overlap with the two separate segments of the initialization line 510. In the overlapping area with the two separate segments of the initialization line 510, the fifth data pattern / component 650 may be electrically connected to the two separate segments of the initialization line 510 respectively through contact holes CNT11 and CNT12 that pass through the second interlayer insulation layer ILD2 and expose the separate segments of the initialization line 510.

[0192] Therefore, the fifth data pattern / component 650 can be electrically connected to the separation section of the initialization line 510, and the initialization line 510 can be electrically connected to the vertical portion 420 of the second semiconductor layer 400.

[0193] The sixth data pattern / component 660 may overlap with the third horizontal portion 150 of the underlying first semiconductor layer 100. In the overlap region, the sixth data pattern / component 660 may be electrically connected to the third horizontal portion 150 of the first semiconductor layer 100 through a contact hole CNT13 that passes through the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the second gate insulating layer GI2 and the first gate insulating layer GI1 and exposes the third horizontal portion 150 of the first semiconductor layer 100.

[0194] The sixth data pattern / component 660 may extend in the second direction DR2 from the overlapping area with the third horizontal portion 150 and may overlap with the overlying connection electrode 730. In the overlapping area, the connection electrode 730 may be electrically connected to the sixth data pattern / component 660 through a contact hole CNT14 that passes through the first via layer VIA1 and exposes the sixth data pattern / component 660.

[0195] Therefore, the sixth data pattern / component 660 can electrically connect the third horizontal portion 150 of the underlying first semiconductor layer 100 to the overlying connection electrode 730.

[0196] The fourth conductive layer 600 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 600 may be a single layer or may include multiple layers. For example, the fourth conductive layer 600 may be a stacked structure including Ti-Al-Ti, Mo-Al-Mo, Mo-AlGe-Mo, and / or Ti-Cu.

[0197] A first via layer VIA1 is disposed on the fourth conductive layer 600. The first via layer VIA1 may comprise an inorganic insulating material, or may comprise an organic insulating material, such as acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene resin (polyphenylene ether resin), polyphenylene sulfide resin, or benzocyclobutene (BCB). When the first via layer VIA1 comprises an organic insulating material, the upper surface of the first via layer VIA1 may be substantially flat despite the presence of the underlying step.

[0198] A fifth conductive layer 700 is disposed on the first via layer VIA1. The fifth conductive layer 700 may include components for supplying a first power supply voltage ELVDD (in...). Figure 3The first power supply voltage line 710 (in the middle) is used to transmit the data signal DATA. Figure 3 The data line 720 (in the middle) and the connection electrode 730 for providing an electrical connection between the anode ANO of the organic light-emitting diode OLED and the sixth data pattern / component 660.

[0199] The first power supply voltage line 710 and the data line 720 may extend in the second direction DR2. The first power supply voltage line 710 and the data line 720 may extend across the boundary of a pixel to an adjacent pixel. For a pixel column extending in the second direction DR2, the first power supply voltage line 710 and the data line 720 are arranged substantially adjacent to the left side of the pixel column, and the first power supply voltage line 710 may be arranged to the right of the data line 720. A connection electrode 730 may be provided for each pixel, and the connection electrode 730 may be arranged in the plan view closer to the curved region BA than at least one of the first scan line 210 and the first light emission control line 220.

[0200] The electrical connection relationship between the first power supply voltage line 710, the data line 720, and the connecting electrode 730 has been described above.

[0201] The second via layer VIA2 is disposed on the fifth conductive layer 700. The second via layer VIA2 may comprise substantially the same material as the first via layer VIA1. When the second via layer VIA2 comprises an organic insulating material, the upper surface of the second via layer VIA2 may be substantially flat despite the presence of the underlying step.

[0202] The anode (ANO) is disposed on the second via layer (VIA2). A separate anode (ANO) can be provided for each pixel. The anode (ANO) can be electrically connected to the connection electrode 730 through a contact hole that passes through the second via layer (VIA2) and exposes a portion of the connection electrode 730.

[0203] The anode ANO can have a multilayer structure comprising a high work function material layer containing indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In₂O₃) and a reflective material layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or combinations thereof. The high work function material layer can be arranged above the reflective material layer to be closer to the light-emitting layer (EL). The anode ANO can have a multilayer structure of ITO-Mg, ITO-MgF, ITO-Ag, or ITO-Ag-ITO.

[0204] A pixel defining layer (PDL) may be disposed on the anode (ANO). The pixel defining layer (PDL) may include openings that partially expose the anode (ANO). The pixel defining layer (PDL) may include organic insulating materials and / or inorganic insulating materials. For example, the pixel defining layer (PDL) may include at least one of polyimide resin, acrylic resin, silicone compound, and polyacrylic resin.

[0205] The light-emitting layer (EL) may be disposed on a portion of the anode (ANO) exposed by the pixel-defined layer (PDL). The EL may include an organic material layer. The organic material layer of the EL may include an organic light-emitting layer and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0206] The cathode (CAT) can be placed on the light-emitting layer (EL). The cathode (CAT) can be a common electrode shared by multiple pixels.

[0207] The cathode CAT may include a low work function material layer comprising Li, Ca, LiF-Ca, LiF-Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or combinations thereof (e.g., a combination of Ag and Mg). The cathode CAT may also include a transparent metal oxide layer disposed on the low work function material layer.

[0208] The corresponding portions of the anode (ANO), the light-emitting layer (EL), and the cathode (CAT) can constitute an organic light-emitting diode (OLED).

[0209] A thin-film encapsulation layer comprising at least one inorganic film and at least one organic film may be disposed on the cathode CAT. The thin-film encapsulation layer encapsulates each component of the pixel and prevents the penetration of external air or moisture.

[0210] Figure 12 This is a cross-sectional view of the display panel of the display device according to the embodiment. Figure 12 A cross-section of the fourth transistor T4 and the leakage prevention diode LD_1 is shown.

[0211] Reference Figure 12 The first electrode 310_1 of the leakage prevention diode LD_1 of the display panel 10_1 is... Figure 7 The difference in the first electrode 310 shown is that the first electrode 310_1 is a part of the first conductive layer 200.

[0212] The first electrode 310_1 of the leakage prevention diode LD_1 may be disposed on one surface (or face) of the first gate insulating layer GI1 and may be covered by the second gate insulating layer GI2. The first electrode 310_1 of the leakage prevention diode LD_1 may be located between the first gate insulating layer GI1 and the second gate insulating layer GI2. In the leakage prevention diode LD_1, the second gate insulating layer GI2 and the first interlayer insulating layer ILD1 may be located between the first electrode 310_1 and the second electrode 411. The insulator of the leakage prevention diode LD_1 may include the second gate insulating layer GI2 and the first interlayer insulating layer ILD1.

[0213] Even if the active layer ACT3 of the third transistor T3 is part of the first semiconductor layer 100 (refer to...) Figure 6 Furthermore, a leakage prevention diode LD_1 can be provided, making it easier to minimize or prevent current leakage. Moreover, since the insulator of the leakage prevention diode LD_1 comprises a second gate insulating layer GI2 and a first interlayer insulating layer ILD1, the thickness of the insulator of the leakage prevention diode LD_1 can be easily adjusted while maintaining the characteristics of each of the second gate insulating layer GI2 and the first interlayer insulating layer ILD1. Therefore, the characteristics of the leakage prevention diode LD_1 can be optimized while maintaining the insulation characteristics of each of the second gate insulating layer GI2 and the first interlayer insulating layer ILD1.

[0214] Figure 13 This is a cross-sectional view of the display panel of the display device according to the embodiment. Figure 13 A cross-section of the fourth transistor T4 and the leakage prevention diode LD is shown.

[0215] Reference Figure 13 Display panel 10_2 and Figure 7 The difference in the implementation of the display panel is that a lower light-blocking pattern BML_2 is also provided below the fourth transistor T4 of each pixel of the display panel 10_2.

[0216] The first conductive layer 200 of the display panel 10_2 may further include a lower light-blocking pattern BML_2. The lower light-blocking pattern BML_2 may be arranged below the active layer ACT4 of the fourth transistor T4.

[0217] The lower light-blocking pattern BML_2 prevents light incident from the lower part of the display panel 10_2 from entering the active layer ACT4 of the fourth transistor T4. The lower light-blocking pattern BML_2 may overlap at least with the channel region of the active layer ACT4 of the fourth transistor T4.

[0218] In some embodiments, the lower light-blocking pattern BML_2 can be used as another gate electrode of the fourth transistor T4. The lower light-blocking pattern BML_2 can be electrically connected to the gate electrode GAT4 of the fourth transistor T4. The lower light-blocking pattern BML_2 can be electrically connected to one of the first electrode SD41 and the second electrode SD42 of the fourth transistor T4.

[0219] Even if the active layer ACT3 of the third transistor T3 is part of the first semiconductor layer 100 (refer to...) Figure 6 Furthermore, a leakage prevention diode LD can be provided, making it easier to minimize or prevent current leakage. Considering the lower light-blocking pattern BML_2 provided below the active layer ACT4, the reliability of the fourth transistor T4 can be improved, thereby improving the reliability of the display panel 10_2.

[0220] Figure 14 This is a layout diagram of a pixel of a display device according to an embodiment. Figure 15 This is a cross-sectional view of the display panel according to the embodiment. Figure 15 The cross-sections of the first transistor T1 and the third transistor T3 are shown.

[0221] Reference Figure 14 and Figure 15 Display panel 10_3 and Figure 4 The difference in the display panel shown is that the display panel 10_3 does not include the fifth conductive layer 700. Figure 4 (as shown in the image).

[0222] In one pixel of the display panel 10_3, the fourth conductive layer 600 may include a first power supply voltage line 710_3 and a data line 720_3, as well as a first data pattern / component 610, a second data pattern / component 620, a fifth data pattern / component 650, and a sixth data pattern / component 660. The first power supply voltage line 710_3 and the data line 720_3 may be arranged on the same layer as each of the first data pattern / component 610, the second data pattern / component 620, the fifth data pattern / component 650, and the sixth data pattern / component 660. The first power supply voltage line 710_3 and the data line 720_3 may be separated and may be spaced apart from each of the first data pattern / component 610, the second data pattern / component 620, the fifth data pattern / component 650, and the sixth data pattern / component 660.

[0223] Third data pattern / component 630 (reference) Figure 4 ) and fourth data pattern / component 640 (refer to) Figure 4(This can be optional.) The first power supply voltage line 710_3 can directly contact the second electrode 320 of the storage capacitor Cst and the second horizontal portion 140 of the first semiconductor layer 100 through contact holes CNT7_3 and CNT8_3, respectively. The data line 720_3 can directly contact the upper portion 111 of the first vertical portion 110 of the first semiconductor layer 100 through contact hole CNT5_3.

[0224] Connecting electrode 730 (reference) Figure 4 The anode (ANO) of an organic light-emitting diode (OLED) can be selected without the need for connecting electrodes 730 (see reference). Figure 4 In the case of the first transistor T1, it is in direct contact with the second electrode SD12.

[0225] Even if the active layer ACT3 of the third transistor T3 is part of the first semiconductor layer 100 (refer to...) Figure 15 Furthermore, it can provide a leakage prevention diode LD, making it easier to minimize or prevent current leakage.

[0226] Many changes and modifications can be made to the described exemplary embodiments without substantially departing from the scope defined by the claims.

Claims

1. A display device, comprising: Light-emitting elements; A first transistor controls the driving current flowing to the light-emitting element based on the voltage applied to the gate electrode of the first transistor; The second transistor is electrically connected between the gate electrode of the first transistor and the first electrode of the first transistor; as well as A diode, wherein a first electrode of the diode is electrically connected to a first electrode of a second transistor, and wherein a second electrode of the diode is connected to the gate electrode of the first transistor. The first electrode of the diode is electrically connected to the anode of the light-emitting element through the second transistor and the fifth transistor.

2. The display device according to claim 1, in, The first electrode of the diode comprises a metal, and the second electrode of the diode comprises an oxide semiconductor.

3. The display device according to claim 2, in, In the diode, current flows from the first electrode to the second electrode.

4. The display device according to claim 1, in, Each of the active layers of the first transistor and the second transistor comprises polysilicon.

5. The display device according to claim 4, further comprising: A third transistor, electrically connected to the gate electrode of the first transistor and receiving an initialization voltage, The active layer of the third transistor includes an oxide semiconductor.

6. The display device according to claim 5, in, The first transistor and the second transistor are PMOS transistors, and the third transistor is an NMOS transistor.

7. The display device according to claim 5, in, The material of the second electrode of the diode is the same as the material of the active layer of the third transistor.

8. The display device according to claim 7, further comprising: Insulator; as well as A capacitor, wherein a first electrode of the capacitor is electrically connected to the gate electrode of the first transistor, wherein a second electrode of the capacitor overlaps with the first electrode of the capacitor, and wherein the first electrode of the diode and the second electrode of the capacitor are directly disposed on the same surface of the insulator.

9. The display device according to claim 1, further comprising: A fourth transistor, which is electrically connected to the second electrode of the first transistor and receives the data voltage; as well as The scan line is electrically connected to both the gate electrode of the second transistor and the gate electrode of the fourth transistor without passing through an intermediary transistor.

10. A display device, comprising: Light-emitting elements; A first transistor controls the driving current flowing to the light-emitting element based on the voltage applied to the gate electrode of the first transistor; The second transistor is electrically connected between the gate electrode of the first transistor and the first electrode of the first transistor; A third transistor is electrically connected to the gate electrode of the first transistor without passing through an intermediary transistor and receives an initialization voltage; as well as A diode, wherein the diode is electrically connected between the first electrode of the second transistor and the gate electrode of the first transistor. The first electrode of the diode is electrically connected to the anode of the light-emitting element through the second transistor and the fifth transistor. Each of the active layers of the first transistor and the second transistor comprises polysilicon, and the active layer of the third transistor comprises an oxide semiconductor.

11. The display device according to claim 10, in, The first electrode of the diode comprises a metal, and the second electrode of the diode comprises an oxide semiconductor.

12. The display device according to claim 11, in, The material of the second electrode of the diode is the same as the material of the active layer of the third transistor.

13. The display device according to claim 12, further comprising: Insulator; as well as A capacitor, wherein a first electrode of the capacitor is electrically connected to the gate electrode of the first transistor, wherein a second electrode of the capacitor overlaps with the first electrode of the capacitor, and wherein the first electrode of the diode and the second electrode of the capacitor are directly disposed on the same surface of the insulator.

14. The display device according to claim 10, further comprising: A fourth transistor, which is electrically connected to the second electrode of the first transistor and receives the data voltage; as well as The scan line is electrically connected to both the gate electrode of the second transistor and the gate electrode of the fourth transistor without passing through an intermediary transistor.

15. A display device, comprising: Substrate; First transistor; A first gate insulating layer is disposed between the gate electrode of the first transistor and the active layer of the first transistor, wherein the active layer of the first transistor is disposed between the gate electrode of the first transistor and the substrate. diode; A second gate insulating layer is disposed between the first electrode of the diode and the substrate, wherein the gate electrode of the first transistor is disposed between the second gate insulating layer and the substrate; A first interlayer insulating layer is disposed between the second electrode of the diode and the substrate, wherein the first electrode of the diode is disposed between the first interlayer insulating layer and the substrate; The second transistor, wherein the first interlayer insulating layer is disposed between the active layer of the second transistor and the substrate; A second interlayer insulating layer is disposed between the first electrode of the first transistor and the substrate, and between the second electrode of the first transistor and the substrate, wherein each of the second electrode of the diode and the active layer of the second transistor is disposed between the second interlayer insulating layer and the substrate. The active layer of the first transistor comprises polysilicon, and each of the active layer of the second transistor and the second electrode of the diode comprises an oxide semiconductor.

16. The display device according to claim 15, further comprising: A connecting member electrically connecting the first electrode of the first transistor and the first electrode of the diode.

17. The display device according to claim 16, in, The connecting member is connected to the first electrode of the first transistor through a first contact hole passing through the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

18. The display device according to claim 16, in, The connecting member is connected to the first electrode of the diode through a second contact hole passing through the second interlayer insulation layer and the first interlayer insulation layer.

19. The display device according to claim 15, further comprising: capacitor, The first electrode of the capacitor is electrically connected to the gate electrode of the first transistor. Wherein, the second electrode of the capacitor overlaps with the first electrode of the capacitor, and The second gate insulating layer is disposed between the second electrode of the capacitor and the substrate.

20. The display device according to claim 19, in, The material of the first electrode of the diode is the same as the material of the second electrode of the capacitor.

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