Semiconductor package structure and method of forming the same

Abstract

The application relates to a semiconductor packaging structure and a forming method thereof. The semiconductor packaging structure comprises a carrier plate, an optical integrated circuit and an optical element, the optical integrated circuit and the optical element are located above the carrier plate, the optical integrated circuit and the optical element have an optical path from the optical element to a light receiving surface of the optical integrated circuit, and an adjusting device is located below the optical integrated circuit, the adjusting device is configured to adjust an angle between the optical path and the light receiving surface to correctly guide the optical path to the light receiving surface. The above technical scheme of the application can at least correct the optical path, so that the light is transmitted along a correct path.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] In conventional packaging structures, optical components such as fiber optic arrays (FAUs) and optical integrated circuits (PICs) use light to transmit and communicate data. However, the optical transmission path is fixed, and if the FAU shifts after the packaging structure is formed, the optical path is difficult to adjust.

[0003] Additionally, in some packaging structures, a reflective element is placed in the optical path between the FAU and the PIC to guide the light correctly to the PIC. However, the angle of the reflective element needs to be set with high precision; otherwise, the deflection of the fiber array will cause the light to travel along the wrong optical path, preventing the light from being correctly guided to the FAU. If the angle of the reflective element can be finely adjusted, it will help to correct and adjust the optical path when it is deflected. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure and its formation method, which can correct the optical path so that light can be transmitted along the correct path.

[0005] Includes: a carrier plate; an optical integrated circuit and an optical element, the optical integrated circuit and the optical element being located above the carrier plate, with an optical path between the optical integrated circuit and the optical element, from the optical element to the light-receiving surface of the optical integrated circuit; and an adjustment device disposed adjacent to the optical integrated circuit, the adjustment device being configured to adjust the optical path entering the light-receiving surface to correctly guide the optical path to the light-receiving surface.

[0006] In some embodiments, the adjustment device is configured to adjust the angle of the light path entering the light-receiving surface.

[0007] In some embodiments, the semiconductor package structure further includes: a reflective element located on a carrier plate and disposed opposite to the optical element, the light-receiving surface of the optical integrated circuit being located above the reflective element, and the light path entering the light-receiving surface after being reflected by the reflective element; wherein, the adjustment device is connected to the reflective element and is configured to change the angle of the reflective element to change the angle of the light path entering the light-receiving surface.

[0008] In some embodiments, the adjustment device includes: a first thermal expansion member located between the carrier plate and the reflective element, disposed adjacent to one end of the reflective element in the direction toward the optical element, wherein the first thermal expansion member is highly adjustable according to temperature to adjust the angle of the reflective element.

[0009] In some embodiments, the adjustment device further includes a second thermal expansion member located between the carrier plate and the reflective element, and disposed adjacent to the other end of the reflective element in the direction toward the optical element, wherein the first thermal expansion member and the second thermal expansion member comprise different thermal expansion materials.

[0010] In some embodiments, the semiconductor package structure further includes a redistribution layer located on the side of the reflective element opposite to the optical element, wherein the optical integrated circuit is located on the redistribution layer and the light-receiving surface of the optical integrated circuit is exposed by the redistribution layer.

[0011] In some embodiments, the redistribution layer includes: a first redistribution layer located on the side of the reflective element opposite to the optical element; and a second redistribution layer bonded to the first redistribution layer and extending above the reflective element, wherein the second redistribution layer has an opening that exposes the light-receiving surface.

[0012] In some embodiments, the semiconductor package structure further includes an electrical integrated circuit located above the redistribution layer.

[0013] In some embodiments, the adjustment device is configured to adjust the tilt angle of the light-receiving surface.

[0014] In some embodiments, the optical element is located above the optical integrated circuit, and the optical integrated circuit has a body and a cantilever connected to the body, the cantilever extending laterally on a carrier plate and spaced apart from the carrier plate, and a light-receiving surface located on the cantilever, wherein the adjustment device is configured to adjust the distance between the end of the cantilever away from the body and the carrier plate to adjust the tilt angle of the light-receiving surface.

[0015] In some embodiments, the adjustment device includes a magnet and a coil located within a gap between the cantilever and the carrier plate, one of the magnet and the coil being located on the carrier plate, and the other of the magnet and the coil being connected below the cantilever, wherein the magnet and the coil are configured to generate magnetic force to adjust the distance between the end of the cantilever away from the body and the carrier plate.

[0016] In some embodiments, the thickness of the cantilever of the optical integrated circuit is less than the thickness of the body.

[0017] In some embodiments, the semiconductor package structure further includes: a molding compound located on a carrier and encapsulating the body of the optical integrated circuit, wherein the molding compound has a cavity, a cantilever and an adjustment device are located in the cavity, and an optical element is located on the molding compound and spans the cavity.

[0018] In some embodiments, the semiconductor package structure further includes an integrated circuit located on a carrier and encapsulated by molding compound.

[0019] In some embodiments, the optical element has a tilt angle.

[0020] According to an embodiment of the present invention, a method for forming a semiconductor package structure is also provided, comprising: providing a carrier plate; forming an adjustment device and an optical integrated circuit above the carrier plate, wherein the light-receiving surface of the optical integrated circuit is formed above the adjustment device; placing an optical element above the carrier plate, wherein an optical path from the optical element to the light-receiving surface of the optical integrated circuit is formed between the optical integrated circuit and the optical element; and adjusting the angle between the light path entering the light-receiving surface and the light-receiving surface by the adjustment device to correctly guide the light path to the light-receiving surface.

[0021] In some embodiments, the method further includes: forming a reflective element disposed opposite to an optical element on an adjustment device, wherein the light path enters a light-receiving surface after being reflected by the reflective element; wherein the adjustment device is configured to change the angle of the reflective element to change the angle of the light path entering the light-receiving surface.

[0022] In some embodiments, forming an adjustment device includes: forming a first thermal expansion member and a second thermal expansion member disposed opposite to each other using different thermal expansion materials between a carrier plate and a reflective element, wherein the height of the first thermal expansion member and the second thermal expansion member is changed by temperature to adjust the angle of the reflective element.

[0023] In some embodiments, the method further includes: forming a first redistribution layer on a carrier substrate, wherein a reflective element is disposed adjacent to the first redistribution layer; bonding a second redistribution layer having an opening onto the first redistribution layer such that the opening is located above the reflective element; and placing an optical integrated circuit on the second redistribution layer, wherein the light-receiving surface of the optical integrated circuit is placed in the opening.

[0024] In some embodiments, forming the adjustment device includes: removing a portion of the optical integrated circuit opposite to the light-receiving surface to form a recess; forming a magnet in the recess; performing a cut along the bottom surface of the recess to form a body of the optical integrated circuit and a cantilever connected to the body and having a magnet and a light-receiving surface; and placing the optical integrated circuit on a carrier plate such that the magnet is opposite to a coil on the carrier plate.

[0025] In some embodiments, after placing the optical integrated circuit, the method further includes: a molding compound forming the body of the encapsulated optical integrated circuit, wherein the molding compound has a cavity for accommodating a cantilever, and the optical element is placed on the molding compound and spans the cavity.

[0026] The above-described technical solution of the present invention, by setting an adjustment device, adjusts the angle between the light path entering the light-receiving surface and the light-receiving surface, so as to correctly guide the light path to the light-receiving surface. Thus, the adjustment device can be used to correct the light path, enabling light to be transmitted along the correct path between optical elements (such as FAU) and optical integrated circuits. Attached Figure Description

[0027] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0028] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0029] Figure 2a yes Figure 1 A magnified view of a portion of area A1.

[0030] Figures 2b-2c This is a schematic diagram of the operation of the adjustment device in the semiconductor packaging structure according to an embodiment of the present invention.

[0031] Figures 3a-3b This is a schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention.

[0032] Figures 4a-4b This is a schematic diagram of the structure of a semiconductor device according to another embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to another embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to another embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to another embodiment of the present invention.

[0036] Figures 8a to 8j This is a schematic diagram of various stages of a method for forming a reflective element in a semiconductor package structure according to an embodiment of the present invention.

[0037] Figures 9a to 9i This is a schematic diagram of the various stages of a method for forming a redistribution layer in a semiconductor package structure according to an embodiment of the present invention.

[0038] Figures 10a to 10l This is a schematic diagram of each stage of the method for forming the semiconductor package structure of the present invention using prefabricated reflective elements and redistribution layers.

[0039] Figure 11 This is a schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention.

[0040] Figures 12a to 12h This is a schematic diagram of the various stages in a method for forming a semiconductor package structure (PIC) according to another embodiment of the present invention.

[0041] Figures 13a to 13m This is a schematic diagram of each stage in a method for forming a semiconductor package structure according to another embodiment of the present invention using a PIC. Specific Implementation

[0042] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0043] This invention provides a semiconductor packaging structure. Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 1000 includes a substrate 210 (carrier). In some embodiments, the thickness of the substrate 210 is in the range of 20 μm to 200 μm. Optical components such as an optical integrated circuit (PIC) 220 and a fiber optic array (FAU) 230 are disposed above the substrate 210. In the illustrated embodiment, the optical component is an FAU 230, but other types of optical components may also be used, and the present invention does not limit this.

[0044] In the illustrated embodiment, a light guide component 223, such as a raster, is disposed on the lower surface of the PIC 220. The light-receiving surface 222 of the PIC 220 is the surface of the light guide component 223. In other embodiments, the light-receiving surface 222 may also be other components or surfaces of the PIC 220 used to receive light from the FAU. The light-receiving surfaces 222 of the PIC 220 have spacing such as... Figure 1 The dashed line in the diagram shows the optical path PG. Light from FAU 230 is transmitted to the light-receiving surface 222 of PIC 220 via the optical path PG.

[0045] In this embodiment, the light path is reflected by the reflective element 250 on the substrate 210 onto the light-receiving surface 222 of the PIC 220. The reflective element 250 is disposed opposite to the FAU 230, and the light-receiving surface 222 of the PIC 220 is located above the reflective element 250.

[0046] Figure 2a yes Figure 1 A magnified view of area A1. (Reference) Figure 2aAs shown, in some embodiments, the reflective element 250 may include a substrate 251 and a reflective layer 253. The reflective layer 253 covers the substrate 251. In some embodiments, the thickness of the reflective layer 253 may be in the range of 3 μm to 30 μm. The reflective layer 253 has an inclined surface opposite to the FAU 230, such that light from the FAU 230 can be reflected by the inclined surface of the reflective layer 253 to the light-receiving surface 222. The inclination angle of the inclined surface of the reflective layer 253 may be in the range of 10° to 80°. In some embodiments, the overall height MH of the reflective element 250 may be in the range of 10 μm to 10 mm. In other embodiments, reflective elements with other structures may also be used.

[0047] An adjustment device 240 is provided below the reflective element 250. The adjustment device 240 is configured to adjust the angle between the light path PG entering the light-receiving surface 222 and the light-receiving surface 222. In this embodiment, the adjustment device 240 adjusts the angle of the light path PG entering the light-receiving surface to correctly guide the light path PG to the light-receiving surface 222. In cases where the light path PG is incorrect, for example, due to the tilt of the FAU, the adjustment device 240 can be used to change the tilt angle of the reflective element 250 to adjust the angle of the light path PG entering the light-receiving surface 222, thereby correctly guiding the light path PG to the light-receiving surface 222. Thus, the adjustment device 240 can be used to correct the light path PG, enabling light to be transmitted along the correct path between the FAU 230 and the PIC 220.

[0048] Specifically, the adjusting device 240 includes a first thermal expansion member 241 and a second thermal expansion member 243. The first thermal expansion member 241 and the second thermal expansion member 243 are arranged opposite to each other in the direction toward the FAU 230, that is, the first thermal expansion member 241 is disposed near one end of the reflective element 250, and the second thermal expansion member 243 is disposed near the other end of the reflective element 250. The first thermal expansion member 241 and the second thermal expansion member 243 are formed of different thermal expansion materials with different coefficients of thermal expansion (CTE).

[0049] Because the first thermal expansion component 241 and the second thermal expansion component 243 have different coefficients of thermal expansion, they can have different height variations at the same temperature. For example, as Figure 2b As shown, when the thermal expansion of the first thermal expansion component 241 is less than that of the second thermal expansion component 243, the height of the first thermal expansion component 241 is less than the height of the second thermal expansion component 243, causing the reflective element 250 to tilt counterclockwise toward the first thermal expansion component 241. Conversely, as... Figure 2cAs shown, when the thermal expansion of the first thermal expansion member 241 is greater than that of the second thermal expansion member 243, the height of the first thermal expansion member 241 is greater than the height of the second thermal expansion member 243, causing the reflective element 250 to tilt clockwise toward the second thermal expansion member 243. Therefore, the height variation of the first and second thermal expansion members 241 and 243 can be controlled by temperature to change the tilt angle of the reflective element 250, thereby adjusting the angle of the light path PG entering the light-receiving surface 222 to correctly guide the light path PG to the light-receiving surface 222. In some embodiments, after determining the appropriate tilt angle of the reflective element 250 through testing, an adhesive material for fixing the reflective element 250 can be provided to maintain the tilt angle of the reflective element 250.

[0050] refer to Figure 2a and combined Figure 2b and Figure 2c As shown, solder 287, a metal layer 288 on the solder 287, and a seed layer 289 on the metal layer 288 may be respectively disposed above the first thermal expansion member 241 and the second thermal expansion member 243 to connect to the reflective element 250. Furthermore, the adjustment device 24 may also include a heating layer 245 and a heating layer 247. The heating layer 245 and the heating layer 247 may be connected to the lower surface of the reflective element 250 and used for applying temperature control.

[0051] Return to reference Figure 1 As shown, a redistribution layer (RDL) 260 is disposed on the substrate 210 and located on the side of the reflective element 250 opposite to the FAU 230. The redistribution layer 260 includes a first redistribution layer 261 and a second redistribution layer 269. The first redistribution layer 261 includes a first dielectric layer 263, a second dielectric layer 265 stacked together, and redistribution lines 262 formed in the first and second dielectric layers 263 and 265. The second redistribution layer 269 includes a third dielectric layer 267 and redistribution lines 266 formed in the third dielectric layer 267. The first redistribution layer 261 and the second redistribution layer 269 are bonded to each other by a bonding solder 285. A protective layer 280 is disposed between the first redistribution layer 261 and the second redistribution layer 269. The second redistribution layer 269 is bonded to the first redistribution layer 261 and extends above the reflective element 250, with the light-receiving surface 222 of the PIC 220 exposed by an opening 268 in the second redistribution layer 269. The PIC 220 is located on the second redistribution layer 269. The light-receiving surface 222 of the PIC 220 is exposed by the redistribution layer 260 and receives light reflected by the reflective element 250 below.

[0052] In the illustrated embodiment, the lowermost first dielectric layer 263 of the first redistribution 261 covers the upper surface of the substrate 210 and extends to the edge of the substrate 210. The second dielectric layer 265 is smaller than the first dielectric layer 263, such that the FAU, reflective element 250, and adjustment device 240 are located on the first dielectric layer 263. The FAU 230 may be disposed adjacent to the edge of the first dielectric layer 263. In some embodiments, the FAU 230 is attached to the first dielectric layer 263 by an adhesive layer 232. In some embodiments, the thickness of the adhesive layer 232 is in the range of 10 μm to 50 μm. Since the adjustment device 240 has the function of adjusting the guiding optical path PG, the placement of the FAU 230 can allow for tilt accuracy.

[0053] An electrical integrated circuit (EIC) 290 is also disposed above the redistribution layer 260. In some embodiments, the size (width) of the EIC 290 can be in the range of 10 μm to 1000 mm. The thickness of the EIC 290 is in the range of 20 μm to 100 μm. In some embodiments, the width of the PIC 220 is in the range of 10 μm to 1000 mm. The thickness of the PIC 220 is in the range of 20 μm to 100 μm. The EIC 290 and PIC 220 can be connected to the second redistribution layer 269 via bump connectors 249, respectively. In some embodiments, the diameter of the bump connectors 249 is in the range of 10 μm to 30 μm, and the pitch between two adjacent bump connectors 249 is in the range of 15 μm to 60 μm.

[0054] An underfill 270 is provided between the EIC 290 and the redistribution layer 260, and between the PIC 220 and the redistribution layer 260. The underfill 270 surrounds the bump connector 249. Solder balls 295 are provided on the lower surface of the substrate 210. In some embodiments, the diameter of the solder balls 295 is in the range of 30 μm to 200 μm, and the pitch between two adjacent solder balls 295 is in the range of 50 μm to 400 μm.

[0055] Figure 3a and Figure 3b This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. For example... Figure 3a and Figure 3b As shown, a molding compound 275 encapsulating the PIC 220, EIC 290, and underfill 270 can be formed on the redistribution layer 260. Figure 3a In the illustrated embodiment, molding compound 275 may have vertical sidewalls and a flat upper surface connected between the vertical sidewalls. Molding compound 275 covers the upper surfaces of EIC 290 and PIC 220. Figure 3bIn the illustrated embodiment, the molding compound 275 may be formed, for example, by a dispensing process, and has an upwardly convex curved surface profile. In such an embodiment, the molding compound 275 may expose a portion of the surface and / or sidewalls of the PIC 220.

[0056] Figure 4a and Figure 4b This is a schematic diagram of a semiconductor package structure according to other embodiments of the present invention. The reflective element 250 can have different shapes. For example... Figure 4a As shown, the upward protrusion of the reflective element 250 may have a sharp angle, so that the surface of the reflective element 250 facing the FAU 230 is inclined. Figure 4b In the illustrated embodiment, the upwardly protruding portion of the reflective element 250 has a curved shape. In other embodiments, the reflective element 250 may have other suitable shapes.

[0057] Figure 5 This is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. In this embodiment, the FAU 230 can contact the dielectric layer 267 of the second redistribution layer 269. The distance between the FAU 230 and the reflective element 250 is reduced, shortening the optical path PG from the FAU 230 to the reflective element 250, and correspondingly reducing the deflection amplitude of the optical path PG.

[0058] Figure 6 This is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. In this embodiment, the first redistribution layer 261 has a surface exposed by the second redistribution layer 269. Furthermore, the EIC 290 is directly physically and electrically connected to the first redistribution layer 261. Additionally, an underfill 270 is formed between the PIC 220 and the second redistribution layer 269, and between the EIC 290 and the first redistribution layer 261.

[0059] Figure 7 This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. For example... Figure 7 As shown, two FAU230s are disposed on opposite sides of the substrate 210, and two adjustment devices 240, two reflective elements 250 and two PICs 220 are respectively disposed on them.

[0060] The present invention also provides a method for forming a semiconductor package structure according to one embodiment. Figures 8a to 8j This is a schematic diagram of various stages of a method for forming a reflective element in a semiconductor package structure according to an embodiment of the present invention.

[0061] like Figure 8aAs shown, a mold 820 with a flat, serrated edge 822 is provided, and a mold 810 is shaped using, for example, a pressing process, such that the surface of the mold 810 forms a serrated surface 812. In some embodiments, the material of the mold 810 can be any suitable material with ductility.

[0062] like Figure 8b As shown, after the molded part 810 has been shaped, a reflective layer 830 is applied along the surface of the molded part 810 using, for example, a coating process. In some embodiments, the material of the reflective layer 830 can be any suitable material with light reflectivity. In some embodiments, the thickness of the reflective layer 830 is in the range of 3 μm to 30 μm.

[0063] like Figure 8c As shown, a heating layer 840 is formed on the back side of the flip-over mold 810 using, for example, a coating process. Figure 8d As shown, a seed layer 289 is formed on the heating layer 840. In some embodiments, the seed layer 289 may be deposited using a process such as physical vapor deposition (PVD).

[0064] like Figure 8e As shown, for example, a mask layer 860 is formed on the seed layer 289 using a layering process. The mask layer 860 is then patterned. In some embodiments, the mask layer 860 may be a photomask and patterned using a photolithography process.

[0065] like Figure 8f As shown, multiple openings 862 are formed in the patterned mask layer 860 to expose the seed layer 289. A metal layer 288 is formed on the seed layer 289 within the openings 862. The metal layer 288 can be formed by processes such as electroplating or electroless plating. Solder 287 is then formed on the metal layer 288 within the openings 862.

[0066] like Figure 8g As shown, the patterned mask layer 860 can be removed using, for example, an etching process. Figure 8h As shown, the seed layer 289, which is masked by the patterned mask layer 860, continues to be removed. Figure 8i As shown, an etching process is then performed to remove the heating layer 840 exposed by the stacked seed layer 289, metal layer 288, and solder 287. Afterwards, the solder 287 is heated and reflowed.

[0067] like Figure 8j As shown, the obtained structure is cut to generate multiple individual reflective elements 250, and individual reflective elements 250 are picked up for use in subsequent processes.

[0068] Figures 9a to 9iThis is a schematic diagram of the various stages of a redistribution layer method in a semiconductor package structure according to an embodiment of the present invention. Figure 9a As shown, a metal layer 912 is formed on the carrier 902. Figure 9b As shown, a mask layer 922 is formed on the metal layer 912. The mask layer 922 is then patterned. In some embodiments, the mask layer 922 may be a photomask and patterned using a photolithography process. Figure 9c As shown, the metal layer 912 exposed to the patterned mask layer 922 is removed using the patterned mask layer 922. Figure 9d As shown, the patterned mask layer 922 is removed, exposing the metal layer 912 covered by the patterned mask layer 922. The remaining metal layer 912 forms pads 914.

[0069] like Figure 9e As shown, a dielectric layer 932 covering the pads 914 is formed on the carrier 902, and the dielectric layer 932 is patterned. In some embodiments, the thickness of the dielectric layer 932 is in the range of 5 μm to 20 μm.

[0070] like Figure 9f As shown, a large square opening 936 and multiple smaller openings 934 are formed in the patterned dielectric layer 932, and the dielectric layer 932 on the side edge of the carrier 902 away from the opening 934 is completely removed to expose the surface of the carrier 902. Opening 936 exposes the surface of the carrier 902, and opening 934 exposes the pads 914 on the carrier 902. A metal layer 942 is then formed on the surface of the carrier 902, the surface of the patterned dielectric layer 932, and in the openings 934 and 936. In some embodiments, a plating process may be used to form the metal layer 942.

[0071] like Figure 9g As shown, a mask layer 952 is formed on the surface of the metal layer 942 and on the sidewalls of the dielectric layer 932, and the mask layer 952 is patterned. Figure 9h As shown, an opening 954 is formed in the patterned mask layer 952 to expose the pad metal layer 942, wherein the opening 954 corresponds to the position of the opening 934 mentioned above. A conductive material 962 is then formed in the opening 954. In some embodiments, the conductive material 962 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Pd, Pt, etc.).

[0072] like Figure 9i As shown, the patterned mask layer 952 and the metal layer 942 hidden by the patterned mask layer 952 are removed, and the remaining metal layer 942 and conductive material 962 together form redistribution lines 966. Thus, redistribution layer 269 is formed.

[0073] Figures 10a to 10lThis is a schematic diagram of each stage of the method for forming a semiconductor package structure according to an embodiment of the present invention using a pre-fabricated reflective element 250 and a redistribution layer 269.

[0074] like Figure 10a As shown, a substrate 210 with a first redistribution layer 261 is provided. Seed layers 1002 and 1004 are provided on the surface of the first dielectric layer 263 of the first redistribution layer 261 exposed by the second dielectric layer 265. A first thermal expansion member 241 and a second thermal expansion member 243 are respectively provided on the seed layers 1002 and 1004.

[0075] like Figure 10b As shown, the reflective element 250 is connected to the first thermal expansion component 241 and the second thermal expansion component 243 via solder 287. Figure 10c As shown, a protective layer 280 is formed on the first redistribution layer 261.

[0076] like Figure 10d As shown, redistribution layer 269 (second redistribution layer) is attached to first redistribution layer 261. Figure 10e As shown, the carrier 902 of the redistribution layer 269 is removed. Figure 10f As shown, EIC 290 is connected to the side of the second redistribution layer 269 near the edge of the substrate 210, and EIC 290 is electrically connected to the second redistribution layer 269.

[0077] like Figure 10g As shown, next to EIC 290, PIC 220 is connected to the second rewiring layer 269. The light-receiving surface 222 of PIC 220 is exposed by the second rewiring layer 269. PIC 220 is connected to the second rewiring layer 269 via bump connector 249. The light-receiving surface 222 of PIC 220 is vertically opposite to the reflective element 250 to receive light reflected by the reflective element 250.

[0078] like Figure 10h As shown, a bottom filler 270 is formed. The bottom filler 270 is formed between the EIC 290, PIC 220, and the second rewiring layer 269. The bottom filler 270 surrounds a plurality of bump connectors 249. Then as... Figure 10i As shown, Figure 10h The resulting structure is inverted, and solder balls 295 are formed on the pads 212 of the substrate 210.

[0079] like Figure 10j As shown, Figure 10i The resulting structure is inverted, and a cutting process is performed using tool 1055, passing through the first dielectric layer 263 of the first redistribution layer 261 and the substrate 210. Then, as... Figure 10kAs shown, the FAU 230 is attached to the surface of the first dielectric layer 263 via the adhesive layer 232. The FAU 230 is disposed opposite to the reflective element 250.

[0080] like Figure 10l As shown, this forms the final package structure. During the bonding process of the FAU 230, the FAU 230 may tilt, resulting in an incorrect optical path PG. This can be addressed using methods such as reference [reference missing]. Figures 1 to 2c The adjustment device shown changes the tilt angle of the reflective element 250 to adjust the angle of the light path PG entering the light-receiving surface 222, so as to correctly guide the light path PG to the light-receiving surface 222. Thus, the adjustment device 240 can be used to correct the light path PG, enabling light to be transmitted along the correct path between the FAU 230 and the PIC 220. After determining an appropriate tilt angle of the reflective element 250 to compensate for the tilt of the FAU, an adhesive material can be provided to fix the reflective element 250 to maintain its tilt angle.

[0081] According to another aspect of the present invention, a semiconductor packaging structure is also provided. Figure 11 This is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 11 As shown, the semiconductor package structure 200 includes a fan-out circuit layer (carrier) 310, which comprises multiple dielectric layers 312 and multiple RDLs 314 formed within the dielectric layers. The thickness of each dielectric layer 312 can range from 5 μm to 20 μm. The RDLs 314 can be designed with fine lines (e.g., linewidth / spacing L / S < 2 μm / 2 μm) for more I / O designs. Solder balls 395 can be disposed below the fan-out circuit layer 310 for connection to external components. In some embodiments, the diameter of the solder balls 395 can range from 30 μm to 200 μm. The pitch between the solder balls 395 can range from 50 μm to 400 μm. By using a fan-out circuit layer 310 with RDLs instead of a substrate, miniaturization and low cost of the package structure can be achieved.

[0082] A PIC 320 and a FAU 330 are disposed above the fan-out line layer 310, with the FAU 330 positioned above the PIC 320. The PIC 320 has a light-receiving surface 322 for receiving light from the FAU 330. In the illustrated embodiment, a light guide component 323, such as a raster, is disposed on the surface of the PIC 320 opposite to the FAU 330. The light-receiving surface 322 of the PIC 320 is the surface of the light guide component 323 facing the FAU 330. In other embodiments, the light-receiving surface 322 may also be other components or surfaces of the PIC 320 for receiving light from the FAU 330. An optical path PG exists between the PIC 320 and the FAU 330, from the FAU 330 to the light-receiving surface 322 of the PIC 320. The optical path PG may be greater than a plurality of period time wavelengths.

[0083] An adjustment device 340 is disposed below the PIC 320, and the adjustment device 340 can be positioned below the light-receiving surface 322 of the PIC 320. The adjustment device 340 is configured to adjust the angle between the optical path PG entering the light-receiving surface 322 and the light-receiving surface 322, so that the optical path PG from the FAU 330 to the PIC 320 is correctly guided to the light-receiving surface 322. For example, if a component in the semiconductor package structure 2000 is misaligned, it will cause a change in the angle between the optical path and the light-receiving surface 322, resulting in the optical path PG failing to reach the light-receiving surface 322 correctly. In such a case, the adjustment device 340 can be used to adjust the tilt angle of the light-receiving surface 322, thereby adjusting the angle between the optical path and the light-receiving surface 322, so that the optical path PG can be correctly guided to the light-receiving surface 322.

[0084] An adjustment device 340 is disposed below the light-receiving surface 322 to adjust the tilt angle of the light-receiving surface 322. Specifically, the PIC 320 is constructed having a main body 328 and a cantilever 329 connected to the main body 328. The main body 328 of the PIC 320 can be fixed to the upper surface of the fan-out line layer 310 by an adhesive layer 333. The total width of the main body 328 and the cantilever 329 of the PIC 320 can be in the range of 10 μm to 1000 μm, and the thickness of the main body 328 of the PIC 320 can be in the range of 20 μm to 200 μm. The tilt angle formed between the cantilever 329 and the horizontal direction (i.e., the tilt angle of the light-receiving surface 322) can be in the range of 10° to 80°. The thickness of the cantilever 329 can be in the range of 5 μm to 20 μm.

[0085] The cantilever 329 extends laterally on and is spaced apart from the fan-out circuit layer 310. The spacing between the lower surface of the cantilever 329 and the upper surface of the fan-out circuit layer 310 can be in the range of 5 μm to 100 μm. In the illustrated embodiment, the thickness of the cantilever 329 of the PIC 320 is less than the thickness of the body 328, so that a gap is formed between the cantilever 329 and the fan-out circuit layer 310. A light-receiving surface 322 is disposed on the upper surface of the cantilever 329. Since there is a gap between the cantilever 329 and the fan-out circuit layer 310, the cantilever 329 can be tilted by changing the vertical distance between the end of the cantilever 329 away from the body 328 and the fan-out circuit layer 310, that is, changing the tilt angle of the light-receiving surface 322 on the cantilever 329. An adjustment device 340 can be disposed between the lower surface of the cantilever 329 and the fan-out circuit layer 310. Furthermore, the adjustment device 340 is configured to adjust the distance between the end of the cantilever 329 away from the main body 328 and the fan-out line layer 310, so as to adjust the tilt angle of the light receiving surface 322.

[0086] In some embodiments, the adjusting device 340 includes a magnet 341 and a coil 343 located within a gap between the cantilever 329 and the fan-out line layer 310. In the illustrated embodiment, the magnet 341 is disposed on the lower surface of the cantilever 329, and the coil 343 is disposed on the fan-out line layer 310 opposite to the magnet 341. In other embodiments, the coil 343 may be disposed on the lower surface of the cantilever 329, and the magnet 341 may be disposed on the fan-out line layer 310. The thickness of the magnet 341 may be in the range of 2 μm to 20 μm. The width CW of the coil 343 may be in the range of 2 μm to 20 μm.

[0087] In some embodiments, magnet 341 is formed of a magnetic material. The magnetic material can be a magnet layer or a magnet paste; the magnet layer can be formed from a palladium magnet alloy through processes such as sputtering. The magnet paste can be made from a magnet through processes such as printing. The magnet paste can be a mixture of materials such as magnet alloy powder (solid content approximately 60%–80%), a polymer binder (solid content approximately 10%–20%), resin, and a volatile solvent (solvent, solid content approximately 10%–20%). The magnet material powder in the magnet layer and / or magnet paste can be magnetite (iron II or iron III oxides; powders of Fe3O4, barium oxide, or strontium oxide), artificial magnets (e.g., Alnico, which contains alloying elements such as aluminum, nickel, and cobalt in iron), rare earth magnets (e.g., neodymium magnets (such as neodymium iron boron iron) and samarium cobalt magnets).

[0088] A coil 343 is placed on the fan-out line layer 310. A magnet 341 is fabricated on the lower surface of the cantilever 329 of the PIC 320. By passing current through the coil 343, a magnetic force can be generated between the magnet 341 and the coil 343. The magnetic force can attract or repel the magnet 341 by the coil 343. The distance between the end of the cantilever 329 away from the main body 328 and the fan-out line layer 310 can be adjusted, thereby causing the cantilever 329 to shift counterclockwise or clockwise and have a tilt angle. Therefore, the angle between the optical path PG and the light-receiving surface 322 can be adjusted using magnetic force. The position of the cantilever 329 can be adjusted by controlling the magnetic force according to the path of the optical path PG, which can effectively control the optical path and optical performance.

[0089] The semiconductor package structure 2000 also includes a molding compound 380. The molding compound 380 is located on the fan-out line layer 310 and encapsulates the body 328 of the PIC 320. The molding compound 380 has a cavity 368 to house the cantilever 329 of the PIC 320 and an adjustment device 340 to adjust the tilt angle of the light-receiving surface 322. A light-absorbing unit (FAU) 330 is located on the molding compound 380 and spans the cavity 368. In the illustrated embodiment, the FAU 330 is secured to the molding compound 380 by an adhesive layer 383. In some embodiments, the height of the molding compound 380 can be in the range of 50 μm to 500 μm. The thickness of the adhesive layer 383 between the FAU 330 and the molding compound 380 can be in the range of 10 μm to 50 μm.

[0090] By using molding compound 380 to form cavity 368 below FAU 330, the optical path PG from FAU 330 directly to the light-receiving surface 322 of PIC 320 is shortened, avoiding light loss due to reflection or refraction. Furthermore, the sidewalls of molding compound 380 defining cavity 368 can be inclined. Molding compound 380 can be used to protect PIC 320, and the inclined sidewalls of cavity 368 formed by molding compound 380 facilitate light collection.

[0091] The semiconductor package structure 2000 may further include an EIC (Electrical Integrated Circuit) 390, which is located on the fan-out line layer 310 and encapsulated by a molding compound 380. In some embodiments, the width of the EIC 390 may be in the range of 10 μm to 1000 μm, and the thickness of the EIC 390 may be in the range of 20 μm to 200 μm. In some embodiments, the lower surface of the EIC 390 has microbumps 349, and the microbumps 349 are electrically connected to the fan-out line layer 310. In some embodiments, the diameter of the microbumps 349 may be in the range of 10 μm to 30 μm. The pitch between two adjacent microbumps 349 may be in the range of 15 μm to 60 μm. Furthermore, a PIC 320 may be connected to the fan-out line layer 310 via a lead 348. By flipping the EIC 390 and using microbumps 349 to bond the EIC 390, and by using leads 348 to bond the PIC 320 to the fan-out line layer 310, lower costs can be achieved and KGD (Known Good Die) loss issues can be avoided.

[0092] In this embodiment, the FAU 330 and PIC 320 are face-to-face. A portion of the PIC region below the light-receiving surface 322 of the PIC 320 is thinned to form a cantilever 329 structure. An adjustment device 340, consisting of a coil 343 and a magnet 341, is placed below the cantilever 329 and between it and the fan-out circuit layer 310. Magnetic force is used to control the tilt angle of the cantilever 329 of the PIC 320, adjusting the angle between the optical path PG and the light-receiving surface 322. This ensures that the optical path PG between the FAU 330 and the light-receiving surface 322 of the PIC 320 can be correctly guided into the light-receiving surface 322 of the PIC 320.

[0093] Figures 12a to 12h This is a schematic diagram of the various stages in a method for forming a semiconductor package structure (PIC) according to another embodiment of the present invention. First, as... Figure 12a As shown, a PIC 320 is provided, and the surface of the PIC 320 has a light guide component 323, the light guide component 323 having a light receiving surface 322. The surface of the PIC 320 also has a pad 1202.

[0094] like Figure 12b As shown, the carrier 1206 is attached to the PIC 320 via the buffer layer 1204, and the resulting structure is inverted. Figure 12c As shown, a mask layer 1210 is applied to the surface of the PIC 320 opposite to the light guide component 323. (As shown...) Figure 12dAs shown, the mask layer 1210 is patterned, and an opening 1212 is formed in the mask layer 1210 to expose the PIC 320.

[0095] like Figure 12e As shown, a portion of the PIC 320 is removed by etching using a patterned mask layer 1210, thereby forming a recess 1215 in the PIC 320. The mask layer 1210 is then removed, and another mask layer 1216 is applied over the PIC 320 with the recess.

[0096] like Figure 12f As shown, a portion of the mask layer 1216 at the bottom of the recess 1215 is removed, forming an opening 1218 in the mask layer 1216 to expose the PIC 320. A magnet 341 is formed within the opening 1218 using a magnetic material. Then, as... Figure 12g As shown, the mask layer 1216 is removed, thereby forming the magnet 341 located in the recess 1215 of the PIC 320. Then, the buffer layer 1204 and the carrier 1206 are removed, and the resulting structure is inverted. Figure 12h As shown, the PIC 320 is cut from the edge of the recess in a process 1220 to form a single PIC 320. The single PIC 320 has a body 328 and a cantilever 329 connected to the body 328.

[0097] Figures 13a to 13m This is a schematic diagram of the various stages in a method for forming a semiconductor package structure according to another embodiment of the present invention using a PIC. Figure 13a As shown, a carrier 1301 is provided, and the carrier 1301 has a plurality of pads 1302.

[0098] like Figure 13b As shown, a dielectric layer 312 is applied to the carrier 1301 and the pad 1302. The dielectric layer 312 is patterned to form openings 1305 within it, and a seed layer 1308 is formed on the dielectric layer 312 and within the openings 1305. Figure 13c As shown, a mask layer 1310 is formed on the seed layer 1308.

[0099] like Figure 13d As shown, the mask layer 1310 in the opening 1305 is removed, and a plurality of openings 1314 are further formed in the mask layer 1310. The openings 1314 may be located above the opening 1305 in the dielectric layer 312. A metallic material 1320 is formed within the openings 1314. Figure 13e As shown, the mask layer 1310 and the seed layer 1308 covered by the mask layer 1310 are removed. The remaining seed layer 1308 and the metal material 1320 form RDL 314.

[0100] like Figure 13fAs shown, another dielectric layer 312 is superimposed on top of dielectric layer 312. (As illustrated...) Figure 13g As shown, through with Figures 13b to 13e A similar process is performed to form an upper RDL layer within the dielectric layer. This forms a fan-out circuit layer 310 that includes the dielectric layer and the RDL. Furthermore, a coil 343 is formed on the fan-out circuit layer 310.

[0101] like Figure 13h As shown, EIC 390 is bonded on fan-out line layer 310. Underfill 370 is formed between EIC 390 and fan-out line layer 310.

[0102] like Figure 13i As shown, Figure 12h The obtained PIC 320 is attached to the fan-out circuit layer 310, such that the magnet 341 and the coil 343 are facing each other, and the magnet 341 and the coil 343 together form the adjustment device 340. The PIC 320 can be attached to the fan-out circuit layer 310 through the adhesive layer 333. A lead 348 is formed, which electrically connects the PIC 320 to the fan-out circuit layer 310.

[0103] like Figure 13j As shown, a molding compound 380 forms the body 328 encapsulating the EIC 390 and PIC 320. The molding compound 380 has a cavity 368 for accommodating the cantilever 329. The cavity 368 may have inclined sidewalls defined by the molding compound 380.

[0104] like Figure 13k As shown, remove carrier 1301. Figure 13k The resulting structure is inverted, such as Figure 13l As shown, the fan-out circuit layer 310 is thinned so that the pad 1302 protrudes from the surface of the fan-out circuit layer 310. Then, solder balls 395 are formed on the pad 1302.

[0105] like Figure 13m As shown, the FAU 330 is placed on the molding compound 380 and across the cavity 368. The molding compound 380 and the fan-out circuit layer 310 are cut along the position shown by the dashed line to form the final package structure. Subsequently, the optical path between the FAU 330 and the PIC 320 in the package structure can be tested, and the tilt angle of the light-receiving surface 322 can be adjusted based on the test results to ensure the optical path is correctly guided to the light-receiving surface 322. In some embodiments, the tilt angle of the light-receiving surface 322 can be fixed using an adhesive material. In other embodiments, the tilt angle of the light-receiving surface 322 may not be fixed, allowing for real-time adjustment of the tilt angle to ensure the optical path is correctly guided to the light-receiving surface.

[0106] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: Carrier plate; An optical integrated circuit and an optical element are located above the carrier plate, and an optical path is formed between the optical integrated circuit and the optical element from the optical element to the light-receiving surface of the optical integrated circuit. An adjustment device, adjacent to the optical integrated circuit, is configured to adjust the optical path entering the light-receiving surface to correctly guide the optical path to the light-receiving surface; The optical element is located above the optical integrated circuit, and the optical integrated circuit has a main body and a cantilever connected to the main body. The cantilever extends laterally on the carrier plate and is spaced apart from the carrier plate. The light-receiving surface is located on the cantilever. The adjustment device is configured to adjust the distance between the end of the cantilever away from the main body and the carrier plate, so as to adjust the tilt angle of the light-receiving surface.

2. The semiconductor packaging structure according to claim 1, characterized in that, The regulating device includes: A magnet and a coil are located within the gap between the cantilever and the carrier plate, with one of the magnet and the coil located on the carrier plate, and the other of the magnet and the coil connected below the cantilever. The magnet and the coil are configured to generate magnetic force to adjust the distance between the end of the cantilever away from the body and the carrier plate.

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