Method for manufacturing array substrate, array substrate and display device
By adding a copper etching process and simplifying the photoresist coating steps in the array substrate fabrication, the production capacity bottleneck of high-end IGZO HFS models has been solved, achieving cost savings and increased production capacity, and improving display performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2022-02-10
- Publication Date
- 2026-07-24
Smart Images
Figure CN114551349B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display device technology, and in particular to a method for fabricating an array substrate, the array substrate, and a display device. Background Technology
[0002] High-resolution, high-refresh-rate IGZO HFS high-end models all employ metal (M3) traces (usually copper) to reduce COM ITO (CITO) resistance, thereby ensuring COM ITO uniformity. However, these high-end IGZO HFS models use PFA material to fabricate the planarization layer, making it difficult to achieve CITO and M3 through HTM PH and 3W1D processes (including copper wet etching, ITO wet etching, oxygen ashing, and copper wet etching). This is because PFA apertures are very deep, resulting in a thick photoresist (PR) layer at the PFA apertures during photolithography, which is difficult to completely remove after exposure and development, posing a risk of PR residue. Increasing the exposure dose can cause PR film breakdown in the halftone areas, leading to the etching of some of the CITO that should be retained, resulting in these areas always appearing dark during display.
[0003] Therefore, CITO and M3 are mostly completed through two photolithography processes and two wet lithography processes, namely the IGZO HFS9Mask Normal process. However, the photolithography process is a bottleneck that limits production capacity, so reducing the time spent on the photolithography process is the key to improving production capacity. Summary of the Invention
[0004] This application provides a method for fabricating an array substrate, an array substrate, and a display device to solve the problem of low production capacity in array substrate manufacturing.
[0005] On one hand, this application provides a method for fabricating an array substrate, comprising:
[0006] A driving circuit layer is provided, the driving circuit layer including a planarization layer with a first via;
[0007] A common electrode layer and a contact electrode layer are sequentially formed on the planarization layer having the first via.
[0008] A photoresist layer is formed on the contact electrode layer;
[0009] The photoresist layer, the common electrode layer, and the contact electrode layer are patterned to form a second via, and the first via and the second via are connected.
[0010] Peel off the photoresist layer;
[0011] A first insulating layer and a pixel electrode layer are formed on the common electrode layer, the contact electrode layer, and the planarization layer.
[0012] In one possible implementation of this application, the second via includes a first sub-via, and the first mask includes a photolithographic area;
[0013] The step of patterning the photoresist layer, the common electrode layer, and the contact electrode layer to form a second via, wherein the first via and the second via are connected, includes:
[0014] The photoresist layer is exposed and developed using a first mask, and the photolithographic area is formed on the first via.
[0015] The contact electrode layer is etched in the photolithography area using a first etching process to form the first sub-hole, which is connected to the first via.
[0016] In one possible implementation of this application, the second via further includes a second sub-via;
[0017] After the step of etching the contact electrode layer in the photolithography area using the first etching process to form the first sub-hole, the method further includes:
[0018] The common electrode layer is etched in the photolithography area using a second etching process to form the second sub-hole, which is connected to the first sub-hole.
[0019] In one possible implementation of this application, after the step of patterning the photoresist layer, the common electrode layer, and the contact electrode layer to form the second via, the method further includes:
[0020] The photoresist layer is exposed and developed using a second photomask.
[0021] The contact electrode layer is etched using a wet etching process to form the contact electrode.
[0022] In one possible implementation of this application, the first driving circuit layer further includes a second insulating layer and a first metal layer, the planarization layer is disposed on the second insulating layer, the second insulating layer is disposed on the first metal layer, and the second insulating layer is exposed in the first via.
[0023] The step of forming a first insulating layer and a pixel electrode layer on the common electrode layer, the contact electrode layer, and the planarization layer includes:
[0024] A first insulating layer is formed on the common electrode layer, the contact electrode layer, and the planarization layer. The first insulating layer is located within the first via and covers the second insulating layer.
[0025] A third via is formed through the first insulating layer and the second insulating layer using a single patterning process, and the first metal layer is exposed in the third via.
[0026] In one possible implementation of this application, the step of providing a driving circuit layer includes:
[0027] Provide a substrate;
[0028] A patterned second metal layer, an interlayer insulating layer, a semiconductor layer, and the first metal layer are sequentially formed on the substrate.
[0029] A second insulating layer is formed on the first metal layer;
[0030] A planarization layer is formed on the second insulating layer;
[0031] The first via is formed on the planarization layer using a third etching process, so that the second insulating layer is exposed in the first via.
[0032] In one possible implementation of this application, after the step of forming the third via through the first insulating layer and the second insulating layer using a single patterning process, the method includes:
[0033] A pixel electrode layer is formed on the second insulating layer, the pixel electrode layer being formed within the third via and covering the first metal layer;
[0034] The pixel electrode layer is patterned using a third etching process to form multiple spaced pixel electrodes.
[0035] In one possible implementation of this application, the thickness of the photoresist layer ranges from 1.2 μm to 1.6 μm.
[0036] On the other hand, this application also provides an array substrate, which is formed using the array substrate fabrication method described above.
[0037] On the other hand, this application also provides a display device including the aforementioned array substrate.
[0038] This application provides a method for fabricating an array substrate, an array substrate, and a display device. The fabrication method includes: providing a driving circuit layer, the driving circuit layer including a planarization layer with a first via; forming a common electrode layer and a contact electrode layer sequentially on the planarization layer with the first via; forming a photoresist layer on the contact electrode layer; patterning the photoresist layer, the common electrode layer, and the contact electrode layer to form a second via, the first via and the second via being connected; removing the photoresist layer; and forming a first insulating layer and a pixel electrode layer on the common electrode layer, the contact electrode layer, and the planarization layer. Compared with the prior art, the fabrication method of this application adds only one copper etching process but reduces one photoresist coating process and one photoresist stripping process. Therefore, when the common electrode layer and the contact electrode layer are patterned, only one photolithography process is required, thereby increasing the photolithography process throughput. This can help improve the throughput of the entire array substrate fabrication process, thus achieving cost savings and increased throughput. Attached Figure Description
[0039] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0040] Figure 1 This is a schematic flowchart illustrating the fabrication method of the array substrate provided in this application.
[0041] Figure 2 This is another schematic diagram of the fabrication method of the array substrate provided in this application.
[0042] Figure 3 A schematic flowchart of step S40 in the method for fabricating the array substrate provided in this application.
[0043] Figure 4 A schematic flowchart of step S10 in the method for fabricating the array substrate provided in this application.
[0044] Figure 5 This is a schematic diagram of the array substrate structure formed by the method for fabricating the array substrate provided in this application. Detailed Implementation
[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0046] In the description of this application, it should be understood that the features referred to by the terms "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. It should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly; for example, they may refer to a direct connection or an indirect connection through an intermediate medium, or they may refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0047] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0048] Please refer to Figures 1-4 This application provides a method for fabricating an array substrate, combined with... Figure 1 and Figure 2 As shown, the process includes the following steps S10-S60:
[0049] S10. A driving circuit layer 100 is provided, the driving circuit layer 100 including a planarization layer 200 having a first via 11.
[0050] The planarization layer (Polymer Film on Array, PFA) 200 is used to modify the surface smoothness of the underlying film, achieving planarization and preventing mutual interference of electric fields. The planarization layer 200 can be made of one or more of the following materials: acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyacrylate, polycarbonate, polyimide, and polystyrene.
[0051] S20. A common electrode layer 300 and a contact electrode layer 400 are sequentially formed on a planarization layer 200 having a first via 11.
[0052] The contact electrode layer 400 is used to form a parallel connection with the metal in the common electrode layer 300, which helps to reduce the resistance of the common electrode layer 300.
[0053] S30. A photoresist layer 500 is formed on the contact electrode layer 400.
[0054] The thickness of the photoresist layer 500 ranges from 1.2 μm to 1.6 μm. Specifically, the thickness of the photoresist layer 500 can be 1.2 μm, 1.4 μm, or 1.6 μm. Compared to existing photoresists that typically have a thickness of 2 μm, the photoresist layer 500 in this application is thinned, thereby saving material and reducing costs.
[0055] S40. The photoresist layer 500, the common electrode layer 300 and the contact electrode layer 400 are patterned to form a second via 12, and the first via 11 and the second via 12 are connected.
[0056] S50, stripped photoresist layer 500.
[0057] S60, a first insulating layer 600 and a pixel electrode layer 700 are formed on the common electrode layer 300, the contact electrode layer 400 and the planarization layer 200.
[0058] The common electrode layer 300 and the pixel electrode layer 700 are used to provide voltage to the light-emitting layer, such as an organic light-emitting layer or a liquid crystal layer. Specifically, either the common electrode layer 300 or the pixel electrode layer 700 can be a single-layer structure of a metal oxide, such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), etc., or can have a stacked structure of silver and indium tin oxide (ITO / Ag / ITO), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and indium tin oxide (ITO / APC / ITO), etc. This embodiment does not impose specific limitations.
[0059] The preparation method of this application embodiment adds a copper etching process and reduces a photoresist coating process compared with the prior art. Therefore, when the common electrode layer 300 and the contact electrode layer 400 are patterned, only one photolithography process is required, thereby increasing the photolithography process capacity. This can help improve the overall capacity of the array substrate process, and thus help achieve cost savings and increased capacity.
[0060] Please combine Figure 2 and Figure 3 In some embodiments, the second via 12 includes a first sub-via 121, and the first mask includes a photolithographic region 501. Correspondingly, step S40, which involves patterning the photoresist layer 500, the common electrode layer 300, and the contact electrode layer 400 to form the second via 12, and connecting the first via 11 and the second via 12, specifically includes the following steps S401-S402:
[0061] S401. The photoresist layer 500 is exposed and developed using the first mask, and the photolithography area 501 is formed on the first via 11.
[0062] Among them, the photolithography area 501 is the area without photoresist coverage. The photoresist patterning process facilitates the subsequent etching process.
[0063] S402. The first etching process is used to etch the contact electrode layer 400 in the photolithography area 501 to form the first sub-hole 121, which is connected to the first via 11.
[0064] The contact electrode layer 400 can be made of copper, and the first etching process can be a copper wet etching process.
[0065] In some embodiments, the second via 12 further includes a second sub-via 122; correspondingly, after step S402, which involves etching the contact electrode layer 400 in the photolithography region 501 using the first etching process to form the first sub-via 121, step S403 may also be included:
[0066] S403. Using a second etching process, the common electrode layer 300 is etched in the photolithography area 501 to form a second sub-via 122, which is connected to the first sub-via 121. The first sub-via 121 is formed in the photoresist layer 500, and the second sub-via 122 is formed in the common electrode layer 300. Before the photoresist layer 500 is stripped, the first sub-via 121, the second sub-via 122, and the first via 11 are interconnected.
[0067] The common electrode layer 300 can be made of ITO material, and correspondingly, the second etching process can be an ITO wet etching process.
[0068] In some embodiments, after step S40, which involves patterning the photoresist layer 500, the common electrode layer 300, and the contact electrode layer 400 to form the second via 12, the following steps S41-S42 are further included:
[0069] S41. The photoresist layer 500 is exposed and developed using a second photomask.
[0070] In this embodiment, based on the first mask, a second mask is used to continue exposing and developing the photoresist layer 500 to form the photoresist pattern required for etching the contact electrode.
[0071] S42. The contact electrode layer 400 is etched using a wet etching process to form the contact electrode.
[0072] In this embodiment, the contact electrode layer 400 can be made of copper material. Therefore, a copper wet etching process is used to etch the contact electrode layer 400 to form a patterned contact electrode. The contact electrode is used to form a parallel connection with the metal in the common electrode layer 300, which helps to reduce the resistance of the common electrode layer 300.
[0073] In some embodiments, please refer to Figure 5 The first driving circuit layer 100 further includes a second insulating layer 106, and a planarization layer 200 is disposed on the second insulating layer 106. The second insulating layer 106 is exposed through the first via 11. The second insulating layer 106 may be a passivation layer (PV layer) used to achieve insulation between metal film layers.
[0074] Correspondingly, step S50, the step of forming the first insulating layer 600 and the pixel electrode layer 700 on the common electrode layer 300, the contact electrode layer 400, and the planarization layer 200, specifically includes the following steps S501-S502:
[0075] S501. A first insulating layer 600 is formed on the common electrode layer 300, the contact electrode layer 400 and the planarization layer 200. The first insulating layer 600 is located in the first via 11 and covers the second insulating layer 106.
[0076] S502, A third via 13 is formed by a one-time patterning process, penetrating the first insulating layer 600 and the second insulating layer 106, and the first metal layer 105 is exposed in the third via 13.
[0077] The third via 13 is formed in the first insulating layer 600 and the second insulating layer 106, wherein at least a planarization layer 200, a common electrode layer 300, and a contact electrode layer 400 are also included between the first insulating layer 600 and the second insulating layer 106.
[0078] In some embodiments, after step S502, which involves forming a third via 13 through the first insulating layer 600 and the second insulating layer 106 using a one-time patterning process, the following steps S503-S504 are included:
[0079] S503, A pixel electrode layer 700 is formed on the second insulating layer 106. The pixel electrode layer 700 is formed in the third via 13 and covers the first metal layer 105.
[0080] S504. The pixel electrode layer 700 is patterned using an etching process to form multiple pixel electrodes spaced apart.
[0081] In some embodiments, please refer to Figure 4 and Figure 5Step S10, the step of providing a driving circuit layer 100, specifically includes the following steps S101-S105.
[0082] S101. A substrate 101 is provided. The substrate 101 can be a flexible substrate or a rigid substrate. For example, the flexible substrate layer can be formed of polyimide (PI), and the rigid substrate can be a rigid material such as glass. The substrate can be a single-layer or multi-layer structure, without special limitation.
[0083] S102, A patterned second metal layer 102, an interlayer insulating layer 103, a semiconductor layer 104, and a first metal layer 105 are sequentially formed on a substrate 101.
[0084] For example, the second metal layer 102 is a gate layer and the first metal layer 105 is a source / drain layer.
[0085] S103, A second insulating layer 106 is formed on the first metal layer 105.
[0086] S104. A planarization layer 200 is formed on the second insulating layer 106.
[0087] S105. An etching process is used to form a first via 11 on the planarization layer 200, so that the second insulating layer 106 is exposed in the first via 11.
[0088] To better implement the array substrate fabrication method of this application, embodiments of this application further improve an array substrate, which is fabricated using the array substrate preparation method. Compared with the prior art, the array substrate of this application embodiment only adds one copper etching process, but reduces one photoresist coating process. Therefore, when the common electrode layer 300 and the contact electrode layer 400 are patterned, only one photolithography process is required, thereby increasing the photolithography process throughput. This can help improve the throughput of the entire array substrate fabrication process, thereby achieving cost savings and increased throughput.
[0089] This application also provides a display device, which includes an array substrate. Since this display device has the aforementioned array substrate, it has all the same beneficial effects, and will not be described again in this embodiment. The display device provided in this embodiment can be a liquid crystal display device, for example, an IPS or FFS type liquid crystal display device, i.e., the common electrode and pixel electrode are formed on the same substrate (i.e., the array substrate). This application does not specifically limit the applicability of the display device; it can be any product or component with display function, such as a television, laptop computer, tablet computer, wearable display device (e.g., smart bracelet, smartwatch), mobile phone, virtual reality device, augmented reality device, in-vehicle display, or advertising light box.
[0090] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not detailed in a particular embodiment, please refer to the relevant descriptions in other embodiments. In specific implementation, each of the above units or structures can be implemented as an independent entity, or can be arbitrarily combined to be implemented as the same or several entities. For specific implementations of the above units or structures, please refer to the preceding method embodiments, which will not be repeated here.
[0091] The foregoing has provided a detailed description of a method for preparing an array substrate, the array substrate itself, and a display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the embodiments of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of the embodiments of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating an array substrate, characterized in that, include: A driving circuit layer is provided, the driving circuit layer including a planarization layer with a first via; A common electrode layer and a contact electrode layer are sequentially formed on the planarization layer having the first via. A photoresist layer is formed on the contact electrode layer, and the thickness of the photoresist layer ranges from 1.2 μm to 1.6 μm; The photoresist layer is exposed and developed using a first mask. The first mask includes a photolithography area, which is formed on the first via. The photoresist layer forms an opening in the photolithography area. The contact electrode layer is etched in the photolithography area using a first etching process to form a first sub-hole, which is connected to the first via. The common electrode layer is etched in the photolithography area using a second etching process to form a second sub-hole, which is connected to the first sub-hole. The photoresist layer is exposed and developed using a second mask to form a photoresist pattern; The contact electrode layer is etched using a wet etching process to form the contact electrode; Peel off the photoresist layer; A first insulating layer and a pixel electrode layer are formed on the common electrode layer, the contact electrode layer, and the planarization layer.
2. The method for fabricating an array substrate according to claim 1, characterized in that, The driving circuit layer further includes a second insulating layer and a first metal layer. The planarization layer is disposed on the second insulating layer, the second insulating layer is disposed on the first metal layer, and the second insulating layer is exposed in the first via. The step of forming a first insulating layer and a pixel electrode layer on the common electrode layer, the contact electrode layer, and the planarization layer includes: A first insulating layer is formed on the common electrode layer, the contact electrode layer, and the planarization layer. The first insulating layer is located within the first via and covers the second insulating layer. A third via is formed through the first insulating layer and the second insulating layer using a single patterning process, and the first metal layer is exposed in the third via.
3. The method for fabricating an array substrate according to claim 2, characterized in that, The step of providing a driving circuit layer includes: Provide a substrate; A patterned second metal layer, an interlayer insulating layer, a semiconductor layer, and the first metal layer are sequentially formed on the substrate. A second insulating layer is formed on the first metal layer; A planarization layer is formed on the second insulating layer; The first via is formed on the planarization layer using a third etching process, so that the second insulating layer is exposed in the first via.
4. The method for fabricating an array substrate according to claim 2, characterized in that, After the step of forming the third via through the first insulating layer and the second insulating layer using a one-time patterning process, the method includes: A pixel electrode layer is formed on the second insulating layer, the pixel electrode layer being formed within the third via and covering the first metal layer; The pixel electrode layer is patterned using a third etching process to form multiple spaced pixel electrodes.
5. An array substrate, characterized in that, It is formed by the method of fabrication of the array substrate according to any one of claims 1-4.
6. A display device, characterized in that, Includes the array substrate as described in claim 5.
Citation Information
Patent Citations
Thin film transistor array substrate and display device
CN208111444U