Method for manufacturing array substrate, array substrate and display device

By adding a copper etching process and simplifying the photoresist coating steps in the array substrate fabrication, the production capacity bottleneck of high-end IGZO HFS models has been solved, achieving cost savings and increased production capacity, and improving display performance.

CN114551349BActive Publication Date: 2026-07-24GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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Patent Information

Application Number
CN202210126349.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-02-10
Publication Date
2026-07-24
Estimated Expiration
2042-02-10

AI Technical Summary

Technical Problem

In existing technologies, when preparing the planarization layer for high-end IGZO HFS models, CITO and M3 are difficult to complete through multiple photolithography and wet etching processes, resulting in a production capacity bottleneck. Furthermore, there is a high risk of photoresist residue at the PFA opening, which affects the display effect.

Method used

By adding a copper etching process during the array substrate fabrication process and reducing one photoresist coating and stripping process, a single photolithography process is used to form the patterning of the common electrode layer and the contact electrode layer, simplifying the fabrication process.

Benefits of technology

It increased the production capacity of photoresist processing, reduced costs, enhanced the process capacity of array substrates, reduced the risk of photoresist residue, and improved the display effect.

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Abstract

The application provides a preparation method of an array substrate, the array substrate and a display device. The preparation method comprises the following steps: providing a driving circuit layer, wherein the driving circuit layer comprises a planarization layer provided with a first via; forming a common electrode layer and a contact electrode layer on the planarization layer provided with the first via; forming a photoresist layer on the contact electrode layer; performing a patterning treatment on the photoresist layer, the common electrode layer and the contact electrode layer to form a second via, wherein the first via and the second via are communicated; stripping the photoresist layer; and forming a first insulating layer and a pixel electrode layer on the common electrode layer, the contact electrode layer and the planarization layer. The preparation method of the application only needs to increase a copper etching process once, reduces a photoresist coating process and a photoresist stripping process once, and thus only needs to adopt one yellow light process when the common electrode layer and the contact electrode layer are formed into patterns, so that the production capacity of the whole array substrate process can be improved, and cost saving and production capacity improvement can be realized.
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