amplification circuit
By introducing isolation and charging modules into the trigger, the power supply terminal is isolated and the output terminal is coupled to the power supply terminal for charging, which solves the problems of high power consumption and slow discharge of the sensitive amplifier trigger, and achieves a faster charging rate and lower power delay.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-11
- Publication Date
- 2026-06-19
AI Technical Summary
Triggers based on sensitive amplifiers suffer from high charging power consumption and slow discharge rate during the pre-charging phase, and also exhibit a large power delay product and poor robustness during use.
An isolation module is used to isolate the first power supply terminal and the second power supply terminal. The output terminal is coupled to the first power supply terminal for charging through a charging module. A sensing module is used to amplify the initial voltage, thereby reducing the number of charging nodes and increasing the discharge rate.
It reduces power loss, shortens data setup delay time, improves the robustness and charging rate of the amplifier circuit, and reduces the power delay product.
Smart Images
Figure CN114583925B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, an amplifier circuit. Background Technology
[0002] Flip-flops are important components in integrated circuits. Common flip-flops include transmission gate flip-flops (TGFF), pulse trigger flip-flops (PTFF), semi-dynamic flip-flops (SDFF), and sense amplifier flip-flops (SAFF).
[0003] During the pre-charge phase, the trigger based on the sensitive amplifier needs to charge the internal nodes of the trigger. There are a large number of these nodes, and there are also MOS transistors that are always in the on state when the SAFF is working. Therefore, the SAFF has the problems of high charging power consumption and slow discharge rate when in use. Summary of the Invention
[0004] One embodiment of this disclosure provides an amplifier circuit, including:
[0005] The isolation module isolates the first power supply terminal and the second power supply terminal based on the isolation signal.
[0006] The sampling module reads the input data;
[0007] The charging module couples the first output terminal and the second output terminal to the first power supply terminal based on the charging signal, and charges the first output terminal and the second output terminal to the initial voltage.
[0008] The sensing module amplifies the input data based on the amplified signal, a first output terminal with an initial voltage, a second output terminal with an initial voltage, and a second power supply terminal.
[0009] In some embodiments, the input data includes:
[0010] The first input data and the second input data are opposite signals.
[0011] In some embodiments, the isolation module includes:
[0012] The first isolation unit has a first end coupled to a first output end and a second end coupled to a second power supply end, and is used to isolate the first output end and the second power supply end based on an isolation signal.
[0013] The second isolation unit has a first end coupled to the second output terminal and a second end coupled to the second power supply terminal, and is used to isolate the second output terminal from the second power supply terminal based on the isolation signal.
[0014] In some embodiments, the isolation module includes:
[0015] The first isolation unit includes a first N-type transistor, with a first terminal coupled to a first output terminal, a second terminal coupled to a second power supply terminal, and a control terminal coupled to an isolation signal;
[0016] The second isolation unit includes a second N-type transistor, with a first terminal coupled to a second output terminal, a second terminal coupled to a second power supply terminal, and a control terminal coupled to an isolation signal.
[0017] In some embodiments, the sensing module includes: a first P-type transistor, a first terminal coupled to a first power supply terminal, a second terminal coupled to a first output terminal, and a control terminal coupled to the second output terminal;
[0018] The second P-type transistor has a first terminal coupled to a first power supply terminal, a second terminal coupled to a second output terminal, and a control terminal coupled to the first output terminal.
[0019] The third N-type transistor has a first terminal coupled to the second terminal of the first isolation unit, a second terminal coupled to the second power supply terminal, and a control terminal coupled to the second output terminal.
[0020] The fourth N-type transistor has a first terminal coupled to the second terminal of the second isolation unit, a second terminal coupled to the second power supply terminal, and a control terminal coupled to the first output terminal.
[0021] In some embodiments, the sampling module includes:
[0022] The first sampling unit includes a fifth N-type transistor for reading the first input data based on the amplified signal;
[0023] The second sampling unit includes a sixth N-type transistor for reading the second input data based on the amplified signal.
[0024] In some embodiments, the fifth N-type transistor includes:
[0025] The first terminal is coupled to the second terminal of the first isolation unit, the second terminal is coupled to the first terminal of the third N-type transistor, and has a control terminal coupled to the first input data; or
[0026] The first terminal is coupled to the second terminal of the third N-type transistor, the second terminal is coupled to the second power supply terminal, and has a control terminal coupled to the first input data.
[0027] In some embodiments, the sixth N-type transistor includes:
[0028] The first terminal is coupled to the second terminal of the second isolation unit, the second terminal is coupled to the first terminal of the fourth N-type transistor, and has a control terminal coupled to the second input data; or
[0029] The first terminal is coupled to the second terminal of the fourth N-type transistor, the second terminal is coupled to the second power supply terminal, and has a control terminal coupled to the second input data.
[0030] In some embodiments, it also includes:
[0031] A noise reduction module is used to respond to input data and prevent errors in the output signals of the first and second output terminals caused by changes in the input data while the amplified signal remains in an effective state. The noise reduction module includes:
[0032] The first noise reduction unit has a first end coupled to the first end of the first sampling unit and a second end coupled to the second end of the first sampling unit, and is used to respond to the second input data;
[0033] The second noise reduction unit has a first end coupled to the first end of the second sampling unit and a second end coupled to the second end of the second sampling unit, and is used to respond to the first input data.
[0034] In some embodiments, the noise reduction module includes:
[0035] The first noise reduction unit includes a seventh N-type transistor, with its first terminal coupled to the first terminal of a fifth N-type transistor, its second terminal coupled to the second terminal of the fifth N-type transistor, and a control terminal coupled to the second input data.
[0036] The second noise reduction unit includes an eighth N-type transistor, with its first terminal coupled to the first terminal of the sixth N-type transistor, its second terminal coupled to the second terminal of the sixth N-type transistor, and a control terminal coupled to the first input data.
[0037] In some embodiments, including:
[0038] The seventh N-type transistor has a weaker conduction capability than the fifth N-type transistor;
[0039] The conduction capability of the eighth N-type transistor is weaker than that of the sixth N-type transistor.
[0040] In some embodiments, the charging module includes:
[0041] The first charging unit has a first end coupled to a first power supply end and a second end coupled to a first output end, used to couple the first output end to the first power supply end based on a charging signal.
[0042] The second charging unit has a first end coupled to a first power supply end and a second end coupled to a second output end, used to couple the second output end to the first power supply end based on a charging signal.
[0043] In some embodiments, the charging module includes:
[0044] The first charging unit includes a third P-type transistor, with a first terminal coupled to a first power supply terminal, a second terminal coupled to a first output terminal, and a control terminal coupled to a charging signal.
[0045] The second charging unit includes a fourth P-type transistor, with a first terminal coupled to a first power supply terminal, a second terminal coupled to a second output terminal, and a control terminal coupled to a charging signal.
[0046] In some embodiments, including:
[0047] The isolation signal and the charging signal are the same signal;
[0048] When the isolation signal is active, the amplified signal is inactive; when the isolation signal is inactive, the amplified signal is active.
[0049] The first output terminal outputs the amplified second input data.
[0050] The second output terminal outputs the amplified first input data.
[0051] In some embodiments, the amplifier circuit further includes:
[0052] The latch module has a first terminal coupled to the first output terminal and a second terminal coupled to the second output terminal, and is used to output amplified input data.
[0053] The amplification circuit provided in this embodiment includes an isolation module, a charging module, a sampling module, and a sensing module. The isolation module isolates a first power supply terminal and a second power supply terminal from each other based on an isolation signal. Upon receiving a charging signal, the charging module indirectly couples the first output terminal and the second output terminal to the first power supply terminal, allowing the first power supply terminal to charge the first and second output terminals. During the charging phase, the isolation module isolates the first and second output terminals from the second power supply terminal, ensuring that the second power supply terminal does not affect the voltages of the first and second output terminals, and eliminating the need to charge the sampling module, thus reducing power loss. The sensing module amplifies the input data based on the amplified signal, the first output terminal with an initial voltage, the second output terminal with an initial voltage, and the second power supply terminal. Because the number of charging nodes is reduced, upon receiving the amplified signal, the voltage of either the first or second output terminal is pulled down based on the input data at a faster rate, thereby reducing the power delay product. Attached Figure Description
[0054] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0055] Figure 1 This is a circuit diagram of a trigger based on a sensitive amplifier;
[0056] Figure 2 A circuit diagram of an amplifier circuit provided in an embodiment of this disclosure;
[0057] Figure 3 A circuit diagram of an amplifier circuit provided in another embodiment of this disclosure;
[0058] Figure 4 This is a timing diagram provided in an embodiment of the present disclosure when no noise reduction module is provided;
[0059] Figure 5 This is a timing diagram showing the setting of a noise reduction module according to an embodiment of the present disclosure.
[0060] Figure label:
[0061] D, First input data; DB, Second input data; S2, Isolation signal;
[0062] S1, charging signal; S3, amplification signal; VCC, first power supply terminal;
[0063] VSS, second power supply terminal; SB, first output terminal; RB, second output terminal;
[0064] 101. First sampling circuit; 102. Second sampling circuit; 103. Sensing circuit;
[0065] 104. First charging circuit; 105. Second charging circuit; 106. Impedance circuit;
[0066] 107. Isolation circuit; 108. Latch circuit;
[0067] 110, First sampling unit; 120, Second sampling unit; 20, Noise reduction module;
[0068] 210. First noise reduction unit; 220. Second noise reduction unit; 30. Isolation module;
[0069] 310, First isolation unit; 320, Second isolation unit; 40, Charging module;
[0070] 410, First charging unit; 420, Second charging unit; 50, Latch module.
[0071] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0072] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0073] like Figure 1 As shown, a trigger based on a sensitive amplifier includes N-type transistors N13 and N14. N-type transistor N13 is used to read first input data D, and N-type transistor N14 is used to read second input data DB. The amplifier circuit also includes P-type transistors P11 and P12, N-type transistors N11 and N12, which constitute a sensing unit. The sensing unit amplifies the first input data D and the second input data DB, and outputs the amplified second input data DB at the first output terminal SB, and outputs the amplified first input data D at the second output terminal RB.
[0074] The amplifier circuit also includes P-type transistors P13 and P14, which are used to charge the first output terminal SB and the second output terminal RB when the control signal CLK is low. The amplifier circuit also includes N-type transistor N16, which is used to isolate the first output terminal SB and the second output terminal RB from the second power supply terminal VSS when charging the first output terminal SB and the second output terminal RB.
[0075] The amplifier circuit also includes transistor N15, which is continuously turned on to ensure that the first output terminal SB and the second output terminal RB can still output the correct signal when there is an abnormal jump in the input data.
[0076] For example, when the first input data D changes from "1" to "0", the second input data DB changes from "0" to "1", while the clock signal remains high. When N-type transistor N13 switches from on to off, the first output terminal SB cannot discharge through N-type transistors N11, N13, and N16. However, the first output terminal SB can still discharge through N-type transistors N11, the continuously conducting N-type transistors N15, N14, and N16, creating a sufficient voltage difference between the first output terminal SB and the second output terminal RB, allowing both the first output terminal SB and the second output terminal RB to still output the correct signal.
[0077] However, in the above technical solution, when the clock signal is low and charging operation is performed, the first output terminal SB, the second output terminal RB, the first terminal A of N-type transistor N13, the first terminal B of N-type transistor N14, and the first terminal C of N-type transistor N16 need to be charged. This results in a large number of charging nodes and significant power loss. Furthermore, the gate of N-type transistor N13 continuously receives a high-level signal, keeping N13 in a constantly conducting state, which also leads to high power loss.
[0078] Furthermore, when the clock signal is high, multiple nodes need to be discharged, which results in a slow discharge rate and a large data setup delay, thus making the power delay product of the amplifier circuit relatively large.
[0079] Furthermore, when N-type transistor N13 is turned on, N-type transistor N14 is turned off. The first output terminal SB discharges through N-type transistors N11, N13, and N16, and the second output terminal RB can also discharge through N-type transistors N12, N15, N13, and N16. This reduces the voltage difference between the first output terminal SB and the second output terminal RB, which is not conducive to accurately outputting the amplified input data from the first output terminal SB and the second output terminal, thus degrading the robustness of the amplifier circuit.
[0080] like Figure 2 As shown, one embodiment of this disclosure provides an amplifier circuit, which includes a sampling module, an isolation module 30, a charging module 40, and a sensing module.
[0081] The isolation module 30 isolates the first power supply terminal VCC and the second power supply terminal VSS based on the isolation signal S2. The charging module 40 indirectly couples the first output terminal SB and the second output terminal RB to the first power supply terminal VCC based on the charging signal S1, charging the first output terminal SB and the second output terminal RB to their initial voltages. After charging the first output terminal SB and the second output terminal RB, the sampling module reads the input data, and the sensing module amplifies the input data based on the amplification signal S3, the first output terminal SB with its initial voltage, the second output terminal RB with its initial voltage, and the second power supply terminal VSS. That is, after receiving the amplification signal S3, the voltage of the first output terminal SB or the voltage of the second output terminal RB is lowered based on the input data. The amplified second input data DB is output from the first output terminal SB, and the amplified first input data D is output from the second output terminal RB.
[0082] An isolation module 30 is configured to isolate the first power supply terminal VCC and the second power supply terminal VSS from each other based on the isolation signal S2. Upon receiving the charging signal S1, the charging module 40 can indirectly couple the first output terminal SB and the second output terminal RB to the first power supply terminal VCC, allowing the first power supply terminal VCC to charge the first output terminal SB and the second output terminal RB. The second power supply terminal VSS will not affect the voltages of the first output terminal SB and the second output terminal RB. Furthermore, since only the first output terminal SB and the second output terminal RB need to be charged, and the sampling module does not need to be charged, the number of charging nodes can be reduced, thereby reducing power loss. After charging is complete, since the sampling module has not been charged, when the voltage of the first output terminal SB or the second output terminal RB is pulled down based on the input data read by the sampling module, the number of discharging nodes is less, the pull-down rate is faster, and the data establishment delay time is shortened, thereby reducing the power delay product.
[0083] Continue to refer to Figure 2 In some embodiments, the charging module 40 includes a first charging unit 410 and a second charging unit 420. The first charging unit 410 has a first terminal and a second terminal. The first terminal of the first charging unit 410 is directly coupled to the first power supply terminal VCC, and the second terminal is directly coupled to the first output terminal SB. The first charging unit 410 is used to indirectly couple the first output terminal SB to the first power supply terminal VCC based on the charging signal S1, so that the first power supply terminal VCC charges the first output terminal SB.
[0084] The second charging unit 420 has a first terminal and a second terminal. The first terminal of the second charging unit 420 is directly coupled to the first power supply terminal VCC, and the second terminal is directly coupled to the second output terminal RB. The second charging unit 420 is used to indirectly couple the second output terminal RB to the first power supply terminal VCC based on the charging signal S1, so that the first power supply terminal VCC charges the second output terminal RB.
[0085] In some embodiments, the isolation module 30 includes a first isolation unit 310 and a second isolation unit 320. The first isolation unit 310 has a first terminal and a second terminal. The first terminal of the first isolation unit 310 is directly coupled to the first output terminal SB, and the second terminal is indirectly coupled to the second power supply terminal VSS. The first isolation unit 310 is used to isolate the first output terminal SB from the second power supply terminal VSS based on the isolation signal S2. The first terminal of the second isolation unit 320 is directly coupled to the second output terminal RB, and the second terminal is indirectly coupled to the second power supply terminal VSS. The second isolation unit 320 is used to isolate the second output terminal RB from the second power supply terminal VSS based on the isolation signal S2. With this configuration, the first isolation unit 310 can isolate the first terminal of the first sampling unit 110 from the first power supply terminal VCC based on the isolation signal S2, and the second isolation unit 320 can isolate the first terminal of the second sampling unit 120 from the first power supply terminal VCC based on the isolation signal S2. When the first power supply terminal VCC charges the first output terminal SB and the second output terminal RB, the second power supply terminal VSS will not pull the voltage of the first output terminal SB and the second output terminal RB.
[0086] In some embodiments, the sampling module includes a first sampling unit 110 and a second sampling unit 120. A first end of the first sampling unit 110 is directly or indirectly coupled to a second end of the first isolation unit 310. In some embodiments, a first end of the second sampling unit 120 is directly or indirectly coupled to a second end of the second isolation unit 320.
[0087] For example: Continue to refer to Figure 2 The first end of the first sampling unit 110 is directly coupled to the second end of the first isolation unit 310, and the first end of the second sampling unit 120 is directly coupled to the second end of the second isolation unit 320. For example, refer to... Figure 3 The first terminal of the first sampling unit 110 is indirectly coupled to the second terminal of the first isolation unit 310, and the first terminal of the second sampling unit 120 is indirectly coupled to the second terminal of the second isolation unit 320. With this configuration, the first power supply terminal VCC will not charge the first and second terminals of the first sampling unit 110, nor the first and second terminals of the second sampling unit 120, thus reducing the number of charging nodes, thereby reducing power loss and improving the charging and discharging rate.
[0088] Continue to refer to Figure 2 In some embodiments, the first isolation unit 310 includes a first N-type transistor N1, and the second isolation unit 320 includes a second N-type transistor N2.
[0089] The first terminal of the first N-type transistor N1 is directly coupled to the first output terminal SB, and the second terminal of the first N-type transistor N1 is indirectly coupled to the second power supply terminal VSS. The control terminal of the first N-type transistor N1 is used to receive the isolation signal S2. The first terminal of the second N-type transistor N2 is directly coupled to the second output terminal RB, and the second terminal of the second N-type transistor N2 is indirectly coupled to the second power supply terminal VSS. The control terminal of the second N-type transistor N2 is used to receive the isolation signal S2.
[0090] In some embodiments, the sensing module includes a first P-type transistor P1, a second P-type transistor P2, a third N-type transistor N3, and a fourth N-type transistor N4. The first sampling unit 110 includes a fifth N-type transistor N5, and the second sampling unit 120 includes a sixth N-type transistor N6.
[0091] The first terminal of the first P-type transistor P1 is directly coupled to the first power supply terminal VCC, the second terminal of the first P-type transistor P1 is directly coupled to the first output terminal SB, and the control terminal of the first P-type transistor P1 is directly coupled to the second output terminal RB. The first terminal of the second P-type transistor P2 is directly coupled to the first power supply terminal VCC, the second terminal of the second P-type transistor P2 is directly coupled to the second output terminal RB, and the control terminal of the second P-type transistor P2 is directly coupled to the first output terminal SB.
[0092] The first terminal of the fifth N-type transistor N5 is directly coupled to the second terminal of the first N-type transistor N1. The second terminal of the fifth N-type transistor N5 is directly coupled to the first terminal of the third N-type transistor N3. The second terminal of the third N-type transistor N3 is directly coupled to the second power supply terminal VSS. The control terminal of the third N-type transistor N3 is directly coupled to the second output terminal RB.
[0093] The first terminal of the sixth N-type transistor N6 is directly coupled to the second terminal of the second N-type transistor N2. The second terminal of the sixth N-type transistor N6 is directly coupled to the first terminal of the fourth N-type transistor N4. The second terminal of the fourth N-type transistor N4 is directly coupled to the second power supply terminal VSS. The control terminal of the fourth N-type transistor N4 is directly coupled to the first output terminal SB.
[0094] Continue to refer to Figure 2 The current path between the first power supply terminal VCC and the second power supply terminal VSS includes, in sequence, the first P-type transistor P1, the first N-type transistor N1, the fifth N-type transistor N5, and the third N-type transistor N3; or, the current path between the first power supply terminal VCC and the second power supply terminal VSS includes, in sequence, the second P-type transistor P2, the second N-type transistor N2, the sixth N-type transistor N6, and the fourth N-type transistor N4.
[0095] In some embodiments, reference Figure 3As shown, the first terminal of the third N-type transistor N3 is connected to the second terminal of the first N-type transistor N1, the second terminal of the third N-type transistor N3 is connected to the first terminal of the fifth N-type transistor N5, and the second terminal of the fifth N-type transistor N5 is connected to the second power supply terminal VSS. The first terminal of the fourth N-type transistor N4 is connected to the second terminal of the second N-type transistor N2, the second terminal of the fourth N-type transistor N4 is connected to the first terminal of the sixth N-type transistor N6, and the second terminal of the sixth N-type transistor N6 is connected to the second power supply terminal VSS.
[0096] That is, the current path between the first power supply terminal VCC and the second power supply terminal VSS includes, in sequence, the first P-type transistor P1, the first N-type transistor N1, the third N-type transistor N3 and the fifth N-type transistor N5; or the current path between the first power supply terminal VCC and the second power supply terminal VSS includes, in sequence, the second P-type transistor P2, the second N-type transistor N2, the fourth N-type transistor N4 and the sixth N-type transistor N6.
[0097] In some embodiments, the first terminal of the fifth N-type transistor N5 is connected to the second terminal of the first N-type transistor N1, the second terminal of the fifth N-type transistor N5 is connected to the first terminal of the third N-type transistor N3, the first terminal of the third N-type transistor N3 is connected to the second power supply terminal VSS, the first terminal of the fourth N-type transistor N4 is connected to the second terminal of the second N-type transistor N2, the second terminal of the fourth N-type transistor N4 is connected to the first terminal of the sixth N-type transistor N6, and the second terminal of the sixth N-type transistor N6 is connected to the second power supply terminal VSS.
[0098] In some embodiments, the first terminal of the third N-type transistor N3 is connected to the second terminal of the first N-type transistor N1, the second terminal of the third N-type transistor N3 is connected to the first terminal of the fifth N-type transistor N5, and the second terminal of the fifth N-type transistor N5 is connected to the second power supply terminal. The first terminal of the sixth N-type transistor N6 is connected to the second terminal of the second N-type transistor N2, the second terminal of the sixth N-type transistor N6 is connected to the first terminal of the fourth N-type transistor N4, and the second terminal of the fourth N-type transistor N4 is connected to the second power supply terminal VSS.
[0099] In this configuration, the isolation signal S2 and the charging signal S1 are the same signal. For example, when the isolation signal S2 is active low, the charging signal S1 is active low. Both the control terminals of the first N-type transistor N1 and the second N-type transistor N2 receive the isolation signal S2, and when the isolation signal S2 is low, both the first N-type transistor N1 and the second N-type transistor N2 are turned off. This disconnects the current path between the first power supply terminal VCC and the second power supply terminal VSS, achieving isolation between the first power supply terminal VCC and the second power supply terminal VSS, isolation between the first terminal of the fifth N-type transistor N5 and the first power supply terminal VCC, and isolation between the first terminal of the sixth N-type transistor N6 and the first power supply terminal VCC.
[0100] In some embodiments, the first charging unit 410 includes a third P-type transistor P3, and the second charging unit 420 includes a fourth P-type transistor P4. The first terminal of the third P-type transistor P3 is directly coupled to the first power supply terminal VCC, and the second terminal of the third P-type transistor P3 is directly coupled to the first output terminal SB. The control terminal of the third P-type transistor P3 receives the charging signal S1. The first terminal of the fourth P-type transistor P4 is directly coupled to the first power supply terminal VCC, and the second terminal of the fourth P-type transistor P4 is directly coupled to the second output terminal RB. The control terminal of the fourth P-type transistor P4 receives the charging signal S1.
[0101] The control terminals of the first N-type transistor N1 and the second N-type transistor N2 both receive the isolation signal S2, which is active low. The control terminals of the third P-type transistor P3 and the fourth P-type transistor P4 also receive the charging signal S1, which is active low. Both P3 and P4 are turned on, indirectly coupling the first output terminal SB to the first power supply terminal VCC and the second output terminal RB to the first power supply terminal VCC. The first power supply terminal VCC charges the first output terminal SB and the second output terminal RB. Furthermore, the isolation module isolates the first output terminal SB from the second power supply terminal VSS and the second output terminal RB from the second power supply terminal VSS, preventing the second power supply terminal VSS from pulling the voltage of the first output terminal SB and the second output terminal RB. Additionally, the isolation module isolates the first terminal of the fifth N-type transistor N5 from the first power supply terminal VCC and the first terminal of the sixth N-type transistor N6 from the first power supply terminal VCC. This reduces the number of charging nodes in the pre-charging stage, lowering power loss and increasing the charging rate. It should be noted that the isolation signal S2 and the charging signal S1 can be the same signal.
[0102] When the isolation signal S2 is active, the amplification signal is inactive; when the isolation signal is inactive, the amplification signal is active. For example, when the isolation signal S2 is active low, the amplification signal S3 is active high. With both the isolation signal S2 and the charging signal S1 active low, the first output terminal SB and the second output terminal RB are charged. After the pre-charging phase is complete, the amplification signal S3 is set to high to amplify the input data. At this time, the charging signal S1 and the isolation signal S2 are inactive high, so that the first power supply terminal VCC no longer charges the first output terminal SB and the second output terminal RB. It should be noted that the amplification signal S3, the isolation signal S2, and the charging signal S1 can be the same signal.
[0103] The input data includes a first input data D and a second input data DB, and the first input data D and the second input data DB are opposite signals. That is, when the first input data D is "0", the second input data DB is "1" and when the first input data D is "1", the second input data DB is "0".
[0104] When the control terminals of the first N-type transistor N1 and the second N-type transistor N2 receive the amplified signal S3, both the first N-type transistor N1 and the second N-type transistor N2 are turned on. The fifth N-type transistor N5 reads the first input data D, and the sixth N-type transistor N6 reads the second input data DB.
[0105] When the first input data D is "1" and the second input data DB is "0", the fifth N-type transistor N5 is turned on, and the sixth N-type transistor N6 is turned off. The first output terminal SB discharges through the first N-type transistor N1, the fifth N-type transistor N5, and the third N-type transistor N3, while the voltage of the second output terminal RB remains unchanged, causing the voltage of the first output terminal SB to drop to VSS. The voltage difference between the first output terminal SB and the second output terminal RB is then amplified by the sensing module, causing the first output terminal SB to output the second input data "0" and the second output terminal RB to output the first input data "1".
[0106] Since the first terminal of the fifth N-type transistor N5 and the second terminal of the sixth N-type transistor N6 are not connected to each other, when the first output terminal SB discharges through the first N-type transistor N1, the fifth N-type transistor N5, and the third N-type transistor N3, the second output terminal RB does not form a discharge path. The voltage of the second output terminal RB remains unchanged and is not affected by the discharge of the first output terminal SB. The voltage difference between the first output terminal SB and the second output terminal RB remains unchanged, thus improving the robustness of the amplifier circuit.
[0107] Furthermore, the first and second terminals of the first N-type transistor N5, and the first and second terminals of the sixth N-type transistor N6, are both kept at a low level, requiring only the first output terminal SB or the second output terminal RB to discharge, thus reducing the internal discharge time. Therefore, the output signal time at the first output terminal SB and the second output terminal RB is shorter, resulting in a shorter data delay time. Due to lower power loss and shorter delay time, the power delay product is also smaller.
[0108] Continue to refer to Figure 2 In some embodiments, the amplification circuit further includes a noise reduction module 20, which is used to respond to input data and prevent the first output terminal SB and the second output terminal RB from outputting erroneous signals when the input data changes during the time that the amplified signal S3 is maintained in an effective state.
[0109] In some embodiments, the noise reduction module 20 includes a first noise reduction unit 210 and a second noise reduction unit 220. A first end of the first noise reduction unit is directly coupled to a first end of the first sampling unit 110, and a second end of the first noise reduction unit is directly coupled to a second end of the first sampling unit 110. The first noise reduction unit 210 is used to respond to second input data DB. A first end of the second noise reduction unit is directly coupled to a first end of the second sampling unit 120, and a second end of the second noise reduction unit is directly coupled to a second end of the second sampling unit 120. The second noise reduction unit 220 is used to respond to first input data D.
[0110] When the first output terminal SB discharges through the first sampling unit 110 and the second output terminal RB remains unchanged, if the first input data D and the second input data DB change, the first output terminal SB cannot continue to discharge through the first sampling unit 110, but can continue to discharge through the first noise reduction unit 210, thereby increasing the voltage difference between the first output terminal SB and the second output terminal RB. Furthermore, the driving capability of the first noise reduction unit 210 is weaker than that of the first sampling unit 110, and the driving capability of the second noise reduction unit 220 is weaker than that of the second sampling unit 120. Therefore, when there is no noise in the input data, it will not affect the voltage at the first terminal of the first sampling unit 110 or the first terminal of the second sampling unit 120.
[0111] With this configuration, when there is noise in the data and a jump occurs, the first noise reduction unit 210 and the second noise reduction unit 220 can eliminate the influence of noise on the output results of the first output terminal SB and the second output terminal RB, but without affecting the normal operation of the first sampling unit 110 and the second sampling unit 120, thereby improving the robustness of the amplifier circuit.
[0112] Continue to refer to Figure 2In some embodiments, the first noise reduction unit 210 includes a seventh N-type transistor N7, and the second noise reduction unit 220 includes an eighth N-type transistor N8. The first terminal of the seventh N-type transistor N7 is directly coupled to the first terminal of the fifth N-type transistor N5, and the second terminal of the seventh N-type transistor N7 is directly coupled to the second terminal of the fifth N-type transistor N5. The control terminal of the seventh N-type transistor N7 receives the second input data DB. The first terminal of the eighth N-type transistor N8 is directly coupled to the first terminal of the sixth N-type transistor N6, and the second terminal of the eighth N-type transistor N8 is directly coupled to the second terminal of the sixth N-type transistor N6. The control terminal of the eighth N-type transistor N8 receives the second input data DB.
[0113] like Figure 4 As shown, when the seventh N-type transistor N7 and the eighth N-type transistor N8 are not set, from time t0 to time t1, the charging signal S1 and the isolation signal S2 remain effective, and the first power supply terminal VCC charges the first output terminal SB and the second output terminal RB to the initial voltage.
[0114] From time t1 to time t3, the amplified signal remains active, and the first N-type transistor N1 and the second N-type transistor N2 are turned on. Specifically, from time t1 to time t2, the first input data D is "1", the second input data DB is "0", and the first output terminal SB discharges through the first N-type transistor N1, the fifth N-type transistor N5, and the third N-type transistor N3, while the second output terminal RB does not discharge. This results in the voltage at the first output terminal SB being lower than the voltage at the second output terminal RB. After amplification by the sensing module, the first output terminal SB is pulled down to a low level, while the second output terminal RB remains at a high level.
[0115] From time t2 to time t3, the first input data D jumps from "1" to "0", and the second input data DB jumps from "0" to "1". The second output terminal RB discharges through the second N-type transistor N2, the sixth N-type transistor N6, and the fourth N-type transistor N4, and the voltage of the second output terminal RB gradually decreases. When the voltage of the second output terminal RB is less than the voltage of the first output terminal SB, it is amplified by the sensing module, and the second output terminal RB is pulled down to a low level. The first output terminal SB remains at a high level and is then latched by the latching module. At its output terminal Q2, the data "0" is output, which is different from the data before the jump. The amplifier circuit outputs incorrect data.
[0116] like Figure 5As shown, with the seventh N-type transistor N7 and the eighth N-type transistor N8 present, from time t2 to time t3, the first input data D jumps from "1" to "0", and the second input data DB jumps from "0" to "1". The first output terminal SB can still discharge through the first N-type transistor N1, the seventh N-type transistor N7, and the third N-type transistor N3 to maintain the voltage of the first output terminal SB being lower than the voltage of the second output terminal RB. After amplification by the sensing module, the first output terminal SB is pulled down to a low level, while the second output terminal RB remains at a high level. After being latched by the latching module, the data "1" is output at its output terminal Q2, which is the same as the data before the jump, and the amplifier circuit outputs the correct data.
[0117] By using the seventh N-type transistor N7 and the eighth N-type transistor N8, errors in the output signals of the first output terminal SB and the second output terminal RB can be avoided if the input data changes while the amplified signal S3 remains in an active state. The conduction capability of the seventh N-type transistor N7 is weaker than that of the fifth N-type transistor N5, and the conduction capability of the eighth N-type transistor N8 is weaker than that of the sixth N-type transistor N6. The seventh and eighth N-type transistors N7 and N8 do not affect the normal operation of the fifth and sixth N-type transistors N5 and N6. Furthermore, the seventh and eighth N-type transistors N7 and N8 are turned on or off under the control of the input data, and will not be continuously turned on, thus improving the robustness of the amplifier circuit.
[0118] Continue to refer to Figure 2 In some embodiments, the amplification circuit further includes a latch module 50, with a first terminal of the latch module 50 coupled to a first output terminal SB and a second terminal of the latch module 50 coupled to a second output terminal RB. The latch module 50 is used to output amplified input data.
[0119] In some embodiments, the latch module 50 includes a first NAND gate G1 and a second NAND gate G2. The first terminal of the first NAND gate G1 is connected to the first output terminal SB, the second terminal of the first NAND gate G1 is connected to the third terminal of the second NAND gate G2, the first terminal of the second NAND gate G2 is connected to the third terminal of the first NAND gate G1, the second terminal of the second NAND gate G2 is connected to the second output terminal RB, and the third terminals Q2 of the first NAND gate G1 and QB2 of the second NAND gate G2 are used to output amplified input data.
[0120] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0121] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. An amplification circuit, characterized by, include: The isolation module isolates the first power supply terminal and the second power supply terminal based on the isolation signal. The sampling module reads the input data; The charging module couples the first output terminal and the second output terminal to the first power supply terminal based on the charging signal, and charges the first output terminal and the second output terminal to the initial voltage. The sensing module amplifies the input data based on the amplified signal, the first output terminal having the initial voltage, the second output terminal having the initial voltage, and the second power supply terminal; The input data includes: First input data and second input data, wherein the first input data and the second input data are opposite signals; The isolation module includes: The first isolation unit has a first end coupled to the first output terminal and a second end coupled to the second power supply terminal, and is used to isolate the first output terminal and the second power supply terminal based on the isolation signal; The second isolation unit has a first end coupled to the second output terminal and a second end coupled to the second power supply terminal, and is used to isolate the second output terminal from the second power supply terminal based on the isolation signal; The sensing module includes: The first P-type transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the first output terminal, and a control terminal coupled to the second output terminal. The second P-type transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the second output terminal, and a control terminal coupled to the first output terminal; The third N-type transistor has a first terminal coupled to the second terminal of the first isolation unit, a second terminal coupled to the second power supply terminal, and a control terminal coupled to the second output terminal. The fourth N-type transistor has a first terminal coupled to the second terminal of the second isolation unit, a second terminal coupled to the second power supply terminal, and a control terminal coupled to the first output terminal.
2. The amplification circuit according to claim 1, characterized by The isolation module includes: The first isolation unit includes a first N-type transistor, a first terminal coupled to the first output terminal, a second terminal coupled to the second power supply terminal, and has a control terminal coupled to the isolation signal; The second isolation unit includes a second N-type transistor, with a first end coupled to the second output terminal, a second end coupled to the second power supply terminal, and a control terminal coupled to the isolation signal.
3. The amplification circuit of claim 1, wherein The sampling module includes: The first sampling unit includes a fifth N-type transistor, used to read the first input data based on the amplified signal; The second sampling unit includes a sixth N-type transistor for reading the second input data based on the amplified signal.
4. The amplification circuit of claim 3, wherein The fifth N-type transistor includes: The first terminal is coupled to the second terminal of the first isolation unit, the second terminal is coupled to the first terminal of the third N-type transistor, and has a control terminal coupled to the first input data; or The first terminal is coupled to the second terminal of the third N-type transistor, the second terminal is coupled to the second power supply terminal, and has a control terminal coupled to the first input data.
5. The amplifier circuit according to claim 3, characterized in that, The sixth N-type transistor includes: The first terminal is coupled to the second terminal of the second isolation unit, the second terminal is coupled to the first terminal of the fourth N-type transistor, and has a control terminal coupled to the second input data; or The first terminal is coupled to the second terminal of the fourth N-type transistor, the second terminal is coupled to the second power supply terminal, and has a control terminal coupled to the second input data.
6. The amplification circuit of claim 3, wherein, Also includes: A noise reduction module is used to respond to the input data and prevent the first and second output terminals from outputting erroneous signals due to changes in the input data while the amplified signal remains in an effective state; wherein, the noise reduction module includes: The first noise reduction unit has a first end coupled to the first end of the first sampling unit and a second end coupled to the second end of the first sampling unit, and is used to respond to the second input data; The second noise reduction unit has a first end coupled to the first end of the second sampling unit and a second end coupled to the second end of the second sampling unit, and is used to respond to the first input data.
7. The amplifier circuit according to claim 6, characterized in that, The noise reduction module includes: The first noise reduction unit includes a seventh N-type transistor, with a first terminal coupled to the first terminal of the fifth N-type transistor, a second terminal coupled to the second terminal of the fifth N-type transistor, and a control terminal coupled to the second input data; The second noise reduction unit includes an eighth N-type transistor, with a first terminal coupled to the first terminal of the sixth N-type transistor, a second terminal coupled to the second terminal of the sixth N-type transistor, and a control terminal coupled to the first input data.
8. The amplification circuit of claim 7, wherein, include: The seventh N-type transistor has a weaker conduction capability than the fifth N-type transistor; The conduction capability of the eighth N-type transistor is weaker than that of the sixth N-type transistor.
9. The amplification circuit of claim 1, wherein, The charging module includes: A first charging unit has a first end coupled to the first power supply terminal and a second end coupled to the first output terminal, used to couple the first output terminal to the first power supply terminal based on the charging signal. The second charging unit has a first end coupled to the first power supply end and a second end coupled to the second output end, and is used to couple the second output end to the first power supply end based on the charging signal.
10. The amplification circuit of claim 9, wherein, The charging module includes: The first charging unit includes a third P-type transistor, with a first terminal coupled to the first power supply terminal, a second terminal coupled to the first output terminal, and a control terminal coupled to the charging signal; The second charging unit includes a fourth P-type transistor, with a first end coupled to the first power supply terminal, a second end coupled to the second output terminal, and a control terminal coupled to the charging signal.
11. The amplification circuit of claim 1, wherein, include: The isolation signal and the charging signal are the same signal; When the isolation signal is active, the amplified signal is inactive; when the isolation signal is inactive, the amplified signal is active. The first output terminal outputs the amplified second input data; The second output terminal outputs the amplified first input data.
12. The amplifier circuit according to claim 1, characterized in that, The amplifier circuit also includes: The latch module has a first end coupled to the first output end and a second end coupled to the second output end, and is used to output amplified input data.