Display device and its driving method

Abstract

The present application relates to a display device and a driving method thereof. Embodiments of the present disclosure relate to a display device, and more particularly to a display device including: a display panel including pixels, the pixels including light-emitting devices that emit light by a driving current flowing from a first power supply voltage to a second power supply voltage in response to a data signal; a data driver circuit for providing a data signal to the pixels through data lines; a gate driver circuit for providing a gate signal to the pixels through gate lines and outputting a light-emitting control signal for controlling one of a reset voltage and a first power supply voltage to be provided to the light-emitting devices; and a timing controller for controlling the data driver circuit and the gate driver circuit, wherein the pixels receive the reset voltage at least once after sending one data signal and before sending the next data signal.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. As display devices, various types of display devices are used, such as liquid crystal display devices (LCDs) and electroluminescent display devices (ELDs).

[0003] An electroluminescent display device (ELD) may include a quantum dot light-emitting display device including quantum dots, an inorganic light-emitting display device, and an organic light-emitting display device.

[0004] Among the above display devices, an electroluminescent display device (ELD) has advantages in that response speed, viewing angle, color reproducibility, etc. can be achieved very excellently, and can also be realized with a relatively thin thickness.

[0005] The above display device can display a still image. When a still image is displayed on the display device, power consumption can be reduced by driving at a low frequency.

[0006] When the display device is driven at a low frequency, as long as the data signal written to the pixel is maintained, the time of a frame increases. In addition, when a still image is displayed on the display device, the same data signal can be written to the pixel during multiple frames. Summary of the Invention

[0007] Even when the same data signal is written to the pixel during multiple frames, the brightness may decrease between one frame and the next frame. When driven at a high frequency, the user does not recognize the brightness decrease, but when driven at a low frequency, the user may recognize the brightness decrease. Therefore, the inventors of the present specification have invented a display device and a driving method thereof that prevent the user from recognizing the brightness decrease when driven at a low frequency.

[0008] The problems to be solved according to the embodiments of the present specification are not limited to the above problems, and other problems not mentioned will be clearly understood by those skilled in the art according to the following description.

[0009] Exemplary embodiments of the present disclosure provide a display device, the display device including: a display panel including pixels, the pixels including light-emitting devices, wherein the pixels receive data signals corresponding to gate signals, the light-emitting devices emit light through a driving current flowing from a first power supply voltage to a second power supply voltage in response to the data signals, and the pixels receive a reset voltage at least once after receiving one data signal and before receiving the next data signal; a data driver circuit configured to provide data signals to the pixels through data lines; a gate driver circuit configured to provide gate signals to the pixels through gate lines and output a light-emitting control signal for controlling one of the reset voltage and the first power supply voltage provided to the light-emitting devices; and a timing controller configured to control the data driver circuit and the gate driver circuit.

[0010] When a first time period elapses after the reset voltage is sent to the light-emitting device, the first power supply voltage may be transmitted to the light-emitting device, and the first time period may be determined by the light-emitting control signal.

[0011] In addition, exemplary embodiments of the present disclosure provide a display device including: a display panel driven in one of a first frequency mode of providing data signals in response to a first frequency and a second frequency mode of providing data signals in response to a second frequency lower than the first frequency; a gate driver circuit configured to provide gate signals and a light-emitting control signal to the display panel; a data driver circuit configured to provide data signals to the display panel; and a timing controller configured to control the data driver circuit and the gate driver circuit, wherein each of the first frequency mode and the second frequency mode includes at least one light-emitting period and at least one non-light-emitting period, and wherein, in the first frequency mode and the second frequency mode, the number of occurrences of the light-emitting period and the non-light-emitting period is the same.

[0012] In addition, exemplary embodiments of the present disclosure provide a driving method of a display device including pixels including light-emitting devices, the pixels receiving data signals corresponding to gate signals, the light-emitting devices emitting light through a driving current flowing from a first power supply voltage to a second power supply voltage in response to the data signals, the driving method including: providing a data signal and a first power supply voltage to the pixels and providing a driving current generated in response to the data signal to the light-emitting devices in the pixels; while the pixels hold the data signal, cutting off the first power supply voltage provided to the pixels and providing a reset voltage to the pixels; providing the first power supply voltage to the pixels; and providing a data signal to the pixels.

[0013] According to an exemplary embodiment of the present specification, by selectively selecting one of a high frequency and a low frequency to be driven, there is an effect of reducing power consumption in a display device.

[0014] In addition, according to an exemplary embodiment of the present specification, when driving the display device at a low frequency, it is possible to minimize brightness variations occurring in the display device, thereby preventing deterioration of image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a plan view of a display device illustrating an exemplary embodiment of the present specification.

[0017] Figure 2A and Figure 2B is a timing diagram illustrating brightness variations in a display device according to an exemplary embodiment of the present specification.

[0018] Figure 3 illustrates Figure 1 a conceptual diagram of a pixel shown.

[0019] Figure 4 illustrates by Figure 3 a timing diagram of changing brightness by a reset voltage in the pixel shown.

[0020] Figure 5A and Figure 5B is a timing diagram illustrating operations of a display device according to an exemplary embodiment of the present specification.

[0021] Figure 6A is a timing diagram showing that the rate of increase in the voltage of an anode electrode during a refresh period is greater than the rate of increase in the voltage of the anode electrode during a reset period.

[0022] Figure 6B is a timing diagram showing that the rate of increase in the voltage of an anode electrode during a refresh period is lower than the rate of increase in the voltage of the anode electrode during a reset period.

[0023] Figure 7A is a timing diagram showing adjustment of a starting point of a refresh period.

[0024] Figure 7B is a timing diagram showing adjustment of a starting point of a reset period.

[0025] Figure 7C is a timing diagram showing adjustment of an end point of a refresh period.

[0026] Figure 7D is a timing diagram showing adjustment of an end point of a reset period.

[0027] Figure 8 is an illustration Figure 1 The circuit diagram of the embodiment of the pixel shown.

[0028] Figure 9 is an illustration Figure 8 The timing diagram of the operation during the refresh period of the pixel shown.

[0029] Figure 10 is an illustration Figure 8 The timing diagram of the operation during the reset period of the pixel shown.

[0030] Figure 11 is an illustration Figure 1 The structural diagram of the timing controller shown.

[0031] Figure 12 is an illustration of the flowchart of the method for driving a display device according to an exemplary embodiment of the present specification. Detailed implementation mode

[0032] In the following description of the examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which, even if the same or similar components are shown in different drawings, the same reference numerals and symbols can be used to represent the same or similar components. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure quite unclear, the detailed description will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed by" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0033] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the essence, order, sequence, quantity, etc. of the element, but only to distinguish the corresponding element from other elements.

[0034] When referring to the first element and the second element being "connected or coupled", "contacting or overlapping", etc., it should be interpreted that not only can the first element be "directly connected or coupled" or "directly contacting or overlapping" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled", "contacting or overlapping", etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacting or overlapping", etc. with each other.

[0035] When time-related terms such as "after", "subsequently", "then", "before", etc. are used to describe the process or operation of an element or configuration, or the flow or steps in an operation method, a processing method, or a manufacturing method, unless used together with the terms "directly" or "immediately", these terms can be used to describe a non-continuous or non-sequential process or operation.

[0036] In addition, when referring to any dimension, relative size, etc., even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal influences or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "can".

[0037] Figure 1 is a plan view illustrating a display device 100 according to an exemplary embodiment of the present specification.

[0038] Referring to Figure 1 , the display device 100 may include a display panel 110, a data driver circuit 120, a gate driver circuit 130, and a timing controller 140.

[0039] The display panel 110 may include a plurality of pixels 101. The plurality of pixels 101 may be arranged in a matrix form within the display panel 110, but the present invention is not limited thereto. Each of the plurality of pixels 101 may emit light of various colors (e.g., red, green, or blue). However, the color of the light emitted from each pixel is not limited thereto. In addition, for example, the display panel 110 may have a rectangular shape.

[0040] Multiple gate lines GL1 to GLn and multiple data lines DL1 to DLm may be provided on the display panel 110. Multiple pixels 101 may be connected to the gate lines GL1 to GLn and the data lines DL1 to DLm. Each pixel 101 may receive a data signal transmitted through a corresponding data line among the data lines DL1 to DLm in response to a gate signal transmitted through a corresponding gate line among the gate lines GL1 to GLn. In addition, multiple emission control lines EML1 to EMLn may be provided on the display panel 110. The emission control lines EML1 to EMLn send an emission control signal to the multiple pixels 101, such that the time when the multiple pixels 101 emit light can be controlled.

[0041] The data driver circuit 120 may be electrically connected to the multiple data lines DL1 to DLm to transmit a data signal to the pixels 101 through the data lines DL1 to DLm. Here, although one data driver circuit 120 is shown, it is not limited thereto. In addition, the data driver circuit 120 may supply a reset voltage to the multiple data lines DL1 to DLm. However, the present invention is not limited thereto, and the reset voltage may be transmitted through a separate line different from the multiple data lines DL1 to DLm. The data driver circuit 120 may be an integrated circuit.

[0042] The gate driver circuit 130 may be electrically connected to the multiple gate lines GL1 to GLn and may supply a gate signal to the multiple pixels 101 through the multiple gate lines GL1 to GLn.

[0043] The gate driver circuit 130 may be electrically connected to the multiple emission control lines EML1 to EMLn and may supply an emission control signal to the multiple pixels 101 through the multiple emission control lines EML1 to EMLn.

[0044] Here, the gate driver circuit 130 is shown as being provided on one side of the display panel 110, but it is not limited thereto and may be provided on both sides of the display panel 110. In addition, the display device 100 may not include a separate gate driver circuit separated from the display panel 110, but may include a gate driver circuit 130 provided in the display panel 110 in a gate generation circuit type (referred to as an in-panel gate (GIP) type). When the gate driver circuit 130 is included in the display device 100 in the gate generation circuit type (GIP type), the gate driver circuit 130 may be formed on the display panel 110 while the multiple pixels 101 are formed on the display panel 110.

[0045] The timing controller 140 may control the data driver circuit 120 and the gate driver circuit 130. The timing controller 140 may provide an image signal RGB and a data control signal DCS to the data driver circuit 120, and may provide a gate control signal GCS to the gate driver circuit 130.

[0046] In addition, the display device 100 may operate in a first frequency mode in which it emits light in response to a first frequency and a second frequency mode in which it emits light in response to a second frequency lower than the first frequency. The image displayed on the display device 100 has a plurality of frames. If the image is driven in the second frequency mode, the time for holding one frame becomes longer. When the time for holding one frame increases, the number of signals generated and processed by the data driver circuit 120, the gate driver circuit 130, and the timing controller 140 may be reduced. Accordingly, the power consumption in the display device 100 may be reduced. Therefore, when the display device 100 operates in the second frequency mode, the power consumption of the display device 100 may be reduced.

[0047] In addition, when the display device 100 operates in the second frequency mode, the pixel 101 may receive a reset voltage.

[0048] In addition, the timing controller 140 may select to operate the display device 100 in the first frequency mode or the second frequency mode, and may control the data driver circuit 120 and the gate driver circuit 130 according to the selected first frequency mode or second frequency mode.

[0049] Figure 2A and Figure 2B are timing diagrams illustrating the brightness change in the display device 100 according to an exemplary embodiment of the present specification. Figure 2A illustrates the case of operating in the first frequency mode, and Figure 2B illustrates the case of operating in the second frequency mode.

[0050] Referring to Figure 2A and Figure 2B , the display device 100 may operate in a first frequency mode in which it operates in response to a first frequency and a second frequency mode in which it operates in response to a second frequency lower than the first frequency. For example, the first frequency may be 60 Hz, and the second frequency may be 1 Hz. However, the values of the first frequency and the second frequency are not limited thereto.

[0051] As Figure 2A shown, when the display device 100 is driven at 60 Hz, the data signal may be written to the pixel 101 60 times in one second (1 s). On the other hand, as Figure 2BAs shown, when the display device 100 is driven at 1 Hz, a data signal can be written to the pixel 101 once per second (1 s). The period during which a new data signal is written to the pixel 101 and an image corresponding to the written data signal is displayed can be referred to as a "refresh period".

[0052] The pixel 101 includes a plurality of transistors. When a data signal is written to the pixel 101, a kickback phenomenon may occur due to the operation of the transistors included in the pixel 101. Due to the kickback phenomenon that occurs when a data signal is written to the pixel 101, the brightness of the light emitted from the pixel 101 may decrease.

[0053] Therefore, as Figure 2A shown, when the display device 100 is driven at 60 Hz, the image displayed on the display device 100 has a brightness decrease 60 times per second (1 s). As Figure 2B shown, when the display device 100 is driven at 1 Hz, the image displayed on the display device 100 can have a brightness decrease once every 1 second (1 s).

[0054] If the brightness decrease occurs 60 times within 1 second (1 s), the user may not be able to recognize the brightness decrease in the image displayed on the display device 100. However, when the brightness decrease occurs once per second (1 s) in the displayed image, the user can recognize the brightness decrease in the image displayed on the display device 100.

[0055] Therefore, when the display device 100 is driven in a second frequency mode that operates in response to a second frequency in order to reduce power consumption, the user can recognize that the image displayed on the display device 100 is flickering. When a still image is displayed on the display device 100, the user can more strongly feel the flickering of the image displayed on the display device 100.

[0056] Figure 3 is an illustration Figure 1 of the conceptual diagram of the pixel 101 shown. Figure 4 is an illustration of Figure 3 the timing diagram of changing the brightness by the reset voltage Vreset in the pixel 101 shown.

[0057] Referring to Figure 3 and Figure 4 , the pixel 101 may include a light-emitting device ED that emits light by receiving a driving current Id, and a pixel circuit 101p that supplies the driving current Id to the light-emitting device ED.

[0058] The light-emitting device ED may include an anode electrode 101a, a cathode electrode 101c, and a light-emitting layer 101b disposed between the anode electrode 101a and the cathode electrode 101c. For example, the light-emitting device ED may be a light-emitting diode. In particular, the light-emitting device ED may be an organic light-emitting diode (OLED).

[0059] The pixel circuit 101p may receive a first power supply voltage EVDD from a first node N1'. The pixel circuit 101p may receive a data signal Vdata or a reset voltage Vreset from a data line DL. In addition, through the operation of the pixel circuit 101p, a second node N2' is electrically connected to a point (the first node N1') where the first power supply voltage EVDD is applied through the pixel circuit 101p, or a reset voltage Vreset may be applied to the second node N2' through the pixel circuit 101p. Since the second node N2' is electrically connected to the anode electrode 101a of the light-emitting device ED, the anode electrode 101a of the light-emitting device ED may be electrically connected to the first power supply voltage EVDD or be applied with the reset voltage Vreset. The voltage level of the first power supply voltage EVDD may be higher than the voltage level of the second power supply voltage EVSS. In addition, the voltage level of the reset voltage Vreset may be a voltage level lower than the threshold voltage of the light-emitting device ED.

[0060] Through the operation of the pixel circuit 101p, the first power supply voltage EVDD is applied to the anode electrode 101a of the light-emitting device ED, and the second power supply voltage EVSS is applied to the cathode electrode 101c. Then, the voltage level of the anode electrode 101a becomes higher than the voltage level of the cathode electrode 101c. Therefore, a driving current Id may flow from the anode electrode 101a to the cathode electrode 101c. Since the light-emitting layer 101b emits light when the driving current Id flows, the light-emitting layer 101b can emit light in response to the data signal Vdata.

[0061] On the other hand, when the reset voltage Vreset is applied to the anode electrode 101a and the first power supply voltage EVDD is not sent, the voltage level of the anode electrode 101a can be reduced to the reset voltage Vreset. Therefore, even if the data signal Vdata is supplied to the pixel circuit 101p, the driving current Id may not flow from the anode electrode 101a to the cathode electrode 101c. Thus, when the reset voltage Vreset is applied to the anode electrode 101a, the light-emitting device ED may not emit light. Here, the reset voltage Vreset is shown as being sent through the data line DL, but it is not limited thereto. In addition, when the first power supply voltage EVDD is supplied to the anode electrode 101a again, the voltage level of the anode electrode 101a increases, causing the driving current to flow through the light-emitting device ED, and the light-emitting device ED emits light. When the first power supply voltage EVDD is supplied to the anode electrode 101a again, the reset voltage Vreset may not be sent to the anode electrode 101a.

[0062] Therefore, since the light-emitting device ED does not emit light when the reset voltage Vreset is applied, the brightness in the image displayed on the display device 100 can be temporarily reduced. In addition, when the reset voltage Vreset is periodically applied to the anode electrode 101a, as Figure 4 shown, the brightness is repeatedly reduced, resulting in a brightness change such as driving at 60 Hz.

[0063] For the above reasons, even if the display device 100 is driven in the second frequency mode, the user may not be able to recognize the brightness deterioration of the image displayed on the display device 100. In addition, in a state where the voltage of the data signal Vdata is constant, the voltage level of the anode electrode 101a can be reduced by the transmission of the reset voltage Vreset and can be increased again by the voltage level of the data signal Vdata. This period can be referred to as the "reset period".

[0064] Figure 5A and Figure 5B are timing diagrams illustrating the operation of the display device 100 according to an exemplary embodiment of the present specification.

[0065] Referring to Figure 5A , when the display device 100 is driven in the first frequency mode, since the data signal is periodically written to the pixel 101, the refresh period Trefresh of writing the data signal to the pixel 101 can be periodically repeated. For example, when the display device 100 is driven in the first frequency mode with a driving frequency of 60 Hz, the refresh period Trefresh can be repeated 60 times per second.

[0066] On the other hand, referring to Figure 5B, when the display device 100 is driven in the second frequency mode, since the data signal Vdata can be written once within a certain period of time, the refresh period Trefresh can occur once within a certain period of time, and the reset period Treset during which the reset voltage Vreset is applied to the anode electrode 101a can occur repeatedly. Therefore, it is possible to prevent a decrease in brightness from being recognized in the second frequency mode. For example, when the display device 100 is driven in the second frequency mode at 1 Hz, after the refresh period Trefresh during which the data signal is written into the pixel 101 appears once within 1 second (1 s), the reset period Treset can occur continuously 59 times.

[0067] The rate (speed) at which the voltage level of the anode electrode 101a increases during the refresh period Trefresh and the rate (speed) at which the voltage level of the anode electrode 101a increases during the reset period Treset can be different. Due to the difference in the rate of increase of the voltage level of the anode electrode 101a, the time when light is emitted from the light-emitting device ED may be different. Therefore, due to the difference in the rate of increase of the voltage level of the anode electrode 101a, the brightness of the display device 100 may be different. More specifically, due to the difference in the rate of increase of the voltage level of the anode electrode 101a, the light emission time (light emission amount) of the light-emitting device ED during the refresh period Trefresh and the light emission time (light emission amount) of the light-emitting device ED during the reset period Treset can be different from each other. Therefore, the brightness of the display device 100 can be different during the refresh period (Trefresh) and the reset period (Treset).

[0068] Figure 6A is a timing diagram showing that the rate (speed) at which the voltage of the anode electrode 101a increases during the refresh period is greater than the rate (speed) at which the voltage of the anode electrode 101a increases during the reset period. Figure 6B is a timing diagram showing that the rate at which the voltage of the anode electrode 101a increases during the refresh period is lower than the rate at which the voltage of the anode electrode 101a increases during the reset period.

[0069] As Figure 6AAs shown, when the rate of increase of the voltage Va at the anode electrode 101a of the light-emitting device ED during the refresh period Trefresh is faster than the rate of increase of the voltage Va at the anode electrode 101a during the reset period Treset, the timing of light emission from the light-emitting device ED during the refresh period Trefresh can be earlier than the timing of light emission from the light-emitting device ED during the reset period Treset. Therefore, the amount of light emitted by the display device 100 during the refresh period Trefresh is greater than the amount of light emitted by the display device 100 during the reset period Treset. Therefore, the brightness of the display device 100 during the refresh period Trefresh can be higher than the brightness of the display device during the reset period Treset.

[0070] In addition, as Figure 6B shown, when the rate of increase of the voltage Va at the anode electrode 101a of the light-emitting device ED during the refresh period Trefresh is slower than the rate of increase of the voltage Va at the anode electrode 101a during the reset period Treset, the timing of light emission from the light-emitting device ED during the refresh period Trefresh can be later than the timing of light emission from the light-emitting device ED during the reset period Treset. Therefore, the amount of light emitted by the display device 100 during the refresh period Trefresh can be less than the amount of light emitted by the display device 100 during the reset period Treset. Therefore, the brightness of the display device 100 during the refresh period Trefresh can be lower than the brightness of the display device 100 during the reset period Treset.

[0071] Therefore, when the display device 100 operates in the second frequency mode, the amount of light emitted by the light-emitting device ED may be different between the refresh period Trefresh and the reset period Treset. Therefore, a difference may occur between the brightness of the display device 100 during the refresh period Trefresh and the brightness of the display device 100 during the reset period Treset. That is, the brightness of the display device 100 during the refresh period Trefresh becomes higher or lower than the brightness of the display device 100 during the reset period Treset, and the user can recognize that the image displayed on the display device 100 is flickering.

[0072] By controlling the amount of light emitted by the light-emitting device ED during the refresh period Trefresh and the amount of light emitted by the light-emitting device ED during the reset period Treset to be the same, the problem of recognizing a flickering image can be solved. In addition, in order to balance the amount of light emitted by the light-emitting device ED during the refresh period Trefresh and the amount of light emitted by the light-emitting device ED during the reset period Treset, the time point at which the drive current Id flows to the light-emitting device ED can be adjusted.

[0073] Figure 7Ais a timing diagram showing the start point of adjusting the refresh period, Figure 7B is a timing diagram showing the start point of adjusting the reset period, Figure 7C is a timing diagram showing the end point of adjusting the refresh period, and Figure 7D is a timing diagram showing the end point of adjusting the reset period.

[0074] By controlling the time points at which the drive current Id is supplied to the light-emitting device ED, it is possible to adjust the start point and end point of the refresh period Trefresh and the start point and end point of the reset period Treset.

[0075] As Figure 7A shown, by differently controlling the start point at which the voltage level Va of the anode electrode 101a increases during the refresh period Trefresh as in cases i, ii, and iii, it is possible to differently control the timing at which the drive current Id is supplied to the light-emitting device ED.

[0076] Referring to Figure 7A , the time point at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh can be the fastest in case 1 and the slowest in case 3. Based on case ii, when the brightness of the reset period Treset is lower than the brightness of the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh can be controlled to be slower, so that the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh becomes the start point in case iii.

[0077] In addition, based on case ii, when the brightness of the reset period Treset is higher than the brightness of the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh can be controlled to be faster, so that the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh becomes the start point in case i.

[0078] Referring to Figure 7B, the time point at which the voltage level Va of the anode electrode 101a increases during the reset period Treset can be the fastest in case i and the slowest in case iii. Based on case ii, when the luminance during the reset period Treset is lower than the luminance during the refresh period Trefresh, the starting point (starting timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset can be controlled to be faster, such that the starting point (starting timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset becomes the starting point in case i.

[0079] In addition, based on case ii, when the luminance during the reset period Treset is higher than the luminance during the refresh period Trefresh, the starting point (starting timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset can be controlled to be slower, such that the starting point (starting timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset becomes the starting point in case iii.

[0080] In addition, as Figure 7C shown, the time point at which the drive current Id supplied to the light-emitting device ED is cut off during the refresh period Trefresh can be controlled differently as in cases i, ii, and iii, such that the timing of terminating the supply of the drive current Id to the light-emitting device ED can be controlled differently.

[0081] Referring to Figure 7C , the time point at which the drive current Id supplied to the light-emitting device ED is cut off during the refresh period Trefresh can be the fastest in case i and the slowest in case iii. Based on case ii, when the luminance during the reset period Treset is higher than the luminance during the refresh period Trefresh, the blocking point (blocking timing) at which the drive current Id supplied to the light-emitting device ED is cut off during the refresh period Trefresh can be controlled to be slower, such that the blocking point (blocking timing) at which the drive current Id supplied to the light-emitting device ED is cut off during the refresh period Trefresh becomes the blocking point in case iii.

[0082] In addition, as Figure 7D shown, the time point at which the drive current Id supplied to the light-emitting device ED is cut off during the reset period Treset can be controlled differently as in cases i, ii, and iii, such that the timing of terminating the supply of the drive current Id to the light-emitting device ED can be controlled differently.

[0083] Referring to Figure 7D, the time point at which the drive current Id supplied to the light-emitting device ED is cut off during the reset period Treset can be the fastest in case i and the slowest in case iii. Based on case ii, when the luminance during the reset period Treset is lower than the luminance during the refresh period Trefresh, the cut-off point (cut-off timing) at which the drive current Id supplied to the light-emitting device ED is cut off during the reset period Treset can be controlled to be slower, such that the cut-off point (cut-off timing) at which the drive current Id supplied to the light-emitting device ED is cut off during the reset period Treset becomes the cut-off point in case iii.

[0084] Figure 8 is an illustration Figure 1 The circuit diagram of the embodiment of the pixel 101 shown.

[0085] Referring to Figure 8 , the pixel 101 may include a pixel circuit 101p and a light-emitting device ED. The pixel circuit 101p may include first to fourth nodes N1 to N4 as electrical nodes. The plurality of signal lines for driving the pixel circuit 101p may include a data line DL, a first gate line GL1 and a second gate line GL2, and a first emission control line EML1 and a second emission control line EML2.

[0086] The pixel circuit 101p may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a capacitor Cst. The first transistor M1 may supply a drive current to the light-emitting device ED in response to a data signal Vdata. The second transistor M2 may supply the data signal Vdata from the data line DL to the first transistor M1 in response to a first gate signal GATE1. The third transistor M3 may supply a first power supply voltage EVDD to the first transistor M1 in response to a first emission control signal EMS1. The fourth transistor M4 may supply the first power supply voltage EVDD or a reset voltage Vreset to the light-emitting device ED in response to a second emission control signal EMS2. The fifth transistor M5 may diode-connect the first transistor M1 in response to a second gate signal GATE2. The capacitor Cst may hold the data signal Vdata supplied to the first transistor M1. The sixth transistor M6 may transfer an initialization voltage Vini for initializing the capacitor Cst and the anode electrode 101a (corresponding to the node N4) of the light-emitting device ED to the capacitor Cst in response to the second gate signal GATE2.

[0087] The first transistor M1 may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor M1 may provide a driving current from the first node N1 to the second node N2 in response to a data signal Vdata sent to the third node N3.

[0088] The second transistor M2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode connected to the first gate line GL1. The second transistor M2 may provide the data signal Vdata flowing through the data line DL to the third node N3 in response to a first gate signal GATE1 sent to the first gate line GL1.

[0089] The third transistor M3 may have a first electrode connected to the first power supply voltage EVDD, a second electrode connected to the first node N1, and a gate electrode connected to the first emission control line EML1. The first power supply voltage EVDD may be supplied to the first electrode of the third transistor M3 through the first power supply line VL1. The third transistor M3 may provide the first power supply voltage EVDD to the first node N1 in response to a first emission control signal EMS1 sent through the first emission control line EML1. When the third transistor M3 is turned on and supplies the first power supply voltage EVDD to the first node N1, the first transistor M1 receives the first power supply voltage EVDD. Therefore, when the first transistor M1 is turned on, a driving current corresponding to the data signal may flow from the first node N1 to the second node N2.

[0090] The fourth transistor M4 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4, and a gate electrode connected to the second emission control line EML2. The fourth transistor M4 may electrically connect the second node N2 and the light-emitting device ED in response to a second emission control signal EMS2 sent through the second emission control line EML2. When the fourth transistor M4 is turned on and the light-emitting device ED is electrically connected to the second node N2, the driving current flowing from the first node N1 to the second node N2 can be transmitted to the light-emitting device ED. Therefore, the light-emitting device ED can emit light.

[0091] The fifth transistor M5 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the second gate line GL2. The fifth transistor M5 may electrically connect the first node N1 and the third node N3 in response to a second gate signal GATE2 sent to the second gate line GL2. When the first node N1 and the third node N3 are electrically connected, the first transistor M1 may be in a diode-connected state. Therefore, the first transistor M1 can operate like a diode.

[0092] The capacitor Cst may include a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The capacitor Cst may hold the voltage applied to the third node N3.

[0093] The sixth transistor M6 may include a first electrode connected to the initialization voltage line VL2 that transmits the initialization voltage Vini, a second electrode connected to the fourth node N4, and a gate electrode connected to the second gate line GL2. The sixth transistor M6 may be turned on in response to the second gate signal GATE2 to transmit the initialization voltage Vini transmitted through the initialization voltage line VL2 to the fourth node N4. The fourth node N4 may be connected to the second electrode of the capacitor Cst and the anode electrode 101a of the light-emitting device ED. When the sixth transistor M6 is turned on, the second electrode of the capacitor Cst and the anode electrode 101a of the light-emitting device ED may be initialized by the initialization voltage Vini.

[0094] In the light-emitting device ED, the anode electrode 101a may be electrically connected to the fourth node N4, and the cathode electrode 101c may be electrically connected to the second power supply voltage EVSS. The light-emitting device ED may emit light according to the amount of current flowing from the anode electrode 101a to the cathode electrode 101c. When the fifth transistor M5 is turned on and the drive current is provided from the first transistor M1, the light-emitting device ED may emit light.

[0095] Here, as Figure 8 shown, the reset voltage Vreset is supplied to the data line DL, and the reset voltage Vreset supplied to the data line DL may be transmitted to the anode electrode 101a of the light-emitting device ED through the second transistor M2 and the fourth transistor M4. In Figure 8 , the reset voltage Vreset is shown as being transmitted to the anode electrode 101a of the light-emitting device ED through the data line DL, but is not limited thereto. The reset voltage Vreset may be transmitted to the anode electrode 101a of the light-emitting device ED through a separate line different from the data line DL. In addition, the circuit diagram of the pixel is shown in Figure 8 for illustrative purposes only, and the embodiments of the present disclosure are not limited thereto. For example, the pixel in the display device of the present disclosure may have various circuit structures other than Figure 8 the circuit structure shown.

[0096] Figure 9 is an illustration Figure 8 of the operation timing diagram during the refresh period of the pixel shown.

[0097] Refer to Figure 9, the refresh period Trefresh is a period during which light is emitted in response to the data signal Vdata written in the pixel 101 after the data signal Vdata is written in the pixel 101. The refresh period Trefresh may include a first period Tf1 to a third period Tf3.

[0098] In the first period Tf1, the first gate signal GATE1 may be sent in a low state (also referred to as a cut-off state or a cut-off level voltage state), and the second gate signal GATE2 may be sent in a high state (also referred to as a conduction state or a conduction level voltage state). In addition, in the first period Tf1, the first emission control signal EMS1 may be sent in a high state, and the second emission control signal EMS2 may be sent in a low state. Here, each of the gate signals GATE1 and GATE2 and the emission control signals EMS1 and EMS2 may have a low state or a high state. For example, in an embodiment of the present disclosure, it is assumed that the first transistor M1 to the sixth transistor M6 are applied as n-type. In this case, the low state (low level voltage state) of the signals (GATE1, GATE2, EMS1, and EMS2) may be a cut-off level voltage state, and the high state (high level voltage state) of the signals (GATE1, GATE2, EMS1, and EMS2) may be a conduction level voltage state. For another example, all or part of the first transistor M1 to the sixth transistor M6 may be applied as p-type. In this case, in the signals applied to the p-type transistor, the low state may be a conduction level voltage state, and the high state may be a cut-off level voltage state.

[0099] Accordingly, the second transistor M2 and the fourth transistor M4 may be cut off, and the third transistor M3, the fifth transistor M5, and the sixth transistor M6 may be conducting. When the sixth transistor M6 is conducting, the initialization voltage Vini sent through the initialization voltage line VL2 may be provided to the fourth node N4 through the sixth transistor M6. At this time, since the second transistor M2 and the fourth transistor M4 are in a cut-off state and the third transistor M3 and the fifth transistor M5 are in a conducting state, the capacitor Cst and the anode electrode 101a of the light-emitting device ED may be initialized by the initialization voltage Vini.

[0100] In addition, in the second period Tf2, the first gate signal GATE1 may be in a high state, and the second gate signal GATE2 may be in a low state for a certain period of the second period Tf2 and then may change to a high state for the remaining period of the second period Tf2. In addition, in the second period Tf2, the first emission control signal EMS1 and the second emission control signal EMS2 may be in a low state.

[0101] When the first strobe signal GATE1 is in the high state, the second transistor M2 is turned on. Therefore, the data signal Vdata supplied to the data line DL can be sent to the second node N2. Further, when the second strobe signal GATE2 is in the low state, the fifth transistor M5 and the sixth transistor M6 are in the off state. Therefore, the initialization voltage Vini may not be sent to the capacitor Cst and the anode electrode 101a of the light-emitting device ED.

[0102] Further, when the second strobe signal GATE2 changes to the high state, the fifth transistor M5 is turned on. Therefore, the first transistor M1 can be in the diode-connected state. When the first transistor M1 is in the diode-connected state, the data signal Vdata sent to the second node N2 can be supplied to the third node N3 through the first node N1. In this case, when the data signal Vdata is supplied to the third node N3, the threshold voltage of the first transistor M1 can be compensated. Therefore, the data signal Vdata stored in the third node N3 can have a voltage value in which the threshold voltage of the first transistor M1 is compensated.

[0103] Further, in the third period Tf3, the first strobe signal GATE1 and the second strobe signal GATE2 can be in the low state, and the second light emission control signal EMS2 and the first light emission control signal EMS1 can sequentially change from the low state to the high state. In the third period Tf3, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 can be turned off by the first strobe signal GATE1 and the second strobe signal GATE2. In the third period Tf3, the third transistor M3 and the fourth transistor M4 can be sequentially turned on by the second light emission control signal EMS2 and the first light emission control signal EMS1.

[0104] When the third transistor M3 and the fourth transistor M4 are sequentially turned on, the drive current can flow from the first node N1 to the second node N2 through the first transistor M1. Therefore, the drive current can be supplied to the light-emitting device ED, and the light-emitting device ED can emit light in response to the supplied drive current.

[0105] In this case, the third transistor M3 and the fourth transistor M4 can be turned on with a difference between the first time periods t1. That is, the fourth transistor M4 can be turned on first, and the third transistor M3 can be turned on later. After the first time period t1 has elapsed from the point at which the fourth transistor M4 is turned on, the third transistor M3 can be turned on. The first time period t1 can be adjusted according to the rate at which the voltage of the anode electrode of the light-emitting device ED increases during the refresh period Trefresh or the reset period Treset.

[0106] When the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period, the first time period t1 can be set to be shorter. In addition, when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period, the first time period t1 can be set to be longer. When the third transistor M3 is turned on, the first power supply voltage EVDD is applied to the first transistor M1 of the pixel 101, so that the drive current can flow out from the first transistor M1. Therefore, in order to shorten the first time period t1, the turn-on timing of the third transistor M3, which is turned on after the fourth transistor M4 is turned on, can be accelerated (faster). In order to set the first time period t1 to be longer, the turn-on timing of the third transistor M3, which is turned on after the fourth transistor M4 is turned on, can be delayed (slower).

[0107] Figure 10 is an illustration Figure 8 The timing diagram of the operation in the reset period of the pixel shown

[0108] Referring to Figure 10 , the reset period Treset can be a period during which a reset voltage Vreset is provided to the anode electrode 101a of the light-emitting device ED to prevent the drive current from being provided to the light-emitting device ED, thereby reducing the brightness of the image displayed on the display device 100. During the period when a data signal Vdata is written to the capacitor Cst and the data signal Vdata is held in the capacitor Cst, the reset period Treset can be repeated, thereby preventing the user from recognizing the reduction in the brightness of the image.

[0109] The reset period Treset can include a first period Tr1 to a third period Tr3. In the reset period Treset, in order to prevent the data signal Vdata from being sent to the pixel 101, the second gate signal GATE2 can be held in a low state. Therefore, the fifth transistor M5 and the sixth transistor M6 can be held in an off state during the reset period Treset. In addition, during the reset period Treset, the data signal Vdata sent in the refresh period Trefresh can be held at the capacitor Cst.

[0110] During the first period Tr1, a reset voltage Vreset may be sent to the data line DL. However, the present disclosure is not limited thereto, and the reset voltage Vreset during the first period Tr1 may be sent through a separate line different from the data line DL. In addition, during the first period Tr1, the first gate signal GATE1 may change from a low state to a high state, and the first emission control signal EMS1 may change from a high state to a low state. In addition, the second emission control signal EMS2 may remain in a low state. Therefore, during the first period Tr1, the second transistor M2 may be turned on, and the third transistor M3 and the fourth transistor M4 may be turned off. When the second transistor M2 is turned on, the reset voltage Vreset supplied to the data line DL may be sent to the second node N2 through the second transistor M2.

[0111] Then, during the second period Tr2, the first emission control signal EMS1 may remain in a low state, the first gate signal GATE1 may change from a high state to a low state, and the second emission control signal EMS2 may change from a low state to a high state. During the second period Tr2, the period when the first gate signal GATE1 remains in a high state and the period when the second emission control signal EMS2 remains in a high state may overlap. That is, the period when the fourth transistor M4 is turned on may overlap with the period when the second transistor M2 is turned on. During the refresh period Trefresh, the period when the fourth transistor M4 is turned on may not overlap with the period when the second transistor M2 is turned on, as Figure 9 shown.

[0112] When the first emission control signal EMS1 remains in a low state, the third transistor M3 remains in an off state, so that the first power supply voltage EVDD is not supplied to the pixel 101. In addition, during the period when both the first gate signal GATE1 and the second emission control signal EMS2 are in a high state, the second transistor M2 and the fourth transistor M4 may be turned on. Therefore, the reset voltage Vreset supplied to the data line DL may be sent to the fourth node N4 through the second node N2. Therefore, the anode electrode 101a of the light-emitting device ED may be initialized by the reset voltage Vreset.

[0113] When the anode electrode 101a of the light-emitting device ED is initialized by the reset voltage Vreset, the voltage of the anode electrode 101a of the light-emitting device ED may decrease, and a drive current may not be supplied to the light-emitting device ED. Therefore, when the anode electrode 101a of the light-emitting device ED is initialized by the reset voltage Vreset, the light-emitting device ED does not emit light, so that the brightness of the image displayed on the display device 100 decreases.

[0114] In addition, in the third period Tr3, the first strobe signal GATE1 may be kept in a low state, and the second emission control signal EMS2 may be kept in a high state. During the third period Tr3, the first emission control signal EMS1 may change from a low state to a high state. The timing at which the first emission control signal EMS1 changes from a low state to a high state may be after a first time period t1 has elapsed since the time when the second emission control signal EMS2 changes from a low state to a high state. In this case, the first time period t1 may be adjusted according to the rate at which the voltage of the anode electrode 101a increases during the refresh period Trefresh or the reset period Treset.

[0115] In the refresh period Trefresh or the reset period Treset, when the rate at which the voltage of the anode electrode 101a increases is fast, the first time period t1 may be set to be short. In the refresh period Trefresh or the reset period Treset, when the rate at which the voltage of the anode electrode 101a increases is slow, the first time period t1 may be set to be long. In order to shorten the first time period t1, the timing at which the third transistor M3 turns on after the fourth transistor M4 turns on may be controlled to be relatively early. In order to set the first time period t1 to be long, the time point at which the third transistor M3 turns on after the fourth transistor M4 turns on may be controlled to be relatively late.

[0116] Figure 11 is an illustration Figure 1 of the structure diagram of the timing controller 140 shown.

[0117] Referring to Figure 11 , the timing controller 140 may include a first frequency driving mode circuit 141 that executes a first frequency mode and a second frequency driving mode circuit 142 that executes a second frequency mode. In addition, the timing controller 140 may select the first frequency driving mode circuit 141 or the second frequency driving mode circuit 142 in response to a selection signal.

[0118] When the first frequency driving mode circuit 141 is selected by the selection signal, the timing controller 140 may output a data control signal DCS and a strobe control signal GCS in response to the first frequency. Here, the data control signal DCS may include a clock, a start pulse, a synchronization signal, etc. The timing controller 140 may supply the image signal RGB to the data driver circuit 120 based on the synchronization signal and the clock signal output in response to the first frequency. The timing controller 140 may cause the data driver circuit 120 to supply a data signal Vdata to the pixel 101 through the data line DL in response to the first frequency.

[0119] In addition, when the second frequency driving mode circuit 142 is selected by a selection signal, the timing controller 140 may output a data control signal DCS and a gate control signal GCS in response to the second frequency. Here, the data control signal DCS may include a clock, a start pulse, a synchronization signal, etc. In addition, the timing controller 140 may provide an image signal RGB to the data driver circuit 120 based on the synchronization signal and the clock signal output in response to the second frequency. In addition, the timing controller 140 may cause the data driver circuit 120 to provide a data signal Vdata or a reset voltage Vreset to the pixel 101 through a data line DL in response to the second frequency.

[0120] The timing controller 140 may store information about Figure 9 or Figure 10 the first time period t1 in

[0121] After the fourth transistor M4 is turned on by the second emission control signal EMS2, the first time period t1 until the third transistor M3 is turned on by the first emission control signal EMS1 may be adjusted. Accordingly, the time point at which the refresh period Trefresh or the reset period Treset starts may be adjusted. Accordingly, the luminance difference of the image displayed on the display device 100 during the refresh period Trefresh and the reset period Treset may be suppressed to prevent a user from recognizing that the image blinks in the second frequency mode.

[0122] In addition, the timing controller 140 may further include a selection circuit 143 that receives a selection signal and selects the first frequency driving mode circuit 141 or the second frequency driving mode circuit 142 based on the selection signal.

[0123] Figure 12 is a flowchart illustrating a method of driving the display device 100 according to an exemplary embodiment of the present specification.

[0124] Referring to Figure 12 , the pixel 101 in the display device 100 may receive a first power supply voltage EVDD (S1200). In addition, the pixel 101 may receive a second power supply voltage EVSS having a lower voltage level than the first power supply voltage EVDD.

[0125] The pixel 101 can receive a data signal Vdata (S1210). The data signal Vdata can be sent to the pixel 101 through a data line DL. The pixel 101 can include a light-emitting device ED that emits light through a driving current flowing from a first power supply voltage EVDD to a second power supply voltage EVSS. The pixel 101 can receive the data signal Vdata in response to a gate signal. The gate signal can include a first gate signal GATE1 and a second gate signal GATE2. In addition, when the pixel 101 can receive the data signal Vdata while receiving the first power supply voltage EVDD, the pixel 101 can generate a driving current corresponding to the data signal Vdata. The driving current can be supplied to the light-emitting device ED.

[0126] A reset voltage Vreset can be supplied to the pixel 101 (S1220). The reset voltage Vreset can be supplied to the pixel 101 through the data line DL. However, the present invention is not limited thereto, and the pixel 101 can receive the reset voltage Vreset through a line different from the data line DL. The reset voltage Vreset supplied to the pixel 101 can be supplied to the anode electrode 101a of the light-emitting device ED. When the reset voltage Vreset is supplied to the anode electrode 101a of the light-emitting device ED, the power supply voltage EVDD may not be supplied to the pixel 101.

[0127] Since the first power supply voltage EVDD is not supplied to the pixel 101, the voltage level of the anode electrode 101a receiving the reset voltage Vreset decreases. Therefore, the driving current does not flow through the light-emitting device ED. When the driving current does not flow through the light-emitting device ED, the light-emitting device ED does not emit light, so that the brightness of the image displayed on the display device 100 can be reduced. In addition, the voltage level of the reset voltage Vreset can be a voltage level lower than the threshold voltage of the light-emitting device ED included in the pixel 101.

[0128] When a first time period t1 elapses after the reset voltage Vreset is sent to the light-emitting device, the first power supply voltage EVDD can be supplied to the pixel 101 again (S1230). When the first power supply voltage EVDD is supplied to the pixel 101, the voltage level of the anode electrode of the light-emitting device ED can increase again. Therefore, the driving current flows through the light-emitting device ED, and the light-emitting device ED emits light again. In addition, after the reset voltage Vreset is supplied again and the reset voltage Vreset is sent to the light-emitting device again, when the first time period t1 elapses, the first power supply voltage EVDD can be supplied to the pixel 101. While maintaining the data signal Vdata, the reset voltage Vreset and the first power supply voltage EVDD can be repeatedly supplied.

[0129] In addition, the length of the first time period t1 can be adjusted by adjusting the timing of supplying the first power supply voltage EVDD to the pixel 101. There may be a difference between the first luminance of the image after supplying the data signal Vdata and before supplying the reset voltage Vreset and the second luminance of the image after supplying one reset voltage Vreset and before supplying the next reset voltage Vreset. In this case, the first time period t1 for supplying the first power supply voltage EVDD thereafter can be adjusted. Here, it has been described that the first power supply voltage EVDD can be supplied after cutting off the reset voltage Vreset, but it is not limited thereto, and the reset voltage Vreset can be cut off after first supplying the first power supply voltage EVDD.

[0130] In addition, the data signal Vdata can be supplied to the pixel 101 again (S1240). The data signal Vdata can be newly stored in the capacitor Cst in the pixel 101 by the data signal Vdata supplied to the pixel 101. In addition, after initializing the capacitor Cst, the data signal Vdata can be stored in the capacitor Cst.

[0131] In addition, the display device 100 can be driven in one of a first frequency mode driven at a first frequency and a second frequency mode driven at a second frequency lower than the first frequency. In the second frequency mode, the display device 100 can supply the reset voltage Vreset to the pixel 101 while holding the data signal Vdata. The first frequency mode and the second frequency mode can be selected by the timing controller 140.

[0132] Each of the first frequency mode and the second frequency mode can include a light-emitting period in which the display device 100 emits light and a non-light-emitting period in which the display device 100 does not emit light. In the first frequency mode and the second frequency mode, the number of occurrences of the light-emitting period and the non-light-emitting period in the display device 100 can be the same.

[0133] The above description has been presented to enable a person skilled in the art to make and use the technical idea of the present disclosure, and the above description has been provided in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to a person skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and the drawings have provided examples of the technical idea of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments, but rather conforms to the broadest scope consistent with the claims. The scope of protection of the present disclosure should be construed based on the appended claims, and all technical ideas within the scope of their equivalents should be construed as being included within the scope of the present disclosure.

[0134] Cross-reference to related applications

[0135] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0157158, filed in Korea on November 20, 2020, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth in this application.

Claims

1. A display device, the display device comprising: A display panel, the display panel including pixels, the pixels including light-emitting devices, wherein the pixels receive data signals corresponding to gate signals, the light-emitting devices emit light through a driving current flowing from a first power supply voltage to a second power supply voltage in response to the data signals, and the pixels receive a reset voltage at least once after receiving one data signal and before receiving the next data signal; A data driver circuit configured to provide the data signals to the pixels through data lines; A gate driver circuit configured to provide the gate signals to the pixels through gate lines and output a light-emitting control signal for controlling the supply of one of the reset voltage and the first power supply voltage to the light-emitting devices; and A timing controller configured to control the data driver circuit and the gate driver circuit, wherein when a first time period elapses after the reset voltage is sent to the light-emitting device, the first power supply voltage is transmitted to the light-emitting device, and the first time period is adjusted according to the rate of increase of the voltage of the anode electrode of the light-emitting device during a refresh period or a reset period, and wherein the first time period set when the rate of increase of the voltage of the anode electrode during the refresh period is faster than the rate of increase of the voltage of the anode electrode during the reset period is shorter than the first time period set when the rate of increase of the voltage of the anode electrode during the refresh period is slower than the rate of increase of the voltage of the anode electrode during the reset period.

2. The display device according to claim 1, wherein The first time period is determined by the light-emitting control signal.

3. The display device according to claim 1, wherein, The first time period is adjusted so as to remove flicker of an image displayed on the display device.

4. The display device according to claim 1, wherein, The light-emitting device further includes a cathode electrode and a light-emitting layer provided between the anode electrode and the cathode electrode, and wherein the first power supply voltage or the reset voltage is sent to the anode electrode, and the second power supply voltage is sent to the cathode electrode.

5. The display device according to claim 4, wherein, The gate signal includes a first gate signal and a second gate signal, the light-emitting control signal includes a first light-emitting control signal and a second light-emitting control signal, and wherein the pixel includes: A first transistor for providing the driving current to the light-emitting device in response to the data signal; A second transistor for providing the data signal from the data line to the first transistor in response to the first gate signal; A third transistor for providing the first power supply voltage to the first transistor in response to the first light-emitting control signal; A fourth transistor for providing the first power supply voltage or the reset voltage to the light-emitting device in response to the second light-emitting control signal; A fifth transistor for diode-connecting the first transistor in response to the second gate signal; A capacitor configured to hold the data signal supplied to the first transistor; and A sixth transistor configured to send an initialization voltage for initializing the capacitor and the anode electrode to the capacitor in response to the second strobe signal.

6. The display device according to claim 5, wherein, The first time period is a time difference between the second light emission control signal and the first light emission control signal.

7. The display device according to claim 5, wherein, A period during which the fourth transistor is turned on overlaps with a period during which the second transistor is turned on.

8. The display device according to claim 1, wherein, The pixel includes: A first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; A second transistor having a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to a first gate line; A third transistor having a first electrode to which the first power supply voltage is applied, a second electrode connected to the first node, and a gate electrode connected to a first light emission control line; A fourth transistor having a first electrode connected to the second node, a second electrode connected to a fourth node, and a gate electrode connected to a second light emission control line; A fifth transistor having a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to a second gate line; A capacitor having a first electrode connected to the third node and a second electrode connected to the fourth node; and A sixth transistor having a first electrode connected to an initialization voltage line that sends an initialization voltage, a second electrode connected to the fourth node, and a gate electrode connected to the second gate line.

9. The display device according to claim 1, wherein, The display panel operates in one of a first frequency mode in which it operates in response to a first frequency and a second frequency mode in which it operates in response to a second frequency lower than the first frequency, and wherein, in the second frequency mode, the reset voltage is sent through the data line.

10. The display device according to claim 1, wherein, The timing controller stores information regarding the time at which the reset voltage is provided and the first time period.

11. The display device according to claim 1, wherein, The reset voltage is sent through the data line.

12. A display device, comprising: A display panel driven in one of a first frequency mode in which it provides a data signal in response to a first frequency and a second frequency mode in which it provides the data signal in response to a second frequency lower than the first frequency; A gate driver circuit configured to provide a gate signal and a light emission control signal to the display panel; A data driver circuit configured to provide the data signal to the display panel; And A timing controller configured to control the data driver circuit and the gate driver circuit, wherein each of the first frequency mode and the second frequency mode includes at least one light emission period and at least one non-light emission period Among them, in the first frequency mode and the second frequency mode, the number of occurrences of the light emitting period and the non-light emitting period is the same. Among them, the display panel includes pixels that write the data signal in response to the gate signal, and the light emitting period and the non-light emitting period are determined in response to the light emission control signal. Among them, the pixel includes a light emitting device having an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode. Among them, one of a first power supply voltage for providing a driving current generated in response to the data signal and a reset voltage for resetting the voltage of the anode electrode is applied to the anode electrode. Among them, when a first time period elapses after the reset voltage is sent to the light emitting device, the first power supply voltage is transmitted to the light emitting device, and the first time period is adjusted according to the rate at which the voltage of the anode electrode of the light emitting device increases during a refresh period or a reset period, and Among them, the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period is shorter than the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period.

13. The display device according to claim 12, wherein, The first time period is determined by the light emission control signal.

14. The display device according to claim 12, wherein, The first time period is adjusted so as to remove the flicker of the image displayed on the display device.

15. The display device according to claim 12, wherein, The gate signal includes a first gate signal and a second gate signal, and the light emission control signal includes a first light emission control signal and a second light emission control signal, and Among them, the pixel includes: A first transistor for providing the driving current to the light emitting device in response to the data signal; A second transistor for providing the data signal from the data line to the first transistor in response to the first gate signal; A third transistor for providing the first power supply voltage to the first transistor in response to the first light emission control signal; A fourth transistor for providing the first power supply voltage or the reset voltage to the light emitting device in response to the second light emission control signal; A fifth transistor for diode-connecting the first transistor in response to the second gate signal; A capacitor for holding the data signal provided to the first transistor; and A sixth transistor for sending an initialization voltage for initializing the capacitor and the anode electrode to the capacitor in response to the second gate signal.

16. The display device according to claim 15, wherein, The first time period is the time difference between the second light emission control signal and the first light emission control signal.

17. The display device according to claim 15, wherein, In the second frequency mode, the period during which the fourth transistor is turned on overlaps with the period during which the second transistor is turned on.

18. The display device according to claim 17, wherein, In the first frequency mode, the period during which the fourth transistor is turned on does not overlap with the period during which the second transistor is turned on.

19. A driving method for a display device, the display device including pixels, the pixels including light-emitting devices, the pixels receiving data signals corresponding to a gate signal, the light-emitting devices emitting light through a driving current flowing from a first power supply voltage to a second power supply voltage in response to the data signals, the driving method including the following steps: Providing the data signals and the first power supply voltage to the pixels, and providing a driving current generated in response to the data signals to the light-emitting devices in the pixels; While the pixels hold the data signals, cutting off the first power supply voltage provided to the pixels, and providing a reset voltage to the pixels; Providing the first power supply voltage to the pixels again; And Providing the data signals to the pixels again, wherein when a first time period has elapsed after the reset voltage is sent to the light-emitting devices, the first power supply voltage is transmitted to the light-emitting devices, and the first time period is adjusted according to a rate at which a voltage of an anode electrode of the light-emitting device increases during a refresh period or a reset period, and wherein the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period is shorter than the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period.

20. The driving method according to claim 19, wherein, The light-emitting devices emit light by receiving a first light emission control signal and a second light emission control signal, and the first light emission control signal and the second light emission control signal are generated with an interval of the first time period.

21. The driving method according to claim 20, wherein, The first light emission control signal is used to control the provision of the first power supply voltage to the pixels, and the second light emission control signal is used to control the provision of the first power supply voltage or the reset voltage to the light-emitting devices.

22. The driving method according to claim 19, wherein, The first time period is adjusted such that flicker of an image displayed on the display device is removed.

23. The driving method according to claim 19, wherein, Cutting off the provision of the reset voltage to the pixels before providing the first power supply voltage to the pixels again.

24. The driving method according to claim 19, wherein, The pixels operate in one of a first frequency mode operating in response to a first frequency and a second frequency mode operating in response to a second frequency lower than the first frequency, and wherein, in the second frequency mode, the reset voltage is sent to the pixels through a data line.

25. The driving method according to claim 24, wherein, In the second frequency mode, before providing the data signals to the pixels again, the steps of cutting off the first power supply voltage provided to the pixels and providing a reset voltage to the pixels while the pixels hold the data signals and the step of providing the first power supply voltage to the pixels again can be repeated one or more times.

26. The driving method according to claim 24, wherein, Each of the first frequency mode and the second frequency mode includes at least one light emission period and at least one non-light emission period, and Wherein, in the first frequency mode and the second frequency mode, the number of occurrences of the light emitting period and the non-light emitting period is the same.

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