Display device

Abstract

The invention provides a display device, a gate drive circuit of the display device comprises N levels of cascaded gate drive units, the ith level of gate drive unit comprises a first transistor, a first frequency division signal line, a second frequency division signal line and a frequency division control module, a gate of the first transistor is electrically connected to a second node, and a gate of the second transistor is electrically connected to a third node. The source electrode and the drain electrode are electrically connected to the first clock signal line and the gate driving signal output end respectively, and the frequency division control module is electrically connected with the first node, the second node, the first frequency division signal line and the second frequency division signal line. The first frequency division signal line and the second frequency division signal line are located between the first transistor and the frequency division control module. Through the layout mode, the metal overline distance is reduced, the layout space of the gate driving unit is saved, meanwhile, different areas of the display panel are refreshed by adopting different refresh frequencies, and the power consumption of the display device is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] In practical applications, different areas of the display panel of a display device often need to display different content. For example, in some application scenarios, some areas of the display panel need to display dynamically changing content, while other areas only need to display static content or content that changes slowly.

[0003] In traditional display devices, the gate driving circuit of the display panel typically uses a uniform refresh rate to drive the entire display area. Specifically, the gate driving circuit includes multiple cascaded gate driving units, which sequentially output gate driving signals according to a fixed timing sequence to drive the pixel units in the display panel for display. Under this driving method, regardless of whether the content displayed in each area of ​​the display panel needs to be updated frequently, all areas are refreshed at the same refresh rate.

[0004] When certain areas of a display panel display static or slowly changing content, continuously refreshing these areas at a high refresh rate will lead to unnecessary power consumption. This is because, in each refresh cycle, the gate drive unit needs to output a gate drive signal to turn on the transistors in the pixel unit, thereby charging the pixel unit. For areas displaying static content, frequent refresh operations do not change the displayed content, but they continuously consume power. Especially in large-size or high-resolution display panels, due to the large number of pixel units, uniformly using a high refresh rate to drive the entire display area will result in high overall power consumption of the display device.

[0005] Furthermore, with the increase in display panel resolution and functionality, the number of transistors and signal lines in the gate drive circuit is constantly increasing, leading to a continuous increase in the layout complexity of the gate drive circuit. In the layout design of the gate drive circuit, electrical connections are required between each transistor and signal line. The routing path and length of the signal lines affect the layout space occupied by the gate drive circuit. Improper routing of the signal lines can result in them occupying excessive layout space, increasing the size of the gate drive circuit perpendicular to the gate drive unit arrangement direction. This, in turn, increases the bezel width of the display panel and reduces its screen-to-body ratio.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0007] The purpose of this application is to provide a display device that reduces power consumption and minimizes the layout space of the gate driving unit.

[0008] This application provides a display device, the display device including a display panel, the display panel including at least one gate driving circuit and a plurality of pixel units, the gate driving circuit including N cascaded gate driving units, where N is a positive integer, the i-th gate driving unit in the N-stage gate driving units including: a first transistor, the gate of the first transistor being electrically connected to a second node of the gate driving unit, one of the source and drain of the first transistor being electrically connected to a first clock signal line, the other of the source and drain of the first transistor being electrically connected to a gate driving signal output terminal; a first frequency divider signal line; a second frequency divider signal line; and a frequency divider control module, the frequency divider control module being electrically connected to the first node, the second node, the first frequency divider signal line and the second frequency divider signal line of the gate driving unit; wherein, from a top view of the display panel, the first frequency divider signal line and the second frequency divider signal line are located between the first transistor and the frequency divider control module.

[0009] In the display device, from a top-down view of the display panel, the length directions of the first frequency divider signal line and the second frequency divider signal line are parallel to the arrangement direction of the multi-stage gate driving units.

[0010] In the display device, from a top-down view of the display panel, the distance between the first frequency divider signal line and the second frequency divider signal line is less than the distance between the first frequency divider signal line and the second frequency divider signal line that is closer to the first transistor and the first transistor.

[0011] In the display device, from a top-down view of the display panel, along the length direction perpendicular to the first frequency divider signal line, the width of the first transistor is greater than the distance between the first frequency divider signal line and the second frequency divider signal line, and less than the distance between the first transistor and the one of the first frequency divider signal lines that is closer to the first transistor.

[0012] In the display device, the frequency division control module includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the gate of the second transistor is electrically connected to the first frequency division signal line, one of the source and drain of the second transistor is electrically connected to the second node, and the other of the source and drain of the second transistor is electrically connected to the first node; the gate and one of the source and drain of the third transistor are both electrically connected to the second frequency division signal line; the gate of the fourth transistor is electrically connected to the other of the source and drain of the third transistor, one of the source and drain of the fourth transistor is electrically connected to the first power supply line, and the other of the source and drain of the fourth transistor is electrically connected to the second node; the gate of the fifth transistor is electrically connected to the first frequency division signal line, one of the source and drain of the fifth transistor is electrically connected to the first power supply line, and the other of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the third transistor.

[0013] In the display device, when a first level signal is input on the first frequency divider signal line and a second level signal is input on the second frequency divider signal line, the second transistor and the fifth transistor are turned on, while the third transistor and the fourth transistor are turned off, and the potential of the first node is transmitted to the second node.

[0014] In the display device, when a second-level signal is input to the first frequency divider signal line and a first-level signal is input to the second frequency divider signal line, the second transistor and the fifth transistor are turned off, while the third transistor and the fourth transistor are turned on, and the potential of the second node is pulled down to the potential of the first power line.

[0015] In the display device, the signals input to the first frequency divider signal line and the second frequency divider signal line are out of phase.

[0016] In a display device, a display area of the display panel includes a first area and a second area arranged along the column direction of a plurality of pixel units. A plurality of rows of pixel units in the first area are electrically connected to a first-stage gate driving unit to a (j-1)-th stage gate driving unit, and a plurality of rows of pixel units in the second area are electrically connected to a j-th stage gate driving unit to a k-th stage gate driving unit, where j and k are positive integers, and 1 < j < k ≤ N; the refresh frequency of the second area is higher than that of the first area; in a driving period of a P-th frame of a picture, a second-level signal is input to the second frequency-dividing signal input terminal, a first-level signal is input to the first frequency-dividing signal input terminal, and the first-stage gate driving unit to the N-th stage gate driving unit sequentially output gate driving signals with a level of the first level, where P is a positive integer; in a first time period of a driving period of a (P + 1)-th frame of a picture, a first-level signal is input to the second frequency-dividing signal input terminal, a second-level signal is input to the first frequency-dividing signal input terminal, and the first-stage gate driving unit to the (j-1)-th stage gate driving unit output gate driving signals with a level of the second level; in a second time period of the driving period of the (P + 1)-th frame of a picture, a second-level signal is input to the second frequency-dividing signal input terminal, a first-level signal is input to the first frequency-dividing signal input terminal, and the j-th stage gate driving unit to the k-th stage gate driving unit sequentially output gate driving signals with a level of the first level.

[0017] In the display device, k < N, the display area further includes a third area, the third area is arranged along the column direction with the first area and the second area, and a plurality of rows of pixel units in the third area are electrically connected to a (k + 1)-th stage gate driving unit to the N-th stage gate driving unit; the refresh frequencies of the first area and the third area are the same; the driving period of the (P + 1)-th frame of a picture further includes a third time period, in the third time period, a first-level signal is input to the second frequency-dividing signal input terminal, a second-level signal is input to the first frequency-dividing signal input terminal, and the (k + 1)-th stage gate driving unit to the N-th stage gate driving unit output gate driving signals with a level of the second level.

[0018] In the display device, the i-th stage gate driving unit further includes: a sixth transistor, wherein the gate and one of the source and drain of the sixth transistor are electrically connected to a start signal input terminal, and the other of the source and drain of the sixth transistor is electrically connected to the first node; a seventh transistor, wherein the gate of the seventh transistor is electrically connected to the first node, one of the source and drain of the seventh transistor is electrically connected to the first clock signal line, and the other of the source and drain of the seventh transistor is electrically connected to a stage signal output terminal; and an eighth transistor, wherein the gate of the eighth transistor is electrically connected to a reset signal input terminal, and one of the source and drain of the eighth transistor is electrically connected to the first node. The eighth transistor has its source and drain connected to the first power line, with one of its sources and drains electrically connected to the first power line; the ninth transistor has its gate electrically connected to the start signal input terminal, its source and drain connected to the first power line, and the other of its source and drain connected to the third node; the tenth transistor has its gate and one of its source and drain both electrically connected to the first control signal input terminal, and the other of its source and drain connected to the third node; the eleventh transistor has its gate electrically connected to the first node, and its source and drain connected to the third node. The first power line is described above, and the other of the source and drain of the eleventh transistor is electrically connected to the third node; the twelfth transistor has its gate electrically connected to the third node, and one of its source and drain is electrically connected to the first power line, while the other of its source and drain is electrically connected to the first node; the thirteenth transistor has its gate electrically connected to the third node, and one of its source and drain is electrically connected to the first power line, while the other of its source and drain is electrically connected to the stage signal output terminal; the fourteenth transistor has its gate... The fourteenth transistor is electrically connected to the third node, with one of its source and drain electrically connected to the second power line and the other of its source and drain electrically connected to the gate drive signal output terminal; the fifteenth transistor has its gate electrically connected to the start signal input terminal, with one of its source and drain electrically connected to the first power line and the other of its source and drain electrically connected to the fourth node; the sixteenth transistor has its gate and one of its source and drain electrically connected to the second control signal input terminal, and the other of its source and drain electrically connected to the fourth node.The seventeenth transistor, whose gate is electrically connected to the first node, whose source and drain are either electrically connected to the first power line, and whose other source and drain are electrically connected to the fourth node; the eighteenth transistor, whose gate is electrically connected to the fourth node, whose source and drain are either electrically connected to the first power line, and whose other source and drain are electrically connected to the first node; the nineteenth transistor, whose gate is electrically connected to the fourth node, whose source and drain are either electrically connected to the first power line, and whose other source and drain are electrically connected to the first node; the twentieth transistor, whose gate is electrically connected to the fourth node, and whose source and drain are either electrically connected to the fourth node; and the twentieth transistor, whose gate is electrically connected to the fourth node, and whose other source and drain are either electrically connected to the fourth node. The second power line is described, with the other of the source and drain of the twentieth transistor electrically connected to the gate drive signal output terminal; the twenty-first transistor has its gate electrically connected to the first pull-down control signal terminal, one of its source and drain electrically connected to the first power line, and the other of its source and drain electrically connected to the first node; the twenty-second transistor has its gate electrically connected to the second pull-down control signal terminal, one of its source and drain electrically connected to the first power line, and the other of its source and drain electrically connected to the gate drive signal output terminal; a first capacitor has its two plates electrically connected to the first node and the gate drive signal output terminal, respectively; and a second capacitor has its two plates electrically connected to the second node and the gate drive signal output terminal, respectively.

[0019] The display device provided in the embodiments of this application achieves output control of the gate drive signal output terminal by setting a frequency division control module, a first frequency division signal line, and a second frequency division signal line in the i-th stage gate drive unit, and arranging the first and second frequency division signal lines between the first transistor and the frequency division control module. When the first frequency division signal line receives a first-level signal and the second frequency division signal line receives a second-level signal, the frequency division control module transfers the potential of the first node to the second node, and the second node controls the conduction state of the first transistor, thereby causing the gate drive signal output terminal to output a gate drive signal. When the first frequency division signal line receives a second-level signal and the second frequency division signal line receives a first-level signal, the frequency division control module pulls the potential of the second node down to the potential of the first power line. The second node is in a low-potential state, the first transistor is cut off, and the gate drive signal output terminal does not output a gate drive signal with a first-level level. By controlling the level states of the first and second frequency divider signal lines, the output control of the gate drive signal output terminal of a specific gate drive unit is achieved without affecting the cascaded transmission between gate drive units. This allows different areas of the display panel to be refreshed at different refresh frequencies. For areas with lower refresh frequencies, the number of gate drive signal outputs is reduced, the number of pixel unit charging cycles is reduced, thereby reducing the power consumption of the display device.

[0020] The display device provided in the embodiments of this application arranges the first frequency divider signal line and the second frequency divider signal line between the first transistor and the frequency divider control module, so that the connection traces between the first frequency divider signal line and the second frequency divider signal line and the frequency divider control module do not need to cross the first transistor, reducing the distance of the metal crossover traces. Since the first transistor and the frequency divider control module are arranged adjacently in the gate driving unit, when the first frequency divider signal line and the second frequency divider signal line are located between the first transistor and the frequency divider control module, the connection path between the first frequency divider signal line and the second frequency divider signal line and the frequency divider control module is shorter, reducing the number and length of cross-layer metal traces and reducing the complexity of the metal layer. At the same time, due to the reduction in the distance of the metal crossover traces, the layout space occupied by the gate driving unit in the direction perpendicular to the arrangement of the gate driving unit is reduced, thereby reducing the bezel width of the display panel and increasing the screen-to-body ratio of the display panel.

[0021] In the display device provided in the embodiments of this application, from a top-view perspective of the display panel, the distance between the first frequency divider signal line and the second frequency divider signal line is less than the distance between the first frequency divider signal line and the second frequency divider signal line closer to the first transistor and the first transistor. The first frequency divider signal line and the second frequency divider signal line are arranged close together, and the first frequency divider signal line and the second frequency divider signal line as a whole maintain a certain distance from the first transistor to avoid interference between the first frequency divider signal line and the second frequency divider signal line and the operation of the first transistor.

[0022] In the display device provided in the embodiments of this application, the display area of ​​the display panel includes a first area and a second area, and the refresh frequency of the second area is higher than that of the first area. During the driving cycle of the P-th frame, a second-level signal is input to the second frequency divider signal input terminal, a first-level signal is input to the first frequency divider signal input terminal, and the first-stage gate driving unit to the Nth-stage gate driving unit sequentially outputs gate driving signals with a first-level level. Both the first and second areas are refreshed. During the first time period of the driving cycle of the P+1-th frame, a first-level signal is input to the second frequency divider signal input terminal, a second-level signal is input to the first frequency divider signal input terminal, and the first-stage gate driving unit to the (j-1)-th-stage gate driving unit corresponding to the first area outputs gate driving signals with a second-level level. The first area is not refreshed. During the second time period of the driving cycle of the P+1-th frame, a second-level signal is input to the second frequency divider signal input terminal, a first-level signal is input to the first frequency divider signal input terminal, and the j-th to k-th-stage gate driving units corresponding to the second area sequentially output gate driving signals with a first-level level. The second area is refreshed. With this driving method, the first area is not refreshed during the driving cycle of the P+1th frame. The refresh rate of the first area is lower than that of the second area, thereby reducing the overall power consumption of the display device.

[0023] In the display device provided in the embodiments of this application, the display area further includes a third region. The first region and the third region have the same refresh frequency, while the refresh frequency of the second region is higher than that of the first and third regions. During the third time period of the driving cycle of the P+1th frame, a first-level signal is input to the second frequency divider signal input terminal, and a second-level signal is input to the first frequency divider signal input terminal. The gate driving units from the (k+1)th to the Nth level corresponding to the third region output gate driving signals with a second-level level, and the third region is not refreshed. Through this driving method, multiple regions of the display panel are refreshed using different refresh frequencies. For the first and third regions with lower refresh frequencies, the number of refreshes is reduced, further reducing the power consumption of the display device. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0025] Figure 2 A schematic diagram of the partitioning of the display area of ​​a display device provided for an embodiment of this application.

[0026] Figure 3 A circuit diagram of the gate driving unit of a display device provided in an embodiment of this application. Detailed Implementation

[0027] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0028] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0029] The technical solutions of different embodiments of this application can be combined with each other.

[0030] like Figure 1 As shown, an embodiment of this application provides a display device, which includes a display panel, a timing controller, and a source driver chip. The display panel includes at least one gate driving circuit and a plurality of pixel units PX arranged in an array. The gate driving circuit includes N cascaded gate driving units, where N is a positive integer. The gate driving circuit is integrated on at least one side of the display area of ​​the display panel and is used to provide gate driving signals to the plurality of pixel units PX to control the turning on and off of the pixel units PX. The timing controller is used to provide control signals to the gate driving circuit and the source driver chip, and the source driver chip is used to provide data signals to the plurality of pixel units PX.

[0031] In the embodiments of this application, the display panel is a liquid crystal display panel, an organic light-emitting diode display panel, a miniature light-emitting diode display panel, or a micro-light-emitting diode display panel. Taking a liquid crystal display panel as an example, the display panel includes multiple gate lines (SCAN), multiple data lines (DATA), and multiple pixel units (PX). The multiple gate lines (SCAN) extend along a first direction, and the multiple data lines (DATA) extend along a second direction. The first direction and the second direction intersect, and the multiple pixel units (PX) are respectively located at the intersection of the gate lines (SCAN) and the data lines (DATA).

[0032] like Figure 2 As shown, the i-th gate driving unit in the N-level gate driving unit includes a first transistor T21, a second transistor T81, a third transistor T83, a fourth transistor T84, a fifth transistor T82, a sixth transistor T11, a seventh transistor T22, an eighth transistor TrQ, a ninth transistor T54, a tenth transistor T51, an eleventh transistor T52, a twelfth transistor T42, a thirteenth transistor T72, a fourteenth transistor T32, a fifteenth transistor T64, a sixteenth transistor T61, a seventeenth transistor T62, an eighteenth transistor T43, a nineteenth transistor T73, a twentieth transistor T33, a twenty-first transistor T41, a twenty-second transistor T31, a first capacitor Ca, and a second capacitor Cb, where i is a positive integer and i is less than or equal to N.

[0033] In the embodiments of this application, the first transistor T21, the second transistor T81, the third transistor T83, the fourth transistor T84, the fifth transistor T82, the sixth transistor T11, the seventh transistor T22, the eighth transistor T1Q, the ninth transistor T54, the tenth transistor T51, the eleventh transistor T52, the twelfth transistor T42, the thirteenth transistor T72, the fourteenth transistor T32, the fifteenth transistor T64, the sixteenth transistor T61, the seventeenth transistor T62, the eighteenth transistor T43, the nineteenth transistor T73, the twentieth transistor T33, the twenty-first transistor T41, and the twenty-second transistor T31 are all N-type transistors. N-type transistors conduct when a first-level signal is input to their gate and are cut off when a second-level signal is input to their gate. The first transistor T21 to the twenty-second transistor T31 are also P-type transistors, or some transistors may be N-type and some may be P-type, with the level states of each signal adjusted accordingly. The first level signal is either a high level signal or a low level signal, and the second level signal is either a high level signal or a low level signal. For example, the first level signal is a high level signal and the second level signal is a low level signal.

[0034] The gate T21_G of the first transistor T21 is electrically connected to the second node Qr(i). One of the source and drain of the first transistor T21 is electrically connected to the first clock signal line CK(l), and the other of the source and drain of the first transistor T21 is electrically connected to the gate drive signal output terminal G(i). The first clock signal line CK(l) is used to provide a clock signal to the first transistor T21, where l is a positive integer. The first transistor T21 is turned on when the second node Qr(i) is at a high potential, transmitting the clock signal from the first clock signal line CK(l) to the gate drive signal output terminal G(i), thereby causing the gate drive signal output terminal G(i) to output the gate drive signal.

[0035] The i-th stage gate drive unit also includes a first frequency divider signal line Mask1, a second frequency divider signal line Mask2, and a frequency divider control module FC. The frequency divider control module FC is electrically connected to the first node Q(i), the second node Qr(i), the first frequency divider signal line Mask1, and the second frequency divider signal line Mask2. The frequency divider control module FC includes a second transistor T81, a third transistor T83, a fourth transistor T84, and a fifth transistor T82.

[0036] The gate of the second transistor T81 is electrically connected to the first frequency divider signal line Mask1. One of the sources and drains of the second transistor T81 is electrically connected to the second node Qr(i), and the other of the sources and drains of the second transistor T81 is electrically connected to the first node Q(i). The first frequency divider signal line Mask1 is used to transmit a first frequency divider signal, which can be either a first-level signal or a second-level signal. The second transistor T81 is turned on when the first frequency divider signal line Mask1 transmits the first-level signal, transferring the potential of the first node Q(i) to the second node Qr(i).

[0037] The gate, source, and drain of the third transistor T83 are all electrically connected to the second frequency divider signal line Mask2. Mask2 is used to transmit a second frequency divider signal, which can be either a first-level signal or a second-level signal. The third transistor T83 is connected in a diode configuration and is turned on when the second frequency divider signal line Mask2 transmits a first-level signal.

[0038] The gate of the fourth transistor T84 is electrically connected to the other of the source and drain of the third transistor T83. One of the source and drain of the fourth transistor T84 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the fourth transistor T84 is electrically connected to the second node Qr(i). The first power supply line VSSQ is used to provide a second-level signal. The fourth transistor T84 is used to turn on when the other of the source and drain of the third transistor T83 is at a high potential, pulling the potential of the second node Qr(i) down to the potential of the first power supply line VSSQ.

[0039] The gate of the fifth transistor T82 is electrically connected to the first frequency divider signal line Mask1. One of the sources and drains of the fifth transistor T82 is electrically connected to the first power supply line VSSQ. The other of the sources and drains of the fifth transistor T82 is electrically connected to the other of the sources and drains of the third transistor T83. The fifth transistor T82 is used to turn on when the first frequency divider signal line Mask1 transmits a first-level signal, pulling the potential of the other of the sources and drains of the third transistor T83 down to the potential of the first power supply line VSSQ, thereby turning off the fourth transistor T84.

[0040] like Figure 3As shown, from a top-down view of the display panel, the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 are located between the first transistor T21 and the frequency division control module FC. The length directions of the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 are parallel to the arrangement direction of the multi-stage gate driving units. The first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 extend along the arrangement direction of the multi-stage gate driving units and are used to transmit the first frequency divider signal and the second frequency divider signal to the multi-stage gate driving units.

[0041] From a top-down view of the display panel, the distance W1 between the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 is less than the distance W2 between the one of the first frequency divider signal lines Mask1 and Mask2 that is closer to the first transistor T21 and the first transistor T21. The first frequency divider signal lines Mask1 and Mask2 are arranged close to each other, maintaining a large gap between them and the first transistor T21. This ensures a large gap between the first frequency divider signal lines Mask1 and Mask2 and other signal lines, reducing interference between them and lowering the parasitic capacitance between them and other signal lines.

[0042] From a top-down view of the display panel, along the length direction perpendicular to the first frequency divider signal line Mask1, the width W3 of the first transistor T21 is greater than the distance W1 between the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2, and less than the distance W2 between the first transistor T21 and the one of the first frequency divider signal lines Mask1 and Mask2. The width of the first transistor T21 refers to its dimension along the length direction perpendicular to the first frequency divider signal line Mask1. By arranging the first frequency divider signal lines Mask1 and Mask2 between the first transistor T21 and the frequency divider control module FC, the length of the connecting wires between the first frequency divider signal lines Mask1 and Mask2 and the transistors in the frequency divider control module FC is reduced, the parasitic resistance and parasitic capacitance of the connecting wires are reduced, the signal transmission speed is improved, and the power consumption is reduced.

[0043] From a top-down view of the display panel, the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 are located between the first transistor T21 and the frequency divider control module FC. This results in shorter connecting wires between the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 and the second transistor T81, the third transistor T83 and the fifth transistor T82 in the frequency divider control module FC. This reduces the layout space of the gate drive circuit and improves the integration of the gate drive circuit.

[0044] like Figure 2 As shown, the gate of the sixth transistor T11, and one of its source and drain are electrically connected to the start signal input terminal STV / ST(i-4), while the other of its source and drain are electrically connected to the first node Q(i). The start signal input terminal STV / ST(i-4) receives the start signal, which is either the stage transmission signal output from the stage transmission signal output terminal of the previous stage gate drive unit or an externally input start signal STV. The sixth transistor T11 is connected in a diode configuration. When a first-level signal is input to the start signal input terminal STV / ST(i-4), the sixth transistor T11 is turned on, transmitting the start signal to the first node Q(i), thereby raising the potential of the first node Q(i).

[0045] The gate of the seventh transistor T22 is electrically connected to the first node Q(i), one of the source and drain of the seventh transistor T22 is electrically connected to the first clock signal line CK(l), and the other of the source and drain of the seventh transistor T22 is electrically connected to the stage transmission signal output terminal ST(i). The stage transmission signal output terminal ST(i) is used to provide a stage transmission signal to the lower-level gate drive unit. The seventh transistor T22 is turned on when the first node Q(i) is at a high potential, transmitting the clock signal of the first clock signal line CK(l) to the stage transmission signal output terminal ST(i), thereby causing the stage transmission signal output terminal ST(i) to output the stage transmission signal.

[0046] The gate of the eighth transistor TrQ is electrically connected to the reset signal input terminal Reset. One of the source and drain of the eighth transistor TrQ is electrically connected to the first node Q(i), and the other of the source and drain of the eighth transistor TrQ is electrically connected to the first power supply line VSSQ. The reset signal input terminal Reset is used to receive a reset signal. The eighth transistor TrQ is used to turn on when a first-level signal is input to the reset signal input terminal Reset, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ, thereby resetting the first node Q(i).

[0047] The gate of the ninth transistor T54 is electrically connected to the start signal input terminal STV / ST(i-4), one of the source and drain of the ninth transistor T54 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the ninth transistor T54 is electrically connected to the third node K(i). The ninth transistor T54 is used to turn on when a first level signal is input to the start signal input terminal STV / ST(i-4), pulling the potential of the third node K(i) down to the potential of the first power supply line VSSQ.

[0048] The gate of the tenth transistor T51, along with one of its source and drain, is electrically connected to the first control signal input terminal LC1. The other of its source and drain is electrically connected to the third node K(i). The first control signal input terminal LC1 receives the first control signal. The tenth transistor T51 is connected in a diode configuration. When a first-level signal is input to the first control signal input terminal LC1, the tenth transistor T51 is turned on, transmitting the first control signal to the third node K(i), thereby raising the potential of the third node K(i).

[0049] The gate of the eleventh transistor T52 is electrically connected to the first node Q(i), one of the source and drain of the eleventh transistor T52 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the eleventh transistor T52 is electrically connected to the third node K(i). The eleventh transistor T52 is used to turn on when the first node Q(i) is at a high potential, pulling the potential of the third node K(i) down to the potential of the first power supply line VSSQ.

[0050] The gate of the twelfth transistor T42 is electrically connected to the third node K(i), one of the source and drain of the twelfth transistor T42 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the twelfth transistor T42 is electrically connected to the first node Q(i). The twelfth transistor T42 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0051] The gate of the thirteenth transistor T72 is electrically connected to the third node K(i). One of the sources and drains of the thirteenth transistor T72 is electrically connected to the first power supply line VSSQ, and the other of the sources and drains of the thirteenth transistor T72 is electrically connected to the stage transmission signal output terminal ST(i). The thirteenth transistor T72 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the stage transmission signal output terminal ST(i) down to the potential of the first power supply line VSSQ.

[0052] The gate of the fourteenth transistor T32 is electrically connected to the third node K(i). One of the source and drain of the fourteenth transistor T32 is electrically connected to the second power supply line VSSG, and the other of the source and drain of the fourteenth transistor T32 is electrically connected to the gate drive signal output terminal G(i). The second power supply line VSSG is used to provide a second level signal. The fourteenth transistor T32 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the second power supply line VSSG.

[0053] The gate of the fifteenth transistor T64 is electrically connected to the start signal input terminal STV / ST(i-4). One of the source and drain of the fifteenth transistor T64 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the fifteenth transistor T64 is electrically connected to the fourth node P(i). The fifteenth transistor T64 is used to turn on when a first level signal is input to the start signal input terminal STV / ST(i-4), pulling the potential of the fourth node P(i) down to the potential of the first power supply line VSSQ.

[0054] The gate of the sixteenth transistor T61, along with one of its source and drain, is electrically connected to the second control signal input terminal LC2. The other of its source and drain is electrically connected to the fourth node P(i). The second control signal input terminal LC2 is used to receive the second control signal. The sixteenth transistor T61 is connected in a diode configuration. When a first-level signal is input to the second control signal input terminal LC2, the sixteenth transistor T61 is turned on, transmitting the second control signal to the fourth node P(i), thereby raising the potential of the fourth node P(i).

[0055] The gate of the seventeenth transistor T62 is electrically connected to the first node Q(i), one of the source and drain of the seventeenth transistor T62 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the seventeenth transistor T62 is electrically connected to the fourth node P(i). The seventeenth transistor T62 is used to turn on when the first node Q(i) is at a high potential, pulling the potential of the fourth node P(i) down to the potential of the first power supply line VSSQ.

[0056] The gate of the eighteenth transistor T43 is electrically connected to the fourth node P(i), one of the source and drain of the eighteenth transistor T43 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the eighteenth transistor T43 is electrically connected to the first node Q(i). The eighteenth transistor T43 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0057] The gate of the nineteenth transistor T73 is electrically connected to the fourth node P(i), one of the source and drain of the nineteenth transistor T73 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the nineteenth transistor T73 is electrically connected to the stage transmission signal output terminal ST(i). The nineteenth transistor T73 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the stage transmission signal output terminal ST(i) down to the potential of the first power supply line VSSQ.

[0058] The gate of the twentieth transistor T33 is electrically connected to the fourth node P(i). One of the sources and drains of the twentieth transistor T33 is electrically connected to the second power supply line VSSG, and the other of the sources and drains of the twentieth transistor T33 is electrically connected to the gate drive signal output terminal G(i). The twentieth transistor T33 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the second power supply line VSSG.

[0059] The gate of the 21st transistor T41 is electrically connected to the first pull-down control signal terminal ST(i+5) / Reset. One of the source and drain of the 21st transistor T41 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the 21st transistor T41 is electrically connected to the first node Q(i). The first pull-down control signal terminal ST(i+5) / Reset is used to receive the first pull-down control signal, which is either the stage transmission signal output terminal of the subsequent gate drive unit or the reset signal Reset. The 21st transistor T41 is turned on when the first level signal is input to the first pull-down control signal terminal ST(i+5) / Reset, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0060] The gate of the 22nd transistor T31 is electrically connected to the second pull-down control signal terminal G(i+4) / Reset. One of the source and drain of the 22nd transistor T31 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the 22nd transistor T31 is electrically connected to the gate drive signal output terminal G(i). The second pull-down control signal terminal G(i+4) / Reset is used to receive the second pull-down control signal, which is either the gate drive signal output terminal of the subsequent gate drive unit or the reset signal Reset. The 22nd transistor T31 is turned on when the second pull-down control signal terminal G(i+4) / Reset receives a first-level signal, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the first power supply line VSSQ.

[0061] The two plates of the first capacitor Ca are electrically connected to the first node Q(i) and the cascade signal output terminal ST(i), respectively. The first capacitor Ca is used to stabilize the potential of the first node Q(i) and further increase the potential of the first node Q(i) through bootstrapping.

[0062] The two plates of the second capacitor Cb are electrically connected to the second node Qr(i) and the gate drive signal output terminal G(i), respectively. The second capacitor Cb is used to stabilize the potential of the second node Qr(i) and further increase the potential of the second node Qr(i) through bootstrapping.

[0063] In the embodiments of this application, the signals transmitted by the first frequency divider signal line Mask1 and the second frequency divider signal line Mask2 are out of phase. When the first frequency divider signal line Mask1 transmits a first-level signal, the second frequency divider signal line Mask2 transmits a second-level signal. When the first frequency divider signal line Mask1 transmits a second-level signal, the second frequency divider signal line Mask2 transmits a first-level signal.

[0064] When the first frequency divider signal line Mask1 transmits a first-level signal and the second frequency divider signal line Mask2 transmits a second-level signal, the second transistor T81 and the fifth transistor T82 are turned on, while the third transistor T83 and the fourth transistor T84 are turned off. The turned-on second transistor T81 transfers the potential of the first node Q(i) to the second node Qr(i). The turned-on fifth transistor T82 pulls the potential of the other of the source and drain terminals of the third transistor T83 down to the potential of the first power supply line VSSQ, thereby causing the gate of the fourth transistor T84 to be at a low potential, and the fourth transistor T84 to be turned off. In this situation, the potential of the second node Qr(i) follows the potential change of the first node Q(i). When the first node Q(i) is at a high potential, the second node Qr(i) is also at a high potential, the first transistor T21 is turned on, and the gate drive signal output terminal G(i) outputs the gate drive signal.

[0065] When the first frequency divider signal line Mask1 transmits a second-level signal and the second frequency divider signal line Mask2 transmits a first-level signal, the second transistor T81 and the fifth transistor T82 are turned off, while the third transistor T83 and the fourth transistor T84 are turned on. The turned-on third transistor T83 transmits the first-level signal from the second frequency divider signal line Mask2 to the gate of the fourth transistor T84, thus turning on the fourth transistor T84. The turned-on fourth transistor T84 pulls the potential of the second node Qr(i) down to the potential of the first power supply line VSSQ. In this situation, the second node Qr(i) is at a low potential, the first transistor T21 is turned off, the gate drive signal output terminal G(i) does not output a gate drive signal with a first-level level, and the gate drive signal output terminal G(i) outputs a gate drive signal with a second-level level. The first level is either a high level or a low level, and the second level is either a high level or a low level; for example, the first level is high and the second level is low.

[0066] By coordinating the second transistor T81, the third transistor T83, the fourth transistor T84, and the fifth transistor T82, the potential of the second node Qr(i) is controlled, thereby controlling the output of the gate drive signal output terminal G(i). When the gate drive signal output terminal G(i) needs to output a gate drive signal, the first frequency divider signal line Mask1 transmits a first-level signal and the second frequency divider signal line Mask2 transmits a second-level signal, causing the potential of the second node Qr(i) to follow the potential change of the first node Q(i), thus causing the gate drive signal output terminal G(i) to output a gate drive signal. When the gate drive signal output terminal G(i) does not need to output a gate drive signal at the first level, the first frequency divider signal line Mask1 transmits a second-level signal and the second frequency divider signal line Mask2 transmits a first-level signal, causing the potential of the second node Qr(i) to be pulled low to the potential of the first power supply line VSSQ, thus causing the gate drive signal output terminal G(i) not to output a gate drive signal at the first level. In this way, the output control of the gate drive signal output terminal G(i) of a specific gate drive unit is achieved without affecting the cascaded transmission between gate drive units.

[0067] The display area of the display panel includes a first area, a second area, and a third area arranged along the column direction of multiple pixel units PX. Multiple rows of pixel units PX in the first area are electrically connected to the first-level to (j - 1)-level gate driving units, multiple rows of pixel units PX in the second area are electrically connected to the j-level to k-level gate driving units, and multiple rows of pixel units PX in the third area are electrically connected to the (k + 1)-level to N-level gate driving units, where j and k are positive integers, and 1 < j < k < N. The refresh frequency of the second area is higher than that of the first area, and the refresh frequencies of the first area and the third area are the same.

[0068] In an embodiment of the present application, the refresh frequencies of the first area and the third area are 60 Hz, and the refresh frequency of the second area is 120 Hz. The first area and the third area are used to display static content or content with slow changes, and the second area is used to display dynamically changing content. By adopting a lower refresh frequency for the first area and the third area and a higher refresh frequency for the second area, the overall power consumption of the display device is reduced.

[0069] The driving cycle for the display device to display a frame of picture includes a first time period, a second time period, and a third time period.

[0070] In the first time period of the driving cycle of the P-th frame of picture, the second frequency-divided signal line Mask2 transmits a second-level signal, the first frequency-divided signal line Mask1 transmits a first-level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off, and the first-level to (j - 1)-level gate driving units sequentially output gate driving signals G1 to Gj-1 with a first level, and the first area is refreshed.

[0071] In the second time period of the driving cycle of the P-th frame of picture, the second frequency-divided signal line Mask2 transmits a second-level signal, the first frequency-divided signal line Mask1 transmits a first-level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off, and the j-level to k-level gate driving units sequentially output gate driving signals Gj to Gk with a first level, and the second area is refreshed.

[0072] During the third time period of the driving cycle of the P-th frame, the second frequency divider signal line Mask2 transmits the second level signal, the first frequency divider signal line Mask1 transmits the first level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off, and the (k+1)th level gate driving unit to the Nth level gate driving unit sequentially output gate driving signals Gk+1 to GN with the first level, and the third area is refreshed.

[0073] During the first time period of the driving cycle of the P+1 frame, the second frequency divider signal line Mask2 transmits the first level signal, and the first frequency divider signal line Mask1 transmits the second level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on. The first-level gate driving unit to the (j-1)th-level gate driving unit all output gate driving signals G1 to Gj-1 with the second level. The first area is not refreshed.

[0074] During the second time period of the driving cycle of the P+1 frame, the second frequency divider signal line Mask2 transmits the second level signal, the first frequency divider signal line Mask1 transmits the first level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off, and the j-th level gate driving unit to the k-th level gate driving unit sequentially output gate driving signals Gj to Gk with the first level, and the second area is refreshed.

[0075] During the third time period of the driving cycle of the P+1 frame, the second frequency divider signal line Mask2 transmits the first level signal, and the first frequency divider signal line Mask1 transmits the second level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on. The gate driving units from the (k+1)th level to the Nth level all output gate driving signals Gk+1 to GN with the second level. The third region is not refreshed.

[0076] With the above driving method, the first and third regions are refreshed during the driving cycle of frame P, but not during the driving cycle of frame P+1, with a refresh rate of 60Hz for both regions. The second region is refreshed during both the driving cycles of frame P and frame P+1, with a refresh rate of 120Hz. This driving method allows different regions of the display panel to be refreshed at different refresh rates, reducing the power consumption of the display device.

[0077] In an embodiment of the present application, the gate driving unit adopts an 8-clock signal driving method, that is, the gate driving circuit uses 8 clock signal lines to provide clock signals to the gate driving unit. The first clock signal line CK(l) is one of the 8 clock signal lines, and the 8 clock signal lines are CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8 respectively. The 8 clock signal lines sequentially provide clock signals to different gate driving units.

[0078] In an embodiment of the present application, both the first power supply line VSSQ and the second power supply line VSSG are used to provide a second-level signal. In some embodiments, the first power supply line VSSQ and the second power supply line VSSG are the same power supply line. In other embodiments, the first power supply line VSSQ and the second power supply line VSSG are different power supply lines, and the potential of the second-level signal provided by the first power supply line VSSQ is the same as or different from the potential of the second-level signal provided by the second power supply line VSSG.

[0079] An embodiment of the present application further provides a driving method for a display device, and this driving method is applied to the above display device. The display device includes a display panel, the display panel includes a plurality of pixel units PX and N-level cascaded gate driving units, the display area of the display panel includes a first area and a second area arranged along the column direction of the plurality of pixel units PX, multiple rows of pixel units PX in the first area are electrically connected to the 1st-level to (j - 1)-level gate driving units, multiple rows of pixel units PX in the second area are electrically connected to the j-level to k-level gate driving units, j and k are positive integers, and 1 < j < k ≤ N, and the refresh frequency of the second area is higher than that of the first area.

[0080] This driving method includes: in the driving period of the Pth frame of the picture, the second frequency-divided signal line Mask2 of the gate driving unit transmits a second-level signal, and the first frequency-divided signal line Mask1 of the gate driving unit transmits a first-level signal, so that the 1st-level to N-level gate driving units sequentially output gate driving signals with a level of the first level, where P is a positive integer. In the first time period of the driving period of the (P + 1)th frame of the picture, the second frequency-divided signal line Mask2 of the gate driving unit transmits a first-level signal, and the first frequency-divided signal line Mask1 of the gate driving unit transmits a second-level signal, so that the 1st-level to (j - 1)-level gate driving units output gate driving signals with a level of the second level. In the second time period of the driving period of the (P + 1)th frame of the picture, the second frequency-divided signal line Mask2 of the gate driving unit transmits a second-level signal, and the first frequency-divided signal line Mask1 of the gate driving unit transmits a first-level signal, so that the j-level to k-level gate driving units sequentially output gate driving signals with a level of the first level.

[0081] In some embodiments, k < N, and the display area of the display panel further includes a third area. The third area is arranged in the column direction with the first area and the second area. Multiple rows of pixel units PX in the third area are electrically connected to the (k + 1)-th to N-th gate driving units. The refresh frequencies of the first area and the third area are the same. The driving period of the (P + 1)-th frame image further includes a third time period. The driving method further includes: in the third time period, the second frequency-dividing signal line Mask2 of the gate driving unit transmits a first-level signal, and the first frequency-dividing signal line Mask1 of the gate driving unit transmits a second-level signal, so that the (k + 1)-th to N-th gate driving units output gate driving signals with a second-level voltage.

[0082] In an embodiment of the present application, when the first frequency-dividing signal line Mask1 transmits a first-level signal and the second frequency-dividing signal line Mask2 transmits a second-level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, and the third transistor T83 in the gate driving unit is turned off. The potential of the first node Q(i) of the gate driving unit is transmitted to the second node Qr(i) of the gate driving unit.

[0083] In an embodiment of the present application, when the first frequency-dividing signal line Mask1 transmits a second-level signal and the second frequency-dividing signal line Mask2 transmits a first-level signal, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on. The potential of the second node Qr(i) of the gate driving unit is pulled down to the potential of the first power supply line VSSQ.

[0084] In an embodiment of the present application, the signals transmitted by the first frequency-dividing signal line Mask1 and the second frequency-dividing signal line Mask2 are inverted.

[0085] Through the above driving method, different areas of the display panel are refreshed at different refresh frequencies, reducing the power consumption of the display device.

[0086] The embodiments of the present application have been described in detail above. The content of this specification should not be construed as a limitation on the protection scope of the present application.

Claims

1. A display device, characterized by comprising: The display device comprises a display panel, the display panel comprising at least one gate drive circuit and a plurality of pixel units, the gate drive circuit comprising N-stage cascaded gate drive units, N being a positive integer, the i-th stage gate drive unit in the N-stage gate drive units comprising: a first transistor, a gate of the first transistor being electrically connected to a second node of the gate drive unit, one of a source and a drain of the first transistor being electrically connected to a first clock signal line, the other of the source and the drain of the first transistor being electrically connected to a gate drive signal output end; a first frequency division signal line; a second frequency division signal line; and a frequency division control module, the frequency division control module being electrically connected to a first node, the second node, the first frequency division signal line and the second frequency division signal line of the gate drive unit; wherein, in a perspective view of the display panel, the first frequency division signal line and the second frequency division signal line are located between the first transistor and the frequency division control module.

2. The display device according to claim 1, wherein In the perspective view of the display panel, a length direction of the first frequency division signal line and a length direction of the second frequency division signal line are parallel to an arrangement direction of the plurality of stages of the gate drive units.

3. The display device according to claim 1, wherein In the perspective view of the display panel, a distance between the first frequency division signal line and the second frequency division signal line is less than a distance between one of the first frequency division signal line and the second frequency division signal line close to the first transistor and the first transistor.

4. The display device according to claim 3, wherein In the perspective view of the display panel, along a direction perpendicular to the length direction of the first frequency division signal line, a width of the first transistor is greater than the distance between the first frequency division signal line and the second frequency division signal line and less than the distance between one of the first frequency division signal line and the second frequency division signal line close to the first transistor and the first transistor.

5. The display device according to claim 1, wherein The frequency division control module comprises a second transistor, a third transistor, a fourth transistor and a fifth transistor; a gate of the second transistor being electrically connected to the first frequency division signal line, one of a source and a drain of the second transistor being electrically connected to the second node, the other of the source and the drain of the second transistor being electrically connected to the first node; a gate and one of a source and a drain of the third transistor being electrically connected to the second frequency division signal line; a gate of the fourth transistor being electrically connected to the other of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor being electrically connected to a first power supply line, the other of the source and the drain of the fourth transistor being electrically connected to the second node; a gate of the fifth transistor being electrically connected to the first frequency division signal line, one of a source and a drain of the fifth transistor being electrically connected to the first power supply line, the other of the source and the drain of the fifth transistor being electrically connected to the other of the source and the drain of the third transistor.

6. The display device according to claim 5, wherein When the first frequency division signal line inputs a first level signal and the second frequency division signal line inputs a second level signal, the second transistor and the fifth transistor are turned on, the third transistor and the fourth transistor are turned off, and the potential of the first node is transmitted to the second node.

7. The display device according to claim 5, wherein When the first frequency division signal line inputs a second level signal and the second frequency division signal line inputs a first level signal, the second transistor and the fifth transistor are turned off, the third transistor and the fourth transistor are turned on, and the potential of the second node is pulled low to the potential of the first power supply line.

8. The display device according to claim 5, wherein The i-th gate drive unit further comprises: a sixth transistor, one of a gate and a source and a drain of the sixth transistor being electrically connected to a start signal input end, the other of the source and the drain of the sixth transistor being electrically connected to the first node; a seventh transistor, a gate of the seventh transistor being electrically connected to the first node, one of a source and a drain of the seventh transistor being electrically connected to the first clock signal line, the other of the source and the drain of the seventh transistor being electrically connected to a stage transmission signal output end; an eighth transistor, a gate of the eighth transistor being electrically connected to a reset signal input end, one of a source and a drain of the eighth transistor being electrically connected to the first node, the other of the source and the drain of the eighth transistor being electrically connected to the first power supply line; a ninth transistor, a gate of the ninth transistor being electrically connected to the start signal input end, one of a source and a drain of the ninth transistor being electrically connected to the first power supply line, the other of the source and the drain of the ninth transistor being electrically connected to a third node; a tenth transistor, one of a gate and a source and a drain of the tenth transistor being electrically connected to a first control signal input end, the other of the source and the drain of the tenth transistor being electrically connected to the third node; an eleventh transistor, a gate of the eleventh transistor being electrically connected to the first node, one of a source and a drain of the eleventh transistor being electrically connected to the first power supply line, the other of the source and the drain of the eleventh transistor being electrically connected to the third node; a twelfth transistor, a gate of the twelfth transistor being electrically connected to the third node, one of a source and a drain of the twelfth transistor being electrically connected to the first power supply line, the other of the source and the drain of the twelfth transistor being electrically connected to the first node; a thirteenth transistor, a gate of the thirteenth transistor being electrically connected to the third node, one of a source and a drain of the thirteenth transistor being electrically connected to the first power supply line, the other of the source and the drain of the thirteenth transistor being electrically connected to the stage transmission signal output end; a fourteenth transistor, a gate of the fourteenth transistor being electrically connected to the third node, one of a source and a drain of the fourteenth transistor being electrically connected to a second power supply line, the other of the source and the drain of the fourteenth transistor being electrically connected to a gate drive signal output end; A fifteenth transistor, a gate of the fifteenth transistor being electrically connected to the start signal input end, one of a source and a drain of the fifteenth transistor being electrically connected to the first power supply line, and the other of the source and the drain of the fifteenth transistor being electrically connected to a fourth node; A sixteenth transistor, a gate and one of a source and a drain of the sixteenth transistor being electrically connected to a second control signal input end, and the other of the source and the drain of the sixteenth transistor being electrically connected to the fourth node; A seventeenth transistor, a gate of the seventeenth transistor being electrically connected to the first node, one of a source and a drain of the seventeenth transistor being electrically connected to the first power supply line, and the other of the source and the drain of the seventeenth transistor being electrically connected to the fourth node; An eighteenth transistor, a gate of the eighteenth transistor being electrically connected to the fourth node, one of a source and a drain of the eighteenth transistor being electrically connected to the first power supply line, and the other of the source and the drain of the eighteenth transistor being electrically connected to the first node; A nineteenth transistor, a gate of the nineteenth transistor being electrically connected to the fourth node, one of a source and a drain of the nineteenth transistor being electrically connected to the first power supply line, and the other of the source and the drain of the nineteenth transistor being electrically connected to the stage transmission signal output end; A twentieth transistor, a gate of the twentieth transistor being electrically connected to the fourth node, one of a source and a drain of the twentieth transistor being electrically connected to the second power supply line, and the other of the source and the drain of the twentieth transistor being electrically connected to the gate driving signal output end; A twenty-first transistor, a gate of the twenty-first transistor being electrically connected to a first pull-down control signal end, one of a source and a drain of the twenty-first transistor being electrically connected to the first power supply line, and the other of the source and the drain of the twenty-first transistor being electrically connected to the first node; A twenty-second transistor, a gate of the twenty-second transistor being electrically connected to a second pull-down control signal end, one of a source and a drain of the twenty-second transistor being electrically connected to the first power supply line, and the other of the source and the drain of the twenty-second transistor being electrically connected to the gate driving signal output end; A first capacitor, two poles of the first capacitor being electrically connected to the first node and the stage transmission signal output end respectively; and A second capacitor, two poles of the second capacitor being electrically connected to the second node and the gate driving signal output end respectively.

9. The display device according to claim 1, wherein The signals input by the first frequency division signal line and the second frequency division signal line are inverted.

10. The display device according to claim 1, wherein The display area of the display panel comprises a first region and a second region arranged along a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first region are electrically connected to the first-stage gate driving unit to the j-1-stage gate driving unit, a plurality of rows of the pixel units in the second region are electrically connected to the j-stage gate driving unit to the k-stage gate driving unit, j and k are positive integers, and 1 < j < k ≤ N. The refresh frequency of the second region is higher than that of the first region. In a driving period of a Pth frame picture, the second frequency division signal input end inputs a second level signal, the first frequency division signal input end inputs a first level signal, and the 1st to Nth gate driving units output gate driving signals with the first level in sequence, and P is a positive integer; In a first time period in a driving period of a (P+1)th frame picture, the second frequency division signal input end inputs the first level signal, the first frequency division signal input end inputs the second level signal, and the 1st to (j-1)th gate driving units output gate driving signals with the second level; In a second time period in the driving period of the (P+1)th frame picture, the second frequency division signal input end inputs the second level signal, the first frequency division signal input end inputs the first level signal, and the jth to kth gate driving units output gate driving signals with the first level in sequence.

11. The display device according to claim 10, wherein k<N, the display area further comprises a third area, the third area is arranged along the column direction with the first area and the second area, and a plurality of rows of pixel units in the third area are electrically connected with the (k+1)th to Nth gate driving units; The first area and the third area have the same refresh frequency; The driving period of the (P+1)th frame picture further comprises a third time period, in which the second frequency division signal input end inputs the first level signal, the first frequency division signal input end inputs the second level signal, and the (k+1)th to Nth gate driving units output gate driving signals with the second level.

Images