Electronic device

Abstract

An electronic device includes an array substrate. The array substrate includes a first gate line, a second gate line, a third gate line, a first pixel unit, a second pixel unit, a third pixel unit, and a gate driver circuit. The third gate line is disposed between the first gate line and the second gate line. The first pixel unit is electrically connected to the first gate line and a data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driver circuit is electrically connected to the first gate line, the second gate line, and the third gate line. The gate driver circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] In some products, the use of a dual-gate-line layout in electronic devices helps reduce the amount of data drive circuitry required. However, this design still has some areas for improvement. Summary of the Invention

[0003] This disclosure provides an electronic device that can provide good display effects.

[0004] According to an embodiment of this disclosure, an electronic device includes an array substrate. The array substrate includes: a first gate line, a second gate line, and a third gate line, wherein the third gate line is disposed between the first gate line and the second gate line; a data line; a first pixel unit electrically connected to the first gate line and the data line; a second pixel unit electrically connected to the second gate line and the data line; a third pixel unit electrically connected to the third gate line and the data line; and a gate driving circuit electrically connected to the first gate line, the second gate line, and the third gate line, wherein the gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.

[0005] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the present disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0007] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 This is a schematic diagram of a portion of the driving waveforms of an electronic device according to an embodiment of this disclosure;

[0009] Figure 3 and Figure 4 This is a schematic diagram and a driving waveform diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 5 This is a schematic diagram of the driving waveform of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 6 and Figure 7 This is a schematic diagram and a driving waveform diagram of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 8 This is a partial top view schematic diagram of the light-shielding layer of an electronic device according to an embodiment of the present disclosure;

[0013] Figures 9 to 12 This is a partial cross-sectional schematic diagram of an electronic device according to several embodiments disclosed herein. Detailed Implementation

[0014] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0015] In this disclosure, a structure (or layer, component, substrate) located on / above another structure (or layer, component, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. A non-direct connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate spacer) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In this disclosure, when a structure is positioned "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0016] The electrical connections or couplings described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components on two circuits, but not limited to these.

[0017] In this disclosure, the thickness, length, and width can be measured using an optical microscope, while the thickness can be measured from a cross-sectional image using an electron microscope, but these methods are not limited to this. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10%, 5%, or 3% between the first and second values.

[0018] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0019] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of this disclosure. Figure 1 In this embodiment, the electronic device 100 includes an array substrate 110. The array substrate 110 includes a first gate line G1, a second gate line G2, and a third gate line G3, as well as a data line DL, a first pixel unit P1, a second pixel unit P2, and a third pixel unit P3 connected to a gate driving circuit 120. The third gate line G3 is disposed between the first gate line G1 and the second gate line G2. The first pixel unit P1 is electrically connected to the first gate line G1 and the data line DL, the second pixel unit P2 is electrically connected to the second gate line G2 and the data line DL, and the third pixel unit P3 is electrically connected to the third gate line G3 and the data line DL. The gate driving circuit 120 is electrically connected to the first gate line G1, the second gate line G2, and the third gate line G3. Furthermore, the gate driving circuit 120 provides a first gate driving signal to the first pixel unit P1, a second gate driving signal to the second pixel unit P2, and a third gate driving signal to the third pixel unit P3 in a time sequence. In this embodiment, the array substrate 110 may also include a data driving circuit 130. The data driving circuit 130 is electrically connected to the data line DL to provide a first data signal to the first pixel unit P1 and a second data signal to the second pixel unit P2.

[0020] like Figure 1 As shown, the array substrate 110 may include multiple lines. Lines extending along a first direction D1 may include gate lines, such as a first gate line G1, a second gate line G2, and a third gate line G3. Lines extending along a second direction D2 may include data lines DL. The first direction D1 is different from the second direction D2. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular to each other, but this is not a limitation. In this embodiment, the first gate line G1, the third gate line G3, and the second gate line G2 are three gate lines on the array substrate 110 that are sequentially adjacent to each other. Therefore, there are no other gate lines (lines for transmitting gate drive signals) between the first gate line G1 and the third gate line G3, and there are no other gate lines (lines for transmitting gate drive signals) between the third gate line G3 and the second gate line G2.

[0021] Additionally, the array substrate 110 may include a plurality of pixel units P arranged in an array along a first direction D1 and a second direction D2. Hereinafter, we will first describe the first pixel unit P1, the second pixel unit P2, and the third pixel unit P3 among these pixel units P. In this embodiment, the first pixel unit P1 and the third pixel unit P3 are arranged adjacent to each other along the first direction D1. The first pixel unit P1 and the third pixel unit P3 may be located between the first gate line G1 and the third gate line G3, and the first pixel unit P1 and the third pixel unit P3 are located on opposite sides of the data line DL. The first pixel unit P1 and the second pixel unit P2 are arranged adjacent to each other along the second direction D2. The third gate line G3 and the second gate line G2 are both located between the first pixel unit P1 and the second pixel unit P2, and the first pixel unit P1 and the second pixel unit P2 are located on the same side of the data line DL. In this embodiment, the distance GD1 between the third gate line G3 and the second gate line G2 along the second direction D2 is smaller than the distance GD2 between the third gate line G3 and the first gate line G1 along the second direction D2.

[0022] The first pixel unit P1 and the third pixel unit P3 are located on opposite sides of the data line DL, but are both electrically connected to the data line DL. Simultaneously, the first pixel unit P1 is electrically connected to the first gate line G1, and the third pixel unit P3 is electrically connected to the third gate line G3. In some embodiments, the first pixel unit P1, the second pixel unit P2, and the third pixel unit P3 may each include an active component (not shown) and a pixel electrode (not shown) connected to the active component. The active component may be, for example, a transistor, and may include a gate, a source, and a drain. The gate may be connected to a corresponding gate line, and the drain may be connected to a corresponding data line. For example, the gate in the first pixel unit P1 may be connected to the corresponding gate line G1, and the drain may be connected to the corresponding data line DL. In some embodiments, when the electronic device 100 is used to provide a display function, the electrical signals of the pixel electrodes can be used to drive the display layer or the light-emitting material to present the brightness to be displayed. In the first pixel unit P1, the gate of the active component is connected to the first gate line G1, and the source is connected to the data line DL. In the third pixel unit P3, the gate of the active component is connected to the third gate line G3, and the source is connected to the data line DL. Furthermore, in the second pixel unit P2, the gate of the active component is connected to the second gate line G2, while the source is connected to the data line DL. In this embodiment, the first gate line G1 and the third gate line G3, the data line DL, the first pixel unit P1, and the third pixel unit P3 can form a dual-gate-line shared data line (2G1D) layout.

[0023] Figure 2 This is a schematic diagram of the waveforms of some drive signals of an electronic device according to an embodiment of this disclosure. For ease of explanation, Figure 2 Presented Figure 1The gate drive signals for the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4, as well as the data signal for the data line DL, are provided by the gate drive circuit 120. The gate drive signals can be provided to the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4, while the data signal can be provided to the data line DL by the data drive circuit 130. For ease of explanation, the drive waveforms for the first pixel unit P1, the second pixel unit P2, the third pixel unit P3, and the fourth pixel unit P4 will be described here. The fourth pixel unit P4 is electrically connected to the fourth gate line G4 and the data line DL. The fourth pixel unit P4 and the second pixel unit P2 are arranged adjacent to each other in the first direction D1. The fourth pixel unit P4 and the third pixel unit P3 are arranged adjacent to each other in the second direction D2. The fourth pixel unit P4 and the second pixel unit P2 are located on opposite sides of the data line DL. Furthermore, the fourth pixel unit P4 and the second pixel unit P2 are located between the second gate line G2 and the fourth gate line G4. The second gate line G2 and the third gate line G3 are located between the fourth pixel unit P4 and the third pixel unit P3.

[0024] Reference Figure 1 and Figure 2 The driving method of the electronic device 100 includes providing a first gate signal waveform 122, a second gate signal waveform 124, a third gate signal waveform 126 and a fourth gate signal waveform 128 to a first gate line G1, a second gate line G2, a third gate line G3 and a fourth gate line G4 respectively by a gate driving circuit 120; and providing a data signal waveform 132 to a data line DL by a data driving circuit 130.

[0025] The first gate signal waveform 122, the second gate signal waveform 124, the third gate signal waveform 126, and the fourth gate signal waveform 128 oscillate between a high level GH and a low level GL, respectively. The first gate drive signal 122H with a high level GH can activate the active component of the first pixel unit P1; the second gate drive signal 124H with a high level GH can activate the active component of the second pixel unit P2; the third gate drive signal 126H with a high level GH can activate the active component of the third pixel unit P3; and the fourth gate drive signal 128H with a high level GH can activate the active component of the fourth pixel unit P4. During one frame period, the first gate line G1 remains at a low level GL except for the first gate drive signal 122H; the second gate line G2 remains at a low level GL except for the second gate drive signal 124H; the third gate line G3 remains at a low level GL except for the third gate drive signal 126H; and the fourth gate line G4 remains at a low level GL except for the first gate drive signal 128H.

[0026] The first gate drive signal 122H can pre-scan the active component of the first pixel unit P1 during time t1 to time t2, and maintain the gate of the active component of the first pixel unit P1 at a high level GH during time t2 to time t3. Therefore, the first drive time GT1 of the first gate drive signal 122H can last from time t1 to time t3. The second gate drive signal 124H can be provided to the second gate line G2 from time t2 to time t3 to pre-scan the active component of the second pixel unit P2, and remains at a high level GH until time t4. Therefore, the second drive time GT2 of the second gate signal waveform 124 can last from time t2 to time t4. According to some embodiments, such as Figure 2 As shown, the first driving time GT1 of the first gate driving signal 122H and the second driving time GT2 of the second gate driving signal 124H may at least partially overlap. In some embodiments, the overlap ratio of the first driving time GT1 of the first gate driving signal 122H and the second driving time GT2 of the second gate driving signal 124H may be, for example, between 10% and 90%, between 10% and 60%, between 40% and 60%, or between 45% and 65%, but is not limited thereto. The above overlap ratio is based on the first driving time GT1 being 100%. Similarly, the third driving time GT3 of the third gate driving signal 126H may be from time t3 to time t5, and the fourth driving time GT4 of the fourth gate driving signal 128H may be from time t4 to time t6.

[0027] The level of the data signal waveform 132 can be varied according to the desired effect (e.g., the brightness of the pixel unit). Figure 2 The data signal waveform 132 shown is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this embodiment, the data signal waveform 132 on the data line DL includes a first data signal 132A, a second data signal 132B, a third data signal 132C, and a fourth data signal 132D. (See also...) Figure 1 and Figure 2During the first driving time GT1, from time t1 to time t2, the first pixel unit P1 is pre-scanned, causing the first gate drive signal 122H of the first gate line G1 to turn on the active component of the first pixel unit P1. During the first driving time GT1, from time t2 to time t3, the active component of the first pixel unit P1 has indeed been turned on, for example, the gate of the active component has been maintained at a high level GH, so that the first data signal 132A is written to the first pixel unit P1 from time t2 to time t3. During the second driving time GT2, from time t2 to time t3, the second pixel unit P2 is pre-scanned to turn on the active component of the second pixel unit P2. During the second driving time GT2, from time t3 to time t4, the first gate line G1 has a low level GL, and the gate of the active component of the second pixel unit P2 has a high level GH, so the second data signal 132B can be written to the second pixel unit P2. Next, during the third driving time GT3, the third pixel unit P3 is also subjected to a similar operation, causing the third data signal 132C to be written to the third pixel unit P3 during time t4 to time t5 of the third driving time GT3. The fourth pixel unit P4 is also written with the fourth data signal 132D during time t5 to time t6 of the fourth driving time GT4 under the fourth gate driving signal 128H. Thus, under the driving of the first gate driving signal 122H, the second gate driving signal 124H, the third gate driving signal 126H, and the fourth gate driving signal 128H, as... Figure 1 As shown, the first pixel unit P1, the second pixel unit P2, the third pixel unit P3, and the fourth pixel unit P2 are updated along the inverted N-shaped path PD.

[0028] In this embodiment, the first pixel unit P1 and the third pixel unit P3 are located between the first gate line G1 and the third gate line G3. According to... Figure 2At time t3, the signal writing to the first pixel unit P1 terminates. Simultaneously, the third gate line G3 adjacent to the first pixel unit P1 is at a low level GL. Therefore, the level of the first pixel unit P1 and the low level GL of the third gate line G3 establish a parasitic capacitance CP1 associated with the first pixel unit P1. After time t3, since the third gate line G3 remains at a low level GL for most of the frame cycle, as it was at time t3, the signal written to the first pixel unit P1 does not experience significant shifts or fluctuations. Therefore, the brightness of the first pixel unit P1 remains stable throughout the frame cycle. Similarly, at time t5, the first gate line G1 adjacent to the third pixel unit P3 is at a low level GL. Therefore, although a parasitic capacitance CP3 is established between the first gate line G1 and the third pixel unit P3 at time t5, the signal written to the third pixel unit P3 does not experience significant shifts or fluctuations due to changes in the level of the first gate line G1. Furthermore, the second gate line G2 pre-scans the second pixel unit P2 between time t2 and time t3 of the second driving time GT2, and therefore has a high level GH at time t3. However, since there is a third gate line G3 between the second gate line G2 and the first pixel unit P1, the second gate line G2 does not have a significant capacitive coupling effect on the first pixel unit P1. Therefore, the high level GH of the second gate line G2 at time t3 is not likely to cause signal offset or fluctuation in the first pixel unit P1. Overall, when the electronic device 100 is used to display an image, the display brightness of the first pixel unit P1 and the third pixel unit P3 can be maintained stably. Similarly, the brightness of other pixel units P can also be maintained stably.

[0029] Figure 1In this embodiment, multiple pixel units P on the array substrate 110 can be used to display different colors. For example, the colors displayed by the multiple pixel units P on the array substrate 110 include red, green, and blue, but are not limited thereto. In some embodiments, adjacent pixel units P in the second direction D2 can be used to display the same color. For example, the first pixel unit P1 and the second pixel unit P2 are, for example, the same color. In some embodiments, in addition to adjacent pixel units P in the second direction D2 being used to display the same color, adjacent pixel units P in the first direction D1 can be used to display different colors. For example, the first pixel unit P1 and the second pixel unit P2 are, for example, the same color, and the first pixel unit P1 and the third pixel unit P3 are different colors. In this embodiment, pixel units P arranged in a column in the second direction D2 can display the same color. The electronic device 100 can provide pixel units P of three colors, and the pixel units P of the three colors are arranged sequentially and repeatedly along the first direction D1. For example, pixel unit P in the first row R1 displays the first color, pixel unit P in the second row R2 displays the second color, pixel unit P in the third row R3 displays the third color, and pixel unit P in the fourth row R4 displays the first color. However, the color configuration of pixel unit P is not limited to this.

[0030] In this embodiment, the level of the data signal waveform 132 can be classified as a positive or negative signal, for example, based on a shared signal value Vcom. Specifically, a signal with a level higher than the shared signal value Vcom is a positive signal, while a signal with a level lower than the shared signal value Vcom is a negative signal. Figure 1 and Figure 2As shown, the first data signal 132A and the second data signal 132B may have opposite polarities. For example, the first data signal 132A may be positive, the second data signal 132B negative, the third data signal 132C negative, and the fourth data signal 132D positive. Because the level difference between signals of different polarities is large, the level on the data line DL may not immediately reach the expected level during polarity conversion. For example, at time t3, the level on the data line DL may not drop directly from the positive first data signal 132A to the negative second data signal 132B. Similarly, the conversion between the third data signal 132C and the fourth data signal 132D at time t5 has a similar situation. Thus, the data signal written to the corresponding pixel unit P after polarity conversion may differ slightly from the expected signal. In this embodiment, the second pixel unit P2 and the fourth pixel unit P4 are the pixel units P for which the data signal is written after polarity conversion. Therefore, in some embodiments, the brightness of the second pixel unit P2 and the fourth pixel unit P4 may not be as expected. This will result in bright or dark fringes along the first direction D1. In some embodiments, the phenomenon of bright or dark fringes can be improved by adjusting the driving waveform. For example, the driving time and the corresponding data signal output time can be adjusted by driving control to lengthen the time when the second pixel unit P2 and the fourth pixel unit P4 are written with data signals, thereby ensuring that the second pixel unit P2 and the fourth pixel unit P4 can have the predetermined level to be presented.

[0031] In this embodiment, the second pixel unit P2 and the third pixel unit P3 are used to display different colors and are updated sequentially, but their corresponding driving times overlap (e.g., between time t3 and time t4), which may cause a color mix problem. The color mix described here can be understood as the third pixel unit P3 possibly being written with the data signal of the second pixel unit P2. However, the first pixel unit P1 and the second pixel unit P2 are used to display the same color, so no color mix problem occurs, and the same applies to the third pixel unit P3 and the fourth pixel unit P4. Therefore, the color mix problem caused by the driving sequence in the electronic device 100 is less noticeable. For example, among the first pixel unit P1, the second pixel unit P2, the third pixel unit P3, and the fourth pixel unit P4, only the third pixel unit P3 has a color mix problem.

[0032] In some embodiments, the first gate line G1 and the third gate line G3 are adjacent to the first pixel unit P1. Furthermore, the first gate line G1 and the third gate line G3 are adjacent, meaning there are no other gate lines between them. In some embodiments, the first driving time GT1 of the first gate line G1 and the third driving time GT3 of the third gate line G3 can be designed to not overlap. Thus, as... Figure 2 As shown, during the first driving time GT1 of driving the first pixel unit P1, the third gate line G3 adjacent to the first pixel unit P1 does not undergo any electrical change. Therefore, the parasitic capacitance CP1 generated by the third gate line G3 during the first driving time GT1 is unlikely to affect the first pixel unit P1. That is, the signal change of the third gate line G3 during the frame cycle is unlikely to change the signal written to the first pixel unit P1, or the disturbance to the signal written to the first pixel unit P1 is very small. Therefore, the parasitic capacitance CP1 generated by the capacitive coupling between the third gate line G3 and the first pixel unit P1 can reduce the impact on the signal written to the first pixel unit P1. In some embodiments, the first driving time GT1 of the first gate line G1 and the third driving time GT3 of the third gate line G3 can be designed to partially overlap, such as... Figure 7 As shown. Similarly, the parasitic capacitance CP1 generated by the third gate line G3 can reduce the impact on the signal written to the first pixel unit P1. In some embodiments, the overlap ratio of the first driving time GT1 of the first gate line G1 and the third driving time GT3 of the third gate line G3 may be, for example, less than 50%, for example, between 0% and 70%, for example, between 0% and 50%, for example, between 0.1% and 30%, but is not limited thereto. The above overlap ratio is based on the first driving time GT1 being 100%.

[0033] Figure 3 and Figure 4 This is a schematic diagram and a driving waveform diagram of an electronic device according to an embodiment of the present disclosure. Figure 3 The electronic device 100 is roughly the same as Figure 1 The electronic device is 100 similar, but Figure 3 Presenting electronic devices 100 Figure 4 A schematic diagram driven by the driving waveform. Identical components in both embodiments are represented by the same component symbols and will not be repeated here. This embodiment differs from... Figure 1 and Figure 2The embodiment is characterized in that the data signal waveform 232 is provided by the data driving circuit 130. Specifically, the data signal waveform 232 includes a first data signal 232A written to a first pixel unit P1, a second data signal 232B written to a second pixel unit P2, a third data signal 232C written to a third pixel unit P3, and a fourth data signal 232D written to a fourth pixel unit P4. Here, the first data signal 232A and the second data signal 232B have the same polarity. For example, the first data signal 232A, the second data signal 232B, the first data signal 232C, and the fourth data signal 232D are all positive polarity signals that are high relative to the shared signal value Vcom.

[0034] In this embodiment, the other four pixel units in the electronic device 100 can be designated as a first pixel unit P1', a second pixel unit P2', a third pixel unit P3', and a fourth pixel unit P4'. The driving methods for the first pixel units P1', P2', P3', and P4' are the same as those for the first pixel units P1, P2', P3', and P4', except that the data signals written to the first pixel units P1', P2', P3', and P4' all have the same polarity, for example, negative polarity. Thus, in one frame cycle, only the first pixel unit P1' is affected by the polarity reversal of the data signal among the first pixel units P1', P2', P3', and P4'. Similarly, among the first pixel units P1 to P4, only the first pixel unit P1 may be affected by the polarity reversal of the data signal. In other words, the polarity reversal of the electronic device 100 occurs only after updating four pixel units, which helps to reduce the number of pixel units that may produce bright or dark patterns. For example, bright or dark patterns caused by the polarity reversal of the data signal are only distributed in a dotted manner on the screen displayed by the electronic device 100.

[0035] Figure 5 This is a schematic diagram of the driving waveform of an electronic device according to an embodiment of this disclosure. Figure 5 In the middle, the data signal waveform 232 is provided by the data drive circuit 130. Figure 3 The data line DL. The trigger waveform Tp can be used to trigger the output of the data signal to control when the corresponding signal is provided. Figure 3 The data line DL. The first gate signal waveform CK1, the second gate signal waveform CK2, the third gate signal waveform CK3, and the fourth gate signal waveform CK4 are provided by the gate drive circuit 120. Figure 3The first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4 are shown in the figure. Please also refer to... Figure 3 and Figure 5 Based on the trigger signal Tp1 of the trigger waveform Tp, the data signal to be written to the first pixel unit P1 is provided to the data line DL from time ta until the first gate signal waveform CK1 drops from high level GH to low level GL. However, before time ta, the first gate line G1 has already been input with a high level GH. During time ta to time ta', the active component of the first pixel unit P1 can be reliably turned on to allow the data signal on the data line DL to be written to the first pixel unit P1. Therefore, time ta to time ta' can be regarded as the effective charging time TC1 of the first pixel unit P1. Similarly, based on the trigger signals Tp2, Tp3, and Tp4 of the trigger waveform Tp, the effective charging time TC2 of the second pixel unit P2 is from time tb to time tb', the effective charging time TC3 of the third pixel unit P3 is from time tc to time tc', and the effective charging time TC4 of the fourth pixel unit P4 is from time td to time td'. In some embodiments, the length of the effective charging time can be adjusted by adjusting the output time of the trigger signals Tp1, Tp2, Tp3, and Tp4. For example, if the first pixel unit P1 receives data signals of different polarities from the preceding pixel unit (not shown), then Tp2 / Tp3 / Tp4 can be delayed and their charging times TC2 / TC3 / TC4 shortened to extend TC1, ensuring that the signal written to the first pixel unit P1 matches the expected value. In this way, bright or dark fringes caused by polarity switching can be improved. Thus, the effective charging time TC1 of the first pixel unit P1 is longer than the effective charging time TC2 of the second pixel unit P2, the effective charging time TC3 of the third pixel unit P3, and the effective charging time TC4 of the fourth pixel unit P4. Figure 1 and Figure 2 In the implementation method described above, a similar approach can also be adopted. Figure 5 The effective charging time of different pixel units P can be adjusted in this way. In addition, time ta' and time tb can be the same in some embodiments, and similarly, time tb' and time tc, and time tc' and time td can also be the same.

[0036] Figure 6 and Figure 7 This is a schematic diagram and a driving waveform diagram of an electronic device according to an embodiment of the present disclosure. Figure 6 The electronic device 100 is roughly the same as Figure 1 The electronic device is 100 similar, but Figure 6 Presenting electronic devices 100 Figure 7 A schematic diagram driven by the driving waveform. Identical components in both embodiments are represented by the same component symbols and will not be repeated here. This embodiment differs from... Figure 1 and Figure 2 The embodiment is characterized in that a first gate signal waveform 322, a second gate signal waveform 324, a third gate signal waveform 326, and a fourth gate signal waveform 328 are provided by a gate driving circuit 120, and a data signal waveform 332 is provided by a data driving circuit 130. Specifically, the first gate signal waveform 322, the second gate signal waveform 324, the third gate signal waveform 326, and the fourth gate signal waveform 328 oscillate between a high level GH and a low level GL, respectively. A first gate driving signal 322H with a high level GH can activate the active component of the first pixel unit P1, a second gate driving signal 324H with a high level GH can activate the active component of the second pixel unit P2, a third gate driving signal 326H with a high level GH can activate the active component of the third pixel unit P3, and a fourth gate driving signal 328H with a high level GH can activate the active component of the fourth pixel unit P4. During a frame cycle, the first driving time GT1 of the first gate driving signal 322H and the second driving time GT2 of the second gate driving signal 324H are synchronized, and the third driving time GT3 of the third gate driving signal 326H and the fourth driving time GT4 of the fourth gate driving signal 328H are synchronized. In some embodiments, so-called synchronization can be understood as the first driving time GT1 and the second driving time GT2 and / or the third driving time GT3 and the fourth driving time GT4 largely overlapping, for example, more than 90% overlap. In some embodiments, so-called synchronization can be understood as the first driving time GT1 and the second driving time GT2 almost completely overlapping and / or the third driving time GT3 and the fourth driving time GT4 almost completely overlapping. In some embodiments, so-called synchronization can be understood as the overlap time of the first driving time GT1 and the second driving time GT2 and / or the third driving time GT3 and the fourth driving time GT4 being greater than the non-overlapping time.

[0037] The data signal waveform 332 includes a first data signal 332A and a second data signal 332B. During the first drive time GT1 and the second drive time GT2, time t1 to time t2 can be the pre-scan time, and time t2 to time t3 can be the charging (writing) time. During time t2 to time t3, the first data signal 332A is provided to the data line DL. Therefore, the first pixel unit P1 and the second pixel unit P2 can be written with the same data signal, such as the first data signal 332A, and have a level A. Similarly, during the third drive time GT3 and the fourth drive time GT4, time t2 to time t3 can be the pre-scan time, and time t3 to time t4 can be the charging (writing) time. During time t3 to time t4, the second data signal 332B is provided to the data line DL. Therefore, the third pixel unit P3 and the fourth pixel unit P4 can be written with the same data signal, such as the second data signal 332B, and have a level B. Levels A and B can be the same or different. When level A and level B are different, level A can be greater than or less than level B, without limitation. In this embodiment, the synchronization of the first driving time GT1 and the second driving time GT2, and the synchronization of the third driving time GT3 and the fourth driving time GT4, enable two pixel units with the same color to be updated synchronously and display the same image information, which helps to speed up the update rate. Compared to the method of updating each pixel unit one by one, the update rate of this embodiment can be increased by approximately two times, which is beneficial for applying the electronic device 100 to game devices (e.g., game console screens, game consoles), but is not limited thereto. In some embodiments, such as Figure 6 and Figure 7 As shown, the first pixel unit P1 and the second pixel unit P2 can be the same color, the third pixel unit P3 and the fourth pixel unit P4 can be the same color, and the first pixel unit P1 and the third pixel unit P2 can be different colors. When the first pixel unit P1 and the second pixel unit P2 are written with the same first data signal 332A, and the third pixel unit P3 and the fourth pixel unit P4 are written with the same second data signal 332B, the update rate can be increased by up to two times.

[0038] In some embodiments, the electronic device may include an array substrate (such as any of the array substrates described above), a counter substrate opposite the array substrate, and a display layer disposed between the array substrate and the counter substrate. In addition to driving the display layer to achieve a display effect, some components on the array substrate and the counter substrate can also be used to define light-shielding areas and non-light-shielding areas, and may be referred to as a light-shielding layer. In some embodiments, the light-shielding layer is not necessarily made of an opaque material, but can achieve an opaque effect through a driving mechanism. The light-shielding layer can be used to block components that are not desired to be seen, and can also be used to define the display area. Therefore, the layout design of the light-shielding layer can affect the display aperture ratio and / or display effect of the electronic device.

[0039] Figure 8 This is a partial top view of the light-shielding layer of an electronic device according to an embodiment of this disclosure. For ease of explanation and to simplify the drawings, Figure 8 The array substrate 110 and the individual components of the opposing substrate are not shown in detail, but only the layout of the light-shielding layer is schematically presented. Figure 8 The electronic device includes a light-shielding layer 300, wherein Figure 8 The presented area roughly corresponds to Figure 1 Part 100A of the array substrate 110. Figure 8 In this structure, the light-shielding layer 300 may have a horizontal light-shielding area 302, a first vertical light-shielding area 304A, and a second vertical light-shielding area 304B. The horizontal light-shielding area 302, the first vertical light-shielding area 304A, and the second vertical light-shielding area 304B can enclose multiple opening areas 306 to serve as display or light-emitting areas. The horizontal light-shielding area 302, the first vertical light-shielding area 304A, and the second vertical light-shielding area 304B are areas with low light transmittance, while the opening areas 306 are areas with high light transmittance.

[0040] The light-shielding layer 300 can be set in Figure 1 In the electronic device 100, the relationship between the light-shielding layer 300 and the components on the array substrate 110 is as follows, but not limited thereto. Each opening region 306 may, for example, be defined as follows: Figure 1 The display area of ​​each pixel unit P. The horizontal light-blocking areas 302 roughly overlap. Figure 1 The gate lines (e.g., the second gate line G2 and the third gate line G3) extend along the first direction D1. The first longitudinal light-shielding regions 304A substantially overlap. Figure 1 The data line DL extends along the second direction D2. The first direction D1 and the second direction D2 may intersect each other. The second longitudinal light-shielding area 304B roughly overlaps. Figure 1 The area between the third pixel unit P3 and the fifth pixel unit P5 extends along the second direction D2. The area where the second vertical light-blocking area 304B is located may not have a data line DL.

[0041] In this embodiment, the first pixel unit P1, the third pixel unit P3, and the fifth pixel unit P5 are arranged adjacent to each other along the first direction D1. The first light-shielding area 304A is located between the first pixel unit P1 and the third pixel unit P3, and the second light-shielding area 304B is located between the third pixel unit P3 and the fifth pixel unit P5. According to some embodiments, the first width WA of the first light-shielding area 304A is greater than the second width WB of the second light-shielding area 304B. The width of the light-shielding layer 300 in the longitudinal light-shielding area of ​​this embodiment can be the size of the light-shielding layer 300 measured along the first direction D1. In some embodiments, the first width WA and the second width WB can be, for example, between 5 micrometers and 30 micrometers. In addition, the first longitudinal light-shielding area 304A can be wider than the data line DL to shield the data line. In some embodiments, the first width WA of the light-shielding layer 300 in the first longitudinal light-shielding area 304A can be greater than the second width WB of the second longitudinal light-shielding area 304B. The light-shielding layer 300 has a relatively narrow second width WB in the second longitudinal light-shielding area 304B, which helps to increase the area of ​​the opening area 306 that can be disposed in the overall electronic device. Therefore, the design of the light-shielding layer 300 with light-shielding areas of unequal width helps to maintain a sufficient aperture ratio. In some embodiments, the difference between the first width WA and the second width WB can be greater than 10% of the first width WA, but is not limited thereto. In some embodiments, the light-shielding layer 300 has light-shielding areas of different widths in different regions, but the width WC of the plurality of opening areas 306 defined by the light-shielding layer 300 can be the same size. Figure 8 As shown, the electronic device can be viewed in its top view when it is illuminated. The area with display and light emission is the opening area 306, and the area without display and light emission is the light-shielding area. In the top view, the first width WA of the first light-shielding area 304A and the second width WB of the second light-shielding area 304B can be measured.

[0042] Figures 9 to 12 This is a partial cross-sectional schematic diagram of an electronic device according to several embodiments of the present disclosure, wherein Figures 9 to 12 Only partial components of the electronic device are shown for illustrative purposes; the electronic device may include other components not shown in the figures. Figures 9 to 12 The cross-sectional structure can correspond to Figure 1 The electronic device 100 in the embodiment along line II is described below; therefore, the reference numerals for some components will be used with reference to [other components]. Figure 1 The label. In addition. Figures 9 to 12 The first direction D1, the second direction D2, and the third direction D3 are used to understand the orientation of each component in the electronic device, and the first direction D1, the second direction D2, and the third direction D can be perpendicular to each other, but are not limited thereto.

[0043] exist Figure 9In the electronic device 400, an array substrate 410, a counter substrate 420, and a display layer 430 are located between the array substrate 410 and the counter substrate 420. The array substrate 410 includes at least a substrate 412, a plurality of insulating layers 414A to 414C, a color filter layer 416, at least two metal layers 418A and 418B, and a transparent conductive layer 419. Insulating layers 414A to 414C are sequentially disposed on the substrate 412 and at least serve to separate and protect the two metal layers 418A and 418B. For example, metal layer 418A is disposed between the substrate 412 and insulating layer 414A, while metal layer 418B is disposed between insulating layers 414A and 414B. Additionally, color filter layer 416 is disposed between insulating layers 414B and 414C, and transparent conductive layer 419 is disposed on insulating layer 414C. Metal layers 418A and 418B can be used to form conductor lines and conductor components in the array substrate 410. For example, metal layer 418A may include shielding lines SH1 to SH3, while metal layer 418B may include data lines DL. Additionally, Figure 9 Although not shown, metal layer 418A may also include Figure 1 The first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4 are provided. In some embodiments, metal layers 418A and 418B can be used to form components such as gates, sources, drains, and / or shared electrodes of active components.

[0044] The array substrate 410 may have multiple pixel units, which are respectively Figure 1 A first pixel unit P1, a third pixel unit P3, and a fifth pixel unit P5 are arranged along a first direction D1. The first pixel unit P1, the third pixel unit P3, and the fifth pixel unit P5 each include an active component and a pixel electrode electrically connected to the active component. Figure 9 The image presents a pixel electrode PE1 for a first pixel unit P1, a pixel electrode PE3 for a third pixel unit P3, and a pixel electrode PE5 for a fifth pixel unit P5. Pixel electrodes PE1, PE3, and PE5 are formed from the same film layer, such as a transparent conductive layer 419. A color filter layer 416 includes a first color pattern 416A, a second color pattern 416B, and a third color pattern 416C corresponding to different pixel units. The first color pattern 416A overlaps with pixel electrode PE1 and can be used to determine the color of the first pixel unit P1. The second color pattern 416B overlaps with pixel electrode PE2 and can be used to determine the color of the second pixel unit P2. The third color pattern 416C overlaps with pixel electrode PE3 and can be used to determine the color of the third pixel unit P3. The colors of the first color pattern 416A, the second color pattern 416B, and the third color pattern 416C can be red, green, and blue, respectively, but are not limited thereto.

[0045] In this embodiment, the data line DL is located between pixel electrode PE1 and pixel electrode PE3, that is, between the first pixel unit P1 and the third pixel unit P3, and is used to provide corresponding data signals to the first pixel unit P1 and the third pixel unit P3. The projection of shielding line SH1 on substrate 412 is located between the projection of pixel electrode PE1 on substrate 412 and the projection of data line DL on substrate 412, while the projection of shielding line SH2 on substrate 412 is located between the projection of pixel electrode PE2 on substrate 412 and the projection of data line DL on substrate 412. In this way, shielding lines SH1 and SH2 can provide signal shielding, reducing the influence of the signal of data line DL on the signals of pixel electrode PE1 and pixel electrode PE3. In addition, there is no data line between pixel electrode PE3 and pixel electrode PE5, and the projection of shielding line SH3 on substrate 412 is located between the projection of pixel electrode PE3 on substrate 412 and the projection of pixel electrode PE5 on substrate 412.

[0046] The opposing substrate 420 may include a substrate 422 and an opposing electrode 424 disposed between the substrate 422 and the display layer 430. When the electronic device 400 displays an image, pixel electrodes PE1, PE3, and PE5 can be written with corresponding data signals, while the opposing electrode 424 is written with a shared signal to generate a driving electric field for driving the display layer 430, thereby allowing the first pixel unit P1, the third pixel unit P3, and the fifth pixel unit P5 to display a predetermined brightness.

[0047] In addition, the electronic device 400 also includes a light-shielding layer 300A. The light-shielding layer 300A includes a light-shielding electrode 442A, a light-shielding electrode 442B, a light-shielding display portion 444A, and a light-shielding display portion 444B. The film layers of the light-shielding electrodes 442A and 442B are the same as those of the pixel electrodes PE1, PE3, and PE5, which are all transparent conductive layers 419. The light-shielding display portions 444A and 444B are respectively portions of the display layer 430 that overlap with the light-shielding electrodes 442A and 442B.

[0048] When the electronic device 400 displays a screen, a shared signal is written to the opposing electrode 424, and the light-shielding electrode 442A and the light-shielding electrode 442B are also written with a shared signal, so that both sides of the light-shielding display area 444A and the light-shielding display area 444B have the same voltage level. When the display layer 444 includes liquid crystal molecules, since the light-shielding electrode 442A and the opposing electrode 424 both have the same signal, the liquid crystal molecules in the light-shielding display area 444A are in a state of no tilt or rotation, forming an opaque first light-shielding area 440A1. Similarly, the light-shielding electrode 442B and the opposing electrode 424 both have the same signal, so that the light-shielding display area 444B is in a state of no tilt or rotation, forming an opaque second light-shielding area 440A2. Therefore, the light-shielding electrode 442A and the light-shielding electrode 442B themselves are transparent, but can be used to define the first light-shielding area 440A1 and the second light-shielding area 440A2, respectively.

[0049] The first light-shielding area 440A1 is located between the first pixel unit P1 and the third pixel unit P3, while the second light-shielding area 440A2 is located between the third pixel unit P3 and the fifth pixel unit P5. The first light-shielding area 440A1, for example, has sufficient width to shield the data line DL. In some embodiments, the light-shielding layer 300A can be applied to... Figure 8 In this embodiment, a light-shielding layer 300 is implemented. Thus, the first width WA of the first light-shielding region 440A1 can be greater than the second width WB of the second light-shielding region 440A2. In this embodiment, the width of the light-shielding region electrode 442A can be greater than, less than, or equal to the width occupied by the shielding lines SH1 and SH2. The first width WA can be the width of the light-shielding region electrode 442A, or the width occupied by the shielding lines SH1 and SH2, whichever is larger. For example, Figure 9 In this design, the edge of the light-shielding electrode 442A can be located above the shielding lines SH1 and SH2. That is, the width of the light-shielding electrode 442A can be less than the width occupied by the outer edges E1 and E2 of the shielding lines SH1 and SH2. Therefore, the first width WA can be the width between the outer edges E1 and E2 of the shielding lines SH1 and SH2. The width of the light-shielding electrode 442B can be greater than, less than, or equal to the width of the shielding line SH3. The second width WB can be either the width of the light-shielding electrode 442B or the width of the shielding line SH3, whichever is larger.

[0050] Figure 10 The electronic device 500 is roughly similar to Figure 9 The electronic device 400, therefore, Figure 10 Continued Figure 9 The component symbols are used, and the same component symbols in the two embodiments represent the same components and can be referenced to each other. Figure 10The electronic device 500 includes an array substrate 410, a counter substrate 420, and a display layer 430 located between the array substrate 410 and the counter substrate 420. The main difference between electronic device 500 and electronic device 400 is that electronic device 500 omits [the array substrate 410, counter substrate 420, and display layer 430]. Figure 4 The light-shielding electrodes 442A and 442B are located in the electronic device 500. However, the data line DL, shielding line SH1, shielding line SH2, and shielding line SH3 of the electronic device 500 provide light-shielding, thus defining light-shielding areas 540A1 and 540A2. In other words, the data line DL, shielding line SH1, shielding line SH2, and shielding line SH3 constitute a light-shielding layer 300B in the electronic device 500. In this embodiment, the widths of the data line DL, shielding line SH1, and shielding line SH2 can be designed such that the projections of the data line DL on the substrate 412 overlap or connect the projections of the shielding lines SH1 and SH2 on the substrate 412, thereby defining the light-shielding area 540A1. Similar to the aforementioned embodiments, the light-shielding layer 300B has a first width WA in the light-shielding area 540A1 between the first pixel unit P1 and the third pixel unit P3, and a second width WB in the light-shielding area 540A2 between the third pixel unit P3 and the fifth pixel unit P5, wherein the first width WA is greater than the second width WB.

[0051] Figure 11 The electronic device 600 is roughly similar to Figure 10 The electronic device 500, therefore, Figure 11 Continued Figure 10 The component symbols are used, and the same component symbols in the two embodiments represent the same components and can be referenced to each other. Figure 11 The electronic device 600 includes an array substrate 410, a counter substrate 420, and a display layer 430 located between the array substrate 410 and the counter substrate 420. The electronic device 600 also includes a light-shielding layer 300B composed of data lines DL, shielding lines SH1, SH2, and SH3. In this embodiment, the array substrate 410 further includes light-shielding patterns 652 and 654. In this embodiment, light-shielding patterns 652 and 654 can be located in light-shielding areas 540A1 and 540A2, respectively, where light-shielding area 540A1 is defined by data lines DL, shielding lines SH1 and SH2, and light-shielding area 540A2 is defined by shielding line SH3. That is, the implementation of light-shielding areas 540A1 and 540A2 of the electronic device 600 is generally similar to... Figure 10The electronic device 500. Additionally, a light-shielding pattern 652 is disposed between the first color pattern 416A and the second color pattern 416B of the color filter layer 416, while a light-shielding pattern 654 is disposed between the second color pattern 416B and the third color pattern 416C of the color filter layer 416. The colors of the first color pattern 416A, the second color pattern 416B, and the third color pattern 416C are different from each other; therefore, the light-shielding pattern 652 can prevent color mixing between the first color pattern 416A and the second color pattern 416B, and the light-shielding pattern 654 can prevent color mixing between the second color pattern 416B and the third color pattern 416C. In this embodiment, the width of the light-shielding pattern 652 can be greater than, less than, or equal to the width occupied by the shielding lines SH1 and SH2. The first width WA can be the width of the light-shielding pattern 652, or the width occupied by the shielding lines SH1 and SH2, based on the larger of the two. For example, Figure 11 In this design, the first width WA can be the width between the outer edge E1 of shielding wire SH1 and the outer edge E2 of shielding wire SH2. The width of the light-shielding pattern 654 can be greater than, less than, or equal to the width of shielding wire SH3. The second width WB can be either the width of the light-shielding pattern 654 or the width of shielding wire SH3, whichever is larger.

[0052] Figure 12 The electronic device 700 includes an array substrate 710, a counter substrate 720, and a display layer 430 located between the array substrate 710 and the counter substrate 720. Some components of the electronic device 700 are generally similar to... Figure 9 In this embodiment, the same component symbols in both embodiments can be referenced to each other. The array substrate 710 includes at least a substrate 412, a plurality of insulating layers 414A-414C, at least two metal layers 418A and 418B, and a transparent conductive layer 419, wherein the substrate 412, the plurality of insulating layers 414A-414C, the at least two metal layers 418A and 418B, and the transparent conductive layer 419 can be referenced to... Figure 9 The electronic device 400 is described. Metal layer 418A may include shielding lines SH1 to SH3, etc., while metal layer 418B may include data lines DL, etc. Specifically, the array substrate 710 differs from... Figure 9 The array substrate 410 is characterized in that it does not include a color filter layer. Additionally, the opposing substrate 720 includes a substrate 422, an opposing electrode 424, a color filter layer 426, and a light-shielding layer 300C. The color filter layer 726 is disposed, for example, between the opposing electrode 424 and the substrate 422, while the light-shielding layer 300C is disposed between the color filter layer 726 and the substrate 422.

[0053] In this embodiment, the color filter layer 726 may include a first color pattern 726A disposed on the first pixel unit P1, a second color pattern 726B disposed on the second pixel unit P2, and a third color pattern 726C disposed on the third pixel unit P3. The first light-shielding pattern 728A of the light-shielding layer 300C is located between the first color pattern 726A and the second color pattern 726B, and the second light-shielding pattern 728B of the light-shielding layer 300C is located between the second color pattern 726B and the third color pattern 726C. The material of the light-shielding layer 300C includes light-shielding materials, such as metal, light-shielding resin, etc. Therefore, the first light-shielding pattern 728A and the second light-shielding pattern 728B can respectively define light-shielding areas 740A1 and 740A2. The first light-shielding pattern 728A is located above the data line DL and can at least block the data line DL. In some embodiments, the light-shielding area 740A1 defined by the first light-shielding pattern 728A has a first width WA, while the light-shielding area 740A2 defined by the second light-shielding pattern 728B has a second width WB, and the first width WA is greater than the second width WB. In some embodiments, the size and relative relationship between the first width WA and the second width WB can be referred to... Figure 10 The embodiments are described, but are not limited thereto.

[0054] In summary, the electronic device of this disclosed embodiment employs a dual gate line shared data line (2G1D) layout and updates pixel units using an inverted N-shaped update path. In some embodiments, the two gate lines adjacent to each pixel unit can provide gate drive signals with non-overlapping drive times, so the parasitic capacitance of the gate lines is less likely to affect the level written to each pixel unit, thus improving phenomena such as bright or dark lines that fail to present the expected brightness. In some embodiments, the polarity reversal of the data signal occurs between adjacent pixel units of the same color, not within an entire row of pixel units of a specific color. Therefore, the unsatisfactory display brightness caused by signal polarity reversal is not limited to a specific color, which helps improve the display effect of the electronic device. In some embodiments, the polarity reversal of the data signal occurs in dotted pixel units, so the unsatisfactory display brightness caused by signal polarity reversal is presented as a dotted distribution, which helps optimize the display effect of the electronic device. In some embodiments, the length of the drive time can be adjusted to improve the unsatisfactory display brightness caused by signal polarity reversal. In some embodiments, adjacent pixel units of the same color can have synchronized drive times, which can improve the update rate. In some embodiments, the electronic device further includes a light-shielding layer, which may have different widths to provide a more flexible layout to accommodate the design of the array substrate.

[0055] In summary, according to some embodiments, the first gate line and the third gate line are arranged adjacent to each other, and in terms of timing, the second gate driving signal is delivered between the first gate driving signal and the third gate driving signal. Thus, the parasitic capacitance generated by the third gate line during the first driving time can have a small or no effect on the first pixel unit, resulting in a better display effect.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. An electronic device, characterized in that, include: Array substrate, the array substrate comprising: A first gate line, a second gate line, and a third gate line extend along a first direction, wherein the third gate line is disposed between the first gate line and the second gate line; The data cable extends along a second direction, which is different from the first direction. The first pixel unit is electrically connected to the first gate line and the data line; The second pixel unit is electrically connected to the second gate line and the data line; The third pixel unit is electrically connected to the third gate line and the data line. Wherein the first pixel unit and the third pixel unit are arranged adjacent to each other along the first direction, and the first pixel unit and the second pixel unit are arranged adjacent to each other along the second direction; and A gate driving circuit is electrically connected to the first gate line, the second gate line, and the third gate line, and provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence. In this frame cycle, the first driving time of the first gate driving signal and the second driving time of the second gate driving signal at least partially overlap.

2. The electronic device according to claim 1, characterized in that, It also includes a data driving circuit electrically connected to the data line to provide a first data signal for the first pixel unit and a second data signal for the second pixel unit, wherein the first data signal and the second data signal have opposite polarities.

3. The electronic device according to claim 1, characterized in that, It also includes a data driving circuit electrically connected to the data line to provide a first data signal for the first pixel unit and a second data signal for the second pixel unit, wherein the first data signal and the second data signal have the same polarity.

4. The electronic device according to claim 1, characterized in that, The first pixel unit and the second pixel unit are the same color, and the first pixel unit and the third pixel unit are different colors.

5. The electronic device according to claim 1, characterized in that, During the frame cycle, the first driving time of the first gate driving signal and the third driving time of the third gate driving signal do not overlap.

6. The electronic device according to claim 1, characterized in that, During the frame cycle, the first driving time of the first gate driving signal and the third driving time of the third gate driving signal partially overlap.

7. The electronic device according to claim 1, characterized in that, It also includes a fifth pixel unit, wherein the first pixel unit, the third pixel unit and the fifth pixel unit are arranged adjacent to each other along a first direction, a first light-shielding area is located between the first pixel unit and the third pixel unit, a second light-shielding area is located between the third pixel unit and the fifth pixel unit, and the first width of the first light-shielding area is greater than the second width of the second light-shielding area.

Images