Differential transmission circuit, chip and electronic equipment

By optimizing the signal path design and common-mode feedback technology, the problems of slow response speed, poor common-mode stability, high power consumption and insufficient noise suppression capability of traditional LVDS transmitter circuits in high-speed and high-precision application scenarios have been solved, realizing a high-speed, low-power and highly robust differential transmitter circuit.

CN122178852APending Publication Date: 2026-06-09GUANGDONG UNIV OF TECH +1
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Patent Information

Application Number
CN202610251115.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-03
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

Traditional LVDS transmitter circuits suffer from slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression in high-speed and high-precision applications.

Method used

It employs a single-slip drive enhancement circuit and a differential drive circuit, including a transmission gate, an inverter chain, a buffer, a common-mode feedback module, and a bias module. By optimizing the signal path design, dynamic biasing, and common-mode feedback technology, it achieves a balance between high speed, low power consumption, and high robustness.

Benefits of technology

It significantly improves response speed, driving capability, power efficiency and common-mode stability, and enhances noise suppression capability, making it suitable for high-speed, low-power and high-interference-resistant application scenarios.

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Abstract

The invention discloses a differential transmission circuit, a chip and electronic equipment, and the circuit comprises a single-to-differential driving enhancement circuit which comprises a single-ended digital input end (IN) and first differential output ends (INP, INN), and is used for converting an input single-ended digital signal into a pair of differential signals; the differential driving circuit is connected to the first differential output ends (INP and INN), comprises second differential output ends (OUTP and OUTN) and is used for converting the differential signals into differential output voltages; wherein the single-slip driving enhancement circuit comprises a transmission gate (Tran) and a phase inverter, and is used for generating the differential signal of which the phase difference is 180 degrees and the time sequence is matched. The embodiment of the invention aims to solve the technical problems of low response speed, poor common-mode stability, high power consumption and insufficient noise suppression capability when the transmitting circuit is applied to the LVDS interface in the prior art.
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