Differential transmitting circuit, chip and electronic device

Abstract

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

Description

Technical Field

[0001] This application relates to a differential transmitter circuit, chip, and electronic device, belonging to the field of analog integrated circuits. Background Technology

[0002] In modern electronic systems, with the increasing demand for high-speed data transmission, Low-Voltage Differential Signaling (LVDS) technology has become one of the core technologies for high-speed serial interfaces due to its advantages such as low power consumption, high interference immunity, and low electromagnetic radiation. The LVDS transmitter circuit, as a core component of this technology, directly determines the data transmission rate, power consumption, and reliability.

[0003] Traditional LVDS transmitter circuits face multiple challenges in high-speed, high-precision applications, including stability, power consumption, and integration. They are typically based on current-mode logic, generating a low-swing signal of approximately 350mV in the differential pair by controlling a 3.5mA constant current source, and relying on terminating resistors to ensure signal integrity. While this basic structure can meet medium-speed requirements, it is susceptible to process variations, temperature fluctuations, and power supply noise, causing the output signal to deviate from the standard range.

[0004] Specifically, parasitic capacitance at the output node limits circuit response speed, while high-frequency ripple introduced by traditional level-shifting structures (such as charge pumps) exacerbates signal distortion. These factors collectively constitute obstacles to achieving higher circuit speeds. Furthermore, when the transmission rate changes dynamically, fixed-structure drive circuits struggle to simultaneously meet the demands of large swing at low speeds and low-capacitance loads at high speeds, limiting the system's application flexibility.

[0005] Reliability is also a key challenge in LVDS transmitter circuit design. Under power-off or short-circuit conditions, leakage current between the output node and the power supply may exceed standard limits, compromising the device's self-protection function. Simultaneously, the miniaturization of process dimensions increases the sensitivity of transistor parameters, further amplifying the effects of matching errors and common-mode drift.

[0006] In summary, traditional LVDS transmitter circuits have significant shortcomings in common-mode stability, speed-power balance, dynamic adaptability, and reliability. Therefore, researching novel driver circuit architectures and achieving a balance between high speed, low power consumption, and high robustness through common-mode feedback optimization and dynamic current control techniques has become a crucial issue in the development of high-speed interface technology. These innovations will drive LVDS technology to play a core role in a wider range of high-performance electronic systems. Summary of the Invention

[0007] In view of this, this application provides a differential transmitter circuit, chip, and electronic device. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

[0008] The first aspect of this application discloses a differential transmission circuit, the differential transmission circuit comprising: A single-slip drive enhancement circuit includes a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; A differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), includes a second differential output terminal (OUT_P, OUT_N), used to convert the differential signal into a differential output voltage; The single-slip drive enhancement circuit includes a transmission gate (Tran) and an inverter chain to generate the differential signal with a phase difference of 180° and timing matching.

[0009] Furthermore, the single-slip drive enhancement circuit also includes a first buffer (BUF1) and a phase-locked module, and the inverter includes a first inverter (INV1) and a second inverter (INV2); The input terminal of the first buffer (BUF1) is connected to the single-ended digital input terminal (IN), the output terminal of the first buffer (BUF1) is connected to the input terminal of the first inverter (INV1), and the output terminal of the first inverter (INV1) is connected to the input terminal of the second inverter (INV2) and the input terminal of the transmission gate (Tran). The phase-locked module is connected between the output of the second inverter (INV2) and the output of the transmission gate (Tran) and has the first differential output (IN_P, IN_N).

[0010] Furthermore, the phase-locked module includes a third inverter (INV3) and a fourth inverter (INV4); The input terminal of the third inverter (INV3) is connected to the first terminal (IN_P) of the first differential output terminal (IN_P,IN_N), and its output terminal is connected to the second terminal (IN_N) of the first differential output terminal (IN_P,IN_N). The input terminal of the fourth inverter (INV4) is connected to the second terminal (IN_N) of the first differential output terminal (IN_P,IN_N), and its output terminal is connected to the first terminal (IN_P) of the first differential output terminal (IN_P,IN_N).

[0011] Furthermore, the single-slip drive enhancement circuit also includes a second buffer (BUF2), a third buffer (BUF3), a fourth buffer (BUF4), and a fifth buffer (BUF5); The output of the second inverter (INV2) is connected to the input of the second buffer (BUF2). The output of the second buffer (BUF2) is connected to the input of the third inverter (INV3), the output of the fourth inverter (INV4), and the input of the fourth buffer (BUF4). The output of the fourth buffer (BUF4) is connected to the first terminal (IN_P). The output of the transmission gate (Tran) is connected to the input of the third buffer (BUF3). The output of the third buffer (BUF3) is connected to the output of the third inverter (INV3), the input of the fourth inverter (INV4), and the input of the fifth buffer (BUF5). The output of the fifth buffer (BUF5) is connected to the second terminal (IN_N).

[0012] Furthermore, the differential drive circuit includes: The output stage includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), and a second NMOS transistor (MN2). The sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are interconnected, and the sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are interconnected. The gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are connected to the first terminal (IN_P), and the gates of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are connected to the second terminal (IN_N). The drains of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are connected to the third terminal (OUT_N) of the second differential output terminal (OUT_P, OUT_N), and the drains of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are connected to the fourth terminal (OUT_P) of the second differential output terminal (OUT_P, OUT_N). The common-mode feedback module is connected to the second differential output terminal (OUT_P, OUT_N) and is used to sample the common-mode voltage and compare it with the reference voltage (VREF) to generate a feedback control signal. The bias module is used to provide bias current; The feedback control signal output by the common-mode feedback module regulates the current flowing through the output stage to stabilize the common-mode voltage of the second differential output terminal (OUT_P, OUT_N).

[0013] Furthermore, the common-mode feedback module includes: The first resistor (R1) and the second resistor (R2) are connected in series between the third terminal (OUT_N) and the fourth terminal (OUT_P), and the midpoint generates a sampling voltage (VCM) representing the common-mode voltage. An operational amplifier (AMP1) has its non-inverting input connected to the sampling point of the sampling voltage (VCM) and its inverting input receiving the reference voltage (VREF). The third PMOS transistor (MP3) has its gate connected to the output of the operational amplifier (AMP1) to receive the feedback control signal, its source connected to the power supply, and its drain connected to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2).

[0014] Furthermore, the bias module includes: Bias current source (IBIAS); The third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) form a current mirror; The gate and drain of the third NMOS transistor (MN3) are connected to the bias current source (IBIAS), and its source is grounded. The gate of the fourth NMOS transistor (MN4) is connected to the gate of the third NMOS transistor (MN3), its source is grounded, and its drain is connected to the source of the first NMOS transistor (MN1) and the second NMOS transistor (MN2).

[0015] Furthermore, a load resistor (Rload) is connected between the second differential output terminals (OUT_P, OUT_N).

[0016] A second aspect of this application discloses a chip, which includes the differential emitter circuit described in the above embodiments.

[0017] A third aspect of this application discloses an electronic device, which includes the differential transmission circuit described in the above embodiments.

[0018] Compared with the prior art, the fully integrated on-chip differential transmitter circuit of this application achieves the following beneficial effects through its innovative circuit design and modular structure: 1) Improved Response Speed: This invention effectively improves the circuit's response speed by optimizing the signal path design. The transmission gate (Tran) in the single-slip drive enhancement circuit operates in parallel with the inverter chain (INV1, INV2), aiming to make the transmission times of the two generation paths for the differential signals IN_P and IN_N as equal as possible. This matching of transmission delays reduces signal distortion, laying the foundation for high-speed data transmission.

[0019] 2) Enhanced driving capability: The circuit uses buffers (BUF1-BUF5) with progressively increasing driving capability to ensure that the generated differential signal has sufficient driving capability to quickly switch the power transistors (MP1, MP2, MN1, MN2) in the subsequent differential drive circuit, thereby accelerating the establishment of the output state.

[0020] 3) Optimized power efficiency: The circuit incorporates a dynamic bias design in the differential drive module, effectively optimizing power efficiency. By mirroring the bias currents of MN3 and MN4, this structure allows for dynamic adjustment of the output stage current according to actual operating requirements, avoiding the static current waste that may exist in traditional circuits and achieving power control under different operating conditions.

[0021] 4) Enhanced Common-Mode Stability: Resistors R1 and R2 sample the voltage at the output terminals (OUT_P and OUT_N) to obtain the common-mode voltage VCM. This VCM is sent to operational amplifier AMP1 and compared with the reference voltage VREF. Its output controls the gate of common-source transistor MP3. This negative feedback loop can automatically adjust the current of MP3, thereby overcoming the effects of power supply voltage fluctuations, temperature changes, and other factors, and stably locking the output common-mode voltage at VREF, significantly improving the system's common-mode stability and anti-interference capability.

[0022] 5) Enhanced noise suppression: As a differential signal system, this circuit naturally suppresses common-mode noise. Any external interference coupled to the differential signal pair will be significantly canceled out when subtracted at the receiver. The common-mode feedback loop stabilizes the common-mode voltage while also reducing its fluctuations, further lowering the risk of common-mode noise converting into differential-mode noise and improving overall signal integrity.

[0023] In summary, this invention, through its unique circuit design and modular structure, not only significantly improves the performance of differential transmitter circuits, but also provides an efficient and reliable solution for applications such as LVDS interfaces. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a single-slip drive enhancement circuit diagram provided for an embodiment of this application.

[0026] Figure 2 This is a differential drive circuit diagram provided for an embodiment of this application.

[0027] Figure label: BUF1, 2, 3, 4, 5 represent the first to fifth buffers, which are digital buffers; INV1, 2, 3, 4 represent the first to fourth inverters, which are digital inverters; Tran represents the transmission gate; MP1, 2, 3 represent the first to third PMOS transistors; MN1, 2, 3, 4 represent the first to fourth NMOS transistors; R1, R2, Rload represent polysilicon resistors; AMP1 represents the operational amplifier, which is a single-ended output amplifier; IN represents the digital input terminal; IN_P, IN_N represent the first differential output terminal; OUT_P, OUT_N represent the second differential output terminal; IBIAS represents the bias current source; VCM represents the sampling voltage / common-mode voltage; VREF represents the reference voltage. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] like Figure 1 He Ru Figure 2 As shown in the figure, this application embodiment provides a differential transmitter circuit for use in a low-voltage differential signal LVDS interface. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal IN and a first differential output terminal IN_P, IN_N, for converting the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal IN_P, IN_N, including a second differential output terminal OUT_P, OUT_N, for converting the differential signal into a differential output voltage; wherein, the single-slip differential drive enhancement circuit includes a transmission gate Tran and an inverter chain for generating the differential signal with a phase difference of 180° and timing matching.

[0031] In some embodiments, the single-slip drive enhancement circuit further includes a first buffer BUF1 and a phase-locked module. The inverter includes a first inverter INV1 and a second inverter INV2. The input terminal of the first buffer BUF1 is connected to the single-ended digital input terminal IN, the output terminal of the first buffer BUF1 is connected to the input terminal of the first inverter INV1, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and the input terminal of the transmission gate Tran, respectively. The phase-locked module is connected between the output terminal of the second inverter INV2 and the output terminal of the transmission gate Tran and has the first differential output terminals IN_P and IN_N.

[0032] In some embodiments, the phase-locked module includes a third inverter INV3 and a fourth inverter INV4; the input terminal of the third inverter INV3 is connected to the first terminal IN_P of the first differential output terminal IN_P,IN_N, and its output terminal is connected to the second terminal IN_N of the first differential output terminal IN_P,IN_N; the input terminal of the fourth inverter INV4 is connected to the second terminal IN_N of the first differential output terminal IN_P,IN_N, and its output terminal is connected to the first terminal IN_P of the first differential output terminal IN_P,IN_N.

[0033] In some embodiments, the single-slip drive enhancement circuit further includes a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, and a fifth buffer BUF5; the output terminal of the second inverter INV2 is connected to the input terminal of the second buffer BUF2, the output terminal of the second buffer BUF2 is connected to the input terminal of the third inverter INV3, the output terminal of the fourth inverter INV4, and the input terminal of the fourth buffer BUF4, respectively, and the output terminal of the fourth buffer BUF4 is connected to the first terminal IN_P; the output terminal of the transmission gate Tran is connected to the input terminal of the third buffer BUF3, the output terminal of the third buffer BUF3 is connected to the output terminal of the third inverter INV3, the input terminal of the fourth inverter INV4, and the input terminal of the fifth buffer BUF5, and the output terminal of the fifth buffer BUF5 is connected to the second terminal IN_N.

[0034] In some embodiments, the differential driving circuit includes: an output stage, comprising a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are interconnected, and the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are interconnected. The gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the first terminal IN_P, and the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the second terminal IN_N. The drain of the first PMOS transistor MP1 and the first NMOS transistor MN2 are connected to the second terminal IN_N. The drain of S-MOSFET MN1 is connected to the third terminal OUT_N of the second differential output terminal OUT_P,OUT_N. The drains of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the fourth terminal OUT_P of the second differential output terminal OUT_P,OUT_N. A common-mode feedback module, connected to the second differential output terminal OUT_P,OUT_N, is used to sample the common-mode voltage and compare it with the reference voltage VREF to generate a feedback control signal. A bias module is used to provide bias current. The feedback control signal output by the common-mode feedback module regulates the current flowing through the output stage to stabilize the common-mode voltage of the second differential output terminal OUT_P,OUT_N.

[0035] In some embodiments, the common-mode feedback module includes: a first resistor R1 and a second resistor R2, connected in series between the third terminal OUT_N and the fourth terminal OUT_P, the midpoint of which generates a sampling voltage VCM representing the common-mode voltage; an operational amplifier AMP1, the non-inverting input of which is connected to the sampling point of the sampling voltage VCM, and the inverting input of which receives the reference voltage VREF; and a third PMOS transistor MP3, the gate of which is connected to the output of the operational amplifier AMP1 to receive the feedback control signal, the source of which is connected to the power supply, and the drain of which is connected to the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2.

[0036] In some embodiments, the bias module includes: a bias current source IBIAS; a third NMOS transistor MN3 and a fourth NMOS transistor MN4 forming a current mirror; the gate and drain of the third NMOS transistor MN3 are connected to the bias current source IBIAS, and its source is grounded; the gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3, its source is grounded, and its drain is connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2.

[0037] In some embodiments, a load resistor Rload is connected between the second differential output terminals OUT_P and OUT_N.

[0038] In some embodiments, this application provides a chip that includes the differential emitter circuit described in the above embodiments.

[0039] In some embodiments, this application provides an electronic device that includes the differential transmission circuit described in the above embodiments.

[0040] In some embodiments, this application provides a working principle of a differential transmitter circuit, specifically including: (1) As Figure 1 As shown, the single-slip drive enhancement circuit has the core function of converting the input single-ended digital signal into a pair of differential signals with strong driving capability and precise timing complementarity, and ensuring that their phase difference is stable at 180°.

[0041] The input signal is first pre-shaped by buffer BUF1. Then, the signal path splits into two: Path 1 (the basic path for generating IN_P): consisting of two inverting stages, INV1 and INV2, whose output signal has the same phase as the input signal; Path 2 (generating IN_N and balancing timing): Tran is controlled by the output of INV1, and its key function is to generate a parallel path to Path 1, aiming to generate a signal that is inverted by the output of INV2 and whose transmission delay is matched as closely as possible. This is the core design for achieving low timing skew.

[0042] INV3 and INV4 are cross-coupled, forming a latching or logic-enhanced structure to ensure that the phase difference between the two signals is precisely locked at 180° before entering the final driver stage. Finally, high-quality differential signals are output through buffers BUF4 and BUF5, which are identical in size and drive capability. Throughout the path, the drive capability of the devices is designed to increase progressively to ensure rapid charging and discharging of the input capacitors of subsequent differential driver circuits.

[0043] (2) Figure 2 As shown, the differential drive circuit is responsible for converting the differential digital signal generated by the previous stage into a differential output voltage with a stable common-mode level.

[0044] The differential pair transistors (MP1 / MN1 and MP2 / MN2) constitute a current switch. Their operating state is controlled by IN_P and IN_N: when IN_P is high and IN_N is low, MP2 and MN1 are turned on, and current flows through MP2, the load resistor Rload (usually located at the receiving end), and MN1, making VOUT_P > VOUT_N; when IN_P is low and IN_N is high, MP1 and MN2 are turned on, changing the current path, making VOUT_N > VOUT_P.

[0045] The output current amplitude can be controlled by adjusting the bias current IBIAS, thereby dynamically adjusting power consumption. Transistors MN3 and MN4 form a current mirror to accurately replicate the bias current IBIAS.

[0046] Resistors R1 and R2 are connected in series at the output, and their midpoint voltage VCM accurately reflects the common-mode voltage of the output signal. Operational amplifier AMP1 forms an error amplifier, with its non-inverting input connected to VCM and its inverting input connected to a stable reference voltage VREF. The output of AMP1 controls the gate of PMOS transistor MP3. This forms a highly efficient negative feedback loop: if the output common-mode voltage VCM deviates from VREF due to power supply noise, temperature changes, or load variations, AMP1 immediately detects the error and adjusts the gate voltage of MP3, thereby changing the current flowing through the output stage and strongly pulling VCM back and stabilizing it at the VREF value. This mechanism greatly improves the output's common-mode noise rejection ratio (CMRR) and overall stability.

[0047] Key point 1: High-precision, fast-response single-ended to differential conversion mechanism: 1-1 Precise Phase Control: The core lies in constructing two parallel paths using a transmission gate (Tran) and an inverter chain (INV1, INV2). The key function of the transmission gate is to generate a signal that is inverted from the output of INV2 and to perform precise timing matching with the INV2 path, ensuring that the 180-degree phase difference between the differential signals IN_P and IN_N is precise and stable. This reduces timing errors and signal distortion at the source, laying the foundation for high-speed transmission.

[0048] 1-2 Gradually Increased Driving Capability: Through a multi-stage buffer / inverter design from BUF1 to BUF5, the driving capability of each stage is carefully designed to increase progressively (driving capability: BUF1 < BUF2 = BUF3 < BUF4 = BUF5). This not only ensures signal integrity but also significantly enhances the driving capability for subsequent circuits, thereby ensuring the ability to quickly and effectively switch the states of subsequent power transistors (MP1, MP2, MN1, MN2).

[0049] Key Point 2: High stability and strong anti-interference differential drive circuit with common-mode feedback: 2-1 Intelligent Current Direction and Low-Voltage Swing Output: The output stage consists of MP1 / MP2 and MN1 / MN2, which can precisely control the switching of the current path according to the input differential signals IN_P and IN_N. By reducing the load resistance Rload to lower the amplitude of the output differential voltage, the signal swing can be effectively reduced, thereby significantly improving the circuit's response speed.

[0050] 2-2 Dynamic Bias and Power Consumption Optimization: The circuit mirrors the bias current through MN3 and MN4. This structure allows for dynamic adjustment of the output stage current based on actual operating conditions. This helps avoid unnecessary quiescent current waste and achieves effective control over circuit power consumption.

[0051] 2-3 Active Monitoring and Stabilization of Common-Mode Voltage: The common-mode negative feedback loop consists of resistors R1, R2, AMP1, and MP3. Resistors R1 and R2 monitor the output common-mode voltage VCM in real time. Operational amplifier AMP1 compares this voltage with a stable reference voltage VREF and feeds the error signal back to the gate of common-source transistor MP3. This closed-loop system automatically adjusts the current of MP3, thereby overcoming the effects of power supply fluctuations, temperature changes, and other factors, strongly stabilizing the output common-mode voltage at VREF, greatly improving the common-mode rejection ratio (CMRR) and the overall system's anti-interference capability.

[0052] Key Point 3: In-Chip Integration and System-Level Optimization The entire circuit (including single-slip drive and differential drive) is fully integrated on a single chip. This fully integrated solution reduces reliance on external discrete components, which not only lowers packaging costs and size but also avoids parasitic parameters and uncertainties introduced by external connections, thereby significantly improving system reliability and performance consistency.

[0053] In summary, the fully integrated on-chip differential transmitter circuit of this invention achieves precise and fast single-ended to differential conversion through a single-switching differential drive enhancement circuit, and ensures output stability and anti-interference through a differential drive circuit with common-mode feedback. This collaborative design effectively solves the shortcomings of traditional LVDS transmitter circuits in terms of response speed, common-mode stability, and power consumption, and is therefore particularly suitable for applications requiring high speed, low power consumption, and high anti-interference.

[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A differential transmitter circuit, characterized in that, include: A single-slip drive enhancement circuit includes a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; A differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), includes a second differential output terminal (OUT_P, OUT_N), used to convert the differential signal into a differential output voltage; The single-slip drive enhancement circuit includes a transmission gate (Tran) and an inverter chain to generate the differential signal with a phase difference of 180° and timing matching.

2. The differential transmitter circuit according to claim 1, characterized in that, The single-slip drive enhancement circuit also includes a first buffer (BUF1) and a phase-locked module, and the inverter includes a first inverter (INV1) and a second inverter (INV2); The input terminal of the first buffer (BUF1) is connected to the single-ended digital input terminal (IN), the output terminal of the first buffer (BUF1) is connected to the input terminal of the first inverter (INV1), and the output terminal of the first inverter (INV1) is connected to the input terminal of the second inverter (INV2) and the input terminal of the transmission gate (Tran). The phase-locked module is connected between the output of the second inverter (INV2) and the output of the transmission gate (Tran) and has the first differential output (IN_P, IN_N).

3. The differential transmitter circuit according to claim 2, characterized in that, The phase-locked module includes a third inverter (INV3) and a fourth inverter (INV4); The input terminal of the third inverter (INV3) is connected to the first terminal (IN_P) of the first differential output terminal (IN_P,IN_N), and its output terminal is connected to the second terminal (IN_N) of the first differential output terminal (IN_P,IN_N). The input terminal of the fourth inverter (INV4) is connected to the second terminal (IN_N) of the first differential output terminal (IN_P,IN_N), and its output terminal is connected to the first terminal (IN_P) of the first differential output terminal (IN_P,IN_N).

4. The differential transmitter circuit according to claim 3, characterized in that, The single-slip drive enhancement circuit also includes a second buffer (BUF2), a third buffer (BUF3), a fourth buffer (BUF4), and a fifth buffer (BUF5); The output of the second inverter (INV2) is connected to the input of the second buffer (BUF2). The output of the second buffer (BUF2) is connected to the input of the third inverter (INV3), the output of the fourth inverter (INV4), and the input of the fourth buffer (BUF4). The output of the fourth buffer (BUF4) is connected to the first terminal (IN_P). The output of the transmission gate (Tran) is connected to the input of the third buffer (BUF3). The output of the third buffer (BUF3) is connected to the output of the third inverter (INV3), the input of the fourth inverter (INV4), and the input of the fifth buffer (BUF5). The output of the fifth buffer (BUF5) is connected to the second terminal (IN_N).

5. The differential transmitter circuit according to claim 1, characterized in that, The differential driving circuit includes: The output stage includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), and a second NMOS transistor (MN2). The sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are interconnected, and the sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are interconnected. The gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are connected to the first terminal (IN_P), and the gates of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are connected to the second terminal (IN_N). The drains of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are connected to the third terminal (OUT_N) of the second differential output terminal (OUT_P, OUT_N), and the drains of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are connected to the fourth terminal (OUT_P) of the second differential output terminal (OUT_P, OUT_N). The common-mode feedback module is connected to the second differential output terminal (OUT_P, OUT_N) and is used to sample the common-mode voltage and compare it with the reference voltage (VREF) to generate a feedback control signal. The bias module is used to provide bias current; The feedback control signal output by the common-mode feedback module regulates the current flowing through the output stage to stabilize the common-mode voltage of the second differential output terminal (OUT_P, OUT_N).

6. The differential transmitter circuit according to claim 5, characterized in that, The common-mode feedback module includes: The first resistor (R1) and the second resistor (R2) are connected in series between the third terminal (OUT_N) and the fourth terminal (OUT_P), and the midpoint generates a sampling voltage (VCM) representing the common-mode voltage. An operational amplifier (AMP1) has its non-inverting input connected to the sampling point of the sampling voltage (VCM) and its inverting input receiving the reference voltage (VREF). The third PMOS transistor (MP3) has its gate connected to the output of the operational amplifier (AMP1) to receive the feedback control signal, its source connected to the power supply, and its drain connected to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2).

7. The differential transmitter circuit according to claim 5, characterized in that, The bias module includes: Bias current source (IBIAS); The third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) form a current mirror; The gate and drain of the third NMOS transistor (MN3) are connected to the bias current source (IBIAS), and its source is grounded. The gate of the fourth NMOS transistor (MN4) is connected to the gate of the third NMOS transistor (MN3), its source is grounded, and its drain is connected to the source of the first NMOS transistor (MN1) and the second NMOS transistor (MN2).

8. The differential transmitter circuit according to claim 5, characterized in that, A load resistor (Rload) is connected between the second differential output terminals (OUT_P, OUT_N).

9. A chip, characterized in that, Includes the differential transmitter circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the differential transmitter circuit as described in any one of claims 1 to 8.

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