Crosstalk suppression module and control method thereof, display panel and display device

Abstract

The application discloses a crosstalk suppression module and a control method thereof, a display panel and a display device, and relates to the technical field of display. The crosstalk suppression module is provided with a gate drive circuit integrating gate scanning units at all levels, and a replacement circuit connected between a direct-current high-voltage signal line and a first passage end of a pre-charging transistor in the gate scanning unit. When the direct-current high-voltage signal line is normal, the pre-charging transistor is enabled to be connected to a pre-charging voltage provided by the direct-current high-voltage signal line under the drive of a front-stage scanning signal to pre-charge the first node, so that an output transistor is turned on and a current-stage scanning signal is output. When the direct-current high-voltage signal line is invalid, the pre-charging transistor is enabled to provide a pre-charging replacement voltage of the replacement circuit to the first node under the drive of the front-stage scanning signal, so that the output transistor is normally turned on. The application aims to improve the fault tolerance of the gate drive circuit to the invalid direct-current high-voltage signal line to improve the uniformity of picture display.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a crosstalk suppression module and its control method, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has become dominant in display applications due to its advantages such as high image quality, low cost, and high reliability. In large-size display panels, dual GOA (Gate Driver on Array) circuits are often used for driving, that is, GOA circuits are set on both sides of the display panel.

[0003] In the GOA circuit (also known as the gate drive circuit), the VDS signal line, as a critical DC high-voltage signal line, is responsible for providing the pre-charge voltage to each stage of the gate scanning unit. However, during the actual manufacturing and use of the display panel, the VDS signal line may fail due to process defects, electrostatic breakdown, or long-term aging. Research has found that when a single-sided VDS signal line fails, the display panel exhibits significant longitudinal crosstalk. Specifically, when the display panel displays a test image with a bright central area and a surrounding background area, a single-sided VDS signal line failure will cause the corresponding row on the failed side to appear as dark stripes due to the loss of the scanning signal. At the same time, the increased waveform noise leads to an increase in the leakage current of the TFT (Thin Film Transistor), causing leakage from the bright central area to the dark stripe area. This results in an abnormally high overall brightness in the vertical direction of the bright central area, making it significantly brighter than the left and right sides, thus creating longitudinal crosstalk.

[0004] Therefore, improving the fault tolerance of the gate drive circuit to the failure of the DC high voltage signal line in order to improve the uniformity of the screen display is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a crosstalk suppression module and its control method, a display panel, and a display device, which aim to improve the fault tolerance of the GOA circuit to the failure of the VDS signal line and thus improve the display quality.

[0006] To achieve the above objectives, this application provides a crosstalk suppression module, the crosstalk suppression module comprising:

[0007] A gate driving circuit includes a multi-stage gate scanning unit. Each gate scanning unit includes a pre-charge transistor, an output transistor, and a first node. The gate of the pre-charge transistor is connected to the previous stage scanning signal output by the previous stage gate scanning unit. The first path terminal of the pre-charge transistor is electrically connected to a preset DC high-voltage signal line. The second path terminal of the pre-charge transistor and the gate of the output transistor are electrically connected to the first node. The first path terminal of the output transistor is connected to a preset clock terminal. The second path terminal of the output transistor is the scan output terminal of this stage. This stage gate scanning unit can be any one of the multiple gate scanning units.

[0008] The gate scanning unit of this stage is configured to enable the pre-charge transistor to pre-charge the first node by connecting to the pre-charge voltage provided by the DC high-voltage signal line under the drive of the previous stage scanning signal when the DC high-voltage signal line is normal, so that the output transistor is turned on and outputs the scanning signal of this stage.

[0009] A backup circuit is connected between the DC high-voltage signal line and the first path terminal of the precharge transistor. The backup circuit is configured to enable the precharge transistor to provide the backup voltage of the backup circuit to the first node under the drive of the previous stage scan signal when the DC high-voltage signal line fails, so as to maintain the normal conduction of the output transistor.

[0010] In one embodiment, the substitute circuit includes a first transistor and a second transistor;

[0011] The gate of the first transistor is electrically connected to the DC high-voltage signal line, the first path terminal of the first transistor is electrically connected to a preset high-voltage signal source, and the second path terminal of the first transistor is electrically connected to the first path terminal of the second transistor.

[0012] The gate of the second transistor is electrically connected to the gate of the precharge transistor, and the second path terminal of the second transistor is electrically connected to the first node.

[0013] In one embodiment, the substitute circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0014] The gate of the third transistor, the first path terminal of the third transistor, and the gate of the fifth transistor are respectively electrically connected to a preset high-voltage signal source. The second path terminal of the third transistor is respectively electrically connected to the first path terminal of the fourth transistor and the first path terminal of the fifth transistor. The second path terminal of the fifth transistor is electrically connected to the first path terminal of the sixth transistor.

[0015] The gate of the fourth transistor is electrically connected to the DC high-voltage signal line, the second path terminal of the fourth transistor is electrically connected to a preset low potential terminal, the gate of the sixth transistor is connected to the pre-stage scanning signal, and the second path terminal of the sixth transistor is connected between the first node and the gate of the output transistor.

[0016] In one embodiment, the crosstalk suppression module includes a detection transistor;

[0017] The gate of the detection transistor is electrically connected to the DC high-voltage signal line, the first path terminal of the detection transistor is electrically connected to the connection line from the driver chip to the DC high-voltage signal line, and the second path terminal of the detection transistor is electrically connected to the high-voltage signal source.

[0018] In one embodiment, the substitute circuit includes a seventh transistor;

[0019] The gate of the seventh transistor and the first path terminal of the seventh transistor are electrically connected to the DC high voltage signal line, and the second path terminal of the seventh transistor is electrically connected to the gate of the precharge transistor.

[0020] Furthermore, this application also provides a control method for a crosstalk suppression module, the control method being applied to the crosstalk suppression module described above, the control method comprising:

[0021] When the preset DC high-voltage signal line is normal, the pre-charge transistor of the current gate scan unit is triggered under the drive of the previous stage scan signal of the previous stage gate scan unit. The pre-charge voltage provided by the DC high-voltage signal line is used to pre-charge the first node of the current gate scan unit, so that the output transistor of the current gate scan unit is turned on and outputs the current stage scan signal; and / or,

[0022] When the DC high-voltage signal line fails, the precharge transistor is enabled to provide the precharge backup voltage of the backup circuit to the first node under the drive of the front-stage scan signal, so as to maintain the normal conduction of the output transistor.

[0023] In one embodiment, the control method includes:

[0024] The operating level of the DC high-voltage signal line is detected by the detection transistor in the crosstalk suppression module.

[0025] When the operating level is low, it is determined that the DC high-voltage signal line is faulty;

[0026] When the operating level is high, it is determined that the DC high voltage signal line is normal.

[0027] In one embodiment, the step of detecting the operating level of the DC high-voltage signal line by the detection transistor in the crosstalk suppression module includes:

[0028] When the detection transistor in the crosstalk suppression module is turned on under the drive of the precharge voltage, the operating level of the DC high voltage signal line is determined to be low based on the turned-on detection transistor.

[0029] When the detection transistor in the crosstalk suppression module remains off under the drive of the precharge voltage, the operating level of the DC high voltage signal line is determined to be high based on the off detection transistor.

[0030] In addition, this application also provides a display panel, the display panel including: a display area; a non-display area, the non-display area including a DC high-voltage signal line and the crosstalk suppression module mentioned above, the gate driving circuits in the crosstalk suppression module being disposed on both sides of the display area, one DC high-voltage signal line corresponding to one gate driving circuit, and each DC high-voltage signal line providing a pre-charge voltage for each stage of the gate scanning unit in the corresponding gate driving circuit.

[0031] In addition, this application also provides a display device, the display device including the display panel described above; and / or, a memory, a processor and a computer program stored in the memory and executable on the processor, the computer program implementing the steps of the control method for the crosstalk suppression module as described above when executed by the processor.

[0032] This application significantly improves the fault tolerance capability of display devices with integrated crosstalk suppression modules (including gate drive circuits and backup circuits) to DC high-voltage signal line failures, thereby ensuring display uniformity in high-contrast scenes. Specifically, the gate drive circuit includes multi-stage gate scanning units. In each stage of the gate scanning unit (i.e., any stage in the multi-stage gate scanning unit), the gate of the pre-charge transistor is connected to the previous stage scanning signal output from the previous stage gate scanning unit. The first path terminal of the pre-charge transistor is electrically connected to a preset DC high-voltage signal line. The second path terminal of the pre-charge transistor and the gate of the output transistor are electrically connected to a first node. The first path terminal of the output transistor is connected to a preset clock terminal, and the second path terminal of the output transistor is the output terminal of this stage of scanning. When the DC high-voltage signal line is normal, the pre-charge transistor, driven by the previous stage scanning signal, receives the pre-charge voltage provided by the DC high-voltage signal line to pre-charge the first node, thereby turning on the output transistor and outputting the current stage scanning signal, realizing normal horizontal scanning drive of this stage of gate scanning unit. When the DC high-voltage signal line fails, by setting a connection between the DC high-voltage signal line and the pre-charge transistor… The backup circuit between the first path terminals of the transistor enables the pre-charge transistor to provide the backup voltage of the backup circuit to the first node under the drive of the previous stage scan signal, so as to maintain the normal conduction of the output transistor. Since the introduction of the backup voltage does not depend on the failed DC high voltage signal line, and the drive of the pre-charge transistor is still controlled by the previous stage scan signal, the gate scan unit of this stage can still maintain normal scan output after the failure of the DC high voltage signal line. This avoids the dark stripes caused by the loss of the scan signal in the pixel row corresponding to the gate scan unit of this stage. At the same time, the problem of increased TFT leakage current caused by increased waveform noise is also eliminated. It fundamentally blocks the leakage path from the middle bright area to the dark stripe area, effectively suppresses the occurrence of longitudinal crosstalk, significantly improves the fault tolerance capability of the display device to the failure of the DC high voltage signal line, and ensures that the display device can still present a uniform display effect under high contrast dynamic picture. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the longitudinal crosstalk involved in the embodiments of this application;

[0036] Figure 2 This is a structural block diagram of the first embodiment of the crosstalk suppression module of this application;

[0037] Figure 3 This is a schematic diagram of the gate scanning unit involved in the embodiments of this application;

[0038] Figure 4 This is a schematic diagram of a substitute circuit involved in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of the detection circuit involved in the embodiment of this application;

[0040] Figure 6 This is a schematic diagram of another substitute circuit involved in the embodiments of this application;

[0041] Figure 7 This is a schematic diagram comparing the signal waveforms of the DC high-voltage signal line and the high-voltage signal source signal before and after VDS failure in the embodiments of this application.

[0042] Figure 8 This is a schematic diagram of another alternative circuit involved in the embodiments of this application;

[0043] Figure 9 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0044] Explanation of icon numbers:

[0045] 10. Gate drive circuit; 11. Gate scan unit; TA, precharge transistor; TB, output transistor; TC, reset transistor; TD, pull-down transistor; C1, storage capacitor; VGL, low potential terminal; Q, first node; 20. Replacement circuit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; VDS, DC high voltage signal line; A, high voltage signal source; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory.

[0046] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0049] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0051] TFT-LCD (Thin Film Transistor Liquid Crystal Display) dominates high-end applications such as televisions, monitors, and automotive displays due to its advantages of high image quality, low cost, and high reliability. In TFT-LCD display panels, crosstalk refers to the phenomenon where a small, unusual image on a simple background causes brightness variations in adjacent horizontal or vertical areas. However, during the actual manufacturing and use of display panels, the VDS signal line may fail due to process defects, electrostatic discharge, or long-term aging, easily leading to vertical crosstalk on the display panel surface, severely affecting display quality.

[0052] Currently, the industry commonly uses conventional GOA circuits to drive display panels. The VDS signal line, as a critical DC high-voltage signal line, is responsible for providing pre-charge voltage to each stage of the gate scanning unit. However, this traditional circuit architecture does not fully account for the failure scenario of a single-sided VDS signal line. In other words, the technology of using existing GOA circuits to drive display panels has the following technical defects.

[0053] On the one hand, when a single VDS signal line fails, the gate scanning units connected to that side cannot obtain the pre-charge voltage, resulting in the loss of the scanning signal for the corresponding row, and the pixels in that row cannot be displayed normally. Figure 1 Taking the crosstalk test image shown in (a) as an example, when the display panel presents a test image with a bright white state in the middle (corresponding to L255 grayscale) and a surrounding background area (corresponding to L127 grayscale), a single-sided VDS failure will cause the corresponding row on the failed side to appear as dark stripes due to the loss of scan signal, and will also present... Figure 1 The alternating bright and dark phenomenon shown in (b) – for example, when the left side fails, odd-numbered rows are dark and even-numbered rows are bright, severely affecting display integrity. On the other hand, when a single-sided VDS signal line fails, the gate scanning units connected to that side lose their pre-charge voltage, resulting in the loss of scanning signals. The pixel transistor gates of the corresponding rows lose normal switching control and are in an unstable floating state. At this time, the reflection and impedance discontinuity caused by the broken signal line in the GOA circuit will couple significant waveform noise onto the floating scan lines through parasitic capacitance. The amplitude of this noise instantaneously exceeds the threshold voltage of the pixel transistor, causing the pixel transistors that should be turned off to frequently enter the subthreshold conduction region. In the crosstalk test screen, the pixel electrodes in the middle bright area (L255 grayscale) store high voltage, while the pixel voltage in the dark ripple row (L0 grayscale) on the failed side is extremely low. The high potential difference between the two drives the charge to slowly leak from the bright area pixels to the dark area pixels through the micro-conducting pixel transistor channels. Because of the continuous loss of scanning signals, this leakage accumulates in each frame, causing the actual brightness of the L0 area, which should display pure black, to abnormally increase. Meanwhile, the central L255 area brightens vertically due to the adjacent dark lines, making the overall average brightness perceived by the human eye as significantly higher than the normal areas on the left and right sides (where the dark lines remain at their original brightness). This ultimately forms a vertical crosstalk bright band that runs through the entire screen. In other words, improving the fault tolerance of the gate drive circuit to the failure of the DC high-voltage signal line to enhance the uniformity of the image display is a pressing technical problem that needs to be solved.

[0054] To address the aforementioned technical deficiencies, this application provides a crosstalk suppression module and its control method, a display panel, and a display device.

[0055] This application provides a crosstalk suppression module, referring to... Figure 1 As shown, Figure 1 This is a structural block diagram of the first embodiment of the crosstalk suppression module of this application. The crosstalk suppression module provided in this application includes:

[0056] A gate driving circuit 10 includes a multi-stage gate scanning unit 11. Each gate scanning unit includes a pre-charge transistor TA, an output transistor TB, and a first node Q. The gate of the pre-charge transistor TA is connected to the previous stage scanning signal output by the previous stage gate scanning unit 11. The first path terminal of the pre-charge transistor TA is electrically connected to a preset DC high-voltage signal line VDS. The second path terminal of the pre-charge transistor TA and the gate of the output transistor TB are electrically connected to the first node Q. The first path terminal of the output transistor TB is connected to a preset clock terminal. The second path terminal of the output transistor TB is the scan output terminal of this stage. The gate scanning unit of this stage can be any one of the multiple gate scanning units 11.

[0057] In this embodiment, a gate driving circuit 10 is provided in the non-display area of ​​the display panel. The gate driving circuit 10 is distributed on both sides of the display area of ​​the display panel, realizing high-reliability line scanning drive for the large-size display panel, providing a basic guarantee for the normal image display of the display panel, and also providing a necessary circuit platform for the fault-tolerant design of the subsequent backup circuit 20. This allows the backup circuit 20 to be independently configured for the gate driving circuit 10 on the corresponding side. Thus, when a single-sided DC high-voltage signal line VDS fails, only the DC high-voltage signal line VDS on the failed side needs to be replaced and repaired, without affecting the normal operation of the DC high-voltage signal line VDS on the other side. This significantly improves the fault tolerance capability of the display panel for local faults and the overall display uniformity.

[0058] It should be noted that the gate driving circuit 10 refers to a circuit structure in which the scanning driving circuit is directly fabricated on the array substrate of the display panel using GOA technology. The gate driving circuit 10 includes multiple cascaded gate scanning units 11, each of which drives one row of pixels on the display panel. By transmitting scanning signals step by step, the row scanning driving of the entire display panel is completed.

[0059] The gate scanning unit 11 is configured to enable the pre-charge transistor TA to pre-charge the first node Q by connecting to the pre-charge voltage provided by the DC high-voltage signal line VDS under the drive of the previous stage scanning signal when the DC high-voltage signal line VDS is normal, so that the output transistor TB is turned on and outputs the current stage scanning signal.

[0060] In this embodiment, refer to Figure 2Since the gate drive circuit 10 in the crosstalk suppression module includes a multi-level gate scan unit 11; the gate scan unit of this level, as the basic component of the gate drive circuit 10, includes at least a pre-charge transistor TA, an output transistor TB and a first node Q. Specifically, by connecting the gate of the precharge transistor TA to the pre-stage scan signal output by the previous stage gate scan unit 11, electrically connecting the first path terminal of the precharge transistor TA to a preset DC high-voltage signal line VDS, and electrically connecting the second path terminal of the precharge transistor TA and the gate of the output transistor TB to the first node Q, and simultaneously connecting the first path terminal of the output transistor TB to a preset clock terminal, and using the second path terminal of the output transistor TB as the scan output terminal of this stage, a complete row scan driving structure is constructed. This allows the current stage gate scan unit to respond to the triggering of the previous stage scan signal when the DC high-voltage signal line VDS is normal, using the precharge voltage provided by the DC high-voltage signal line VDS to precharge the first node Q, thereby controlling the output transistor TB to conduct and transmitting the periodic clock signal CK provided by the clock terminal to the scan output terminal of this stage. The resulting scan signal of this stage achieves precise driving of a row of pixels. At the same time, the first path terminal of the precharge transistor TA serves as a clear intervention point, providing a structural basis for the subsequent backup circuit 20 to be connected in parallel, enabling the backup circuit 20 to achieve functional replacement in the fault state without changing the basic architecture of the original circuit.

[0061] It should be noted that the current gate scan unit refers to any one level of gate scan unit 11 in the multi-level gate scan unit 11, and each level of gate scan unit 11 corresponds to driving one row of pixels on the display panel. The previous level scan signal refers to the scan signal output by the previous level gate scan unit 11 of the current level gate scan unit, which serves as the input trigger signal of the current level gate scan unit and is used to control the turn-on timing of the pre-charge transistor TA in the current level gate scan unit.

[0062] The local scan signal refers to the signal driving waveform formed by transmitting the periodic clock signal CK input from the clock terminal to the local scan output terminal through the turned-on output transistor TB in the local gate scan unit. This local scan signal Gn can control the conduction of the nth row pixel to write the grayscale voltage, and at the same time, it serves as the pre-stage scan signal for the next stage gate scan unit 11, used to trigger the conduction of the pre-charge transistor TA in the next stage gate scan unit 11.

[0063] The precharge transistor TA is a thin-film transistor controlled by the preceding scan signal. It is used to precharge the first node Q before the scan begins, raising the potential of the first node Q to a level sufficient to turn on the output transistor TB. This precharge transistor TA can be an N-type thin-film transistor or an N-type MOSFET.

[0064] The output transistor TB refers to a thin-film transistor controlled by the Q potential of the first node. It is used to transmit the clock signal to the scan output terminal of this stage after pre-charging is completed, generating the final scan signal. This output transistor TB can be an N-type thin-film transistor or an N-type MOSFET.

[0065] The first node Q refers to the key control node inside the gate scan unit 11. The potential of the first node Q directly determines the conduction state of the output transistor TB and is the intermediate node connecting the precharge transistor TA and the output transistor TB.

[0066] For example, the gate scan unit 11 may include Figure 3The precharge transistor TA, output transistor TB, reset transistor TC, pull-down transistor TD, and storage capacitor C1 are shown. In this circuit, the gate of the precharge transistor TA is connected to the previous stage scan signal output by the gate scan unit 11. The first path terminal of the precharge transistor TA is electrically connected to the DC high-voltage signal line VDS, and the second path terminal of the precharge transistor TA is electrically connected to the first node Q. The precharge transistor TA is turned on under the drive of the previous stage scan signal, and the precharge voltage provided by the DC high-voltage signal line VDS is transmitted to the first node Q through the turned-on precharge transistor TA. The gate of the output transistor TB is electrically connected to the first node Q. The first path terminal of the output transistor TB is electrically connected to the clock terminal, and the second path terminal of the output transistor TB is the scan output terminal of this stage. The output transistor TB is turned on after the potential of the first node Q rises, and the clock signal is transmitted to the scan output terminal of this stage to generate the scan signal of this stage. The gate of the reset transistor TC is connected to the scan signal output by the next stage gate scan unit 11. The first path terminal of the reset transistor TC is electrically connected to the first node Q, and the second path terminal of the reset transistor TC is electrically connected to the low potential terminal VGL. The reset transistor TC switches from the cutoff state to the on state when it receives the scan signal output by the next stage gate scan unit 11, so that the on-state can transmit the precharge voltage provided by the turned-on reset transistor TC. C resets the first node Q to a low potential; the gate of the pull-down transistor TD is connected to the scan signal output by the next-stage gate scan unit 11. The first path terminal of the pull-down transistor TD is electrically connected to the scan output terminal of this stage, and the second path terminal of the pull-down transistor TD is electrically connected to the low potential terminal VGL. When the pull-down transistor TD is connected to the scan signal output by the next-stage gate scan unit 11, it marks the end of the scan output cycle of this stage and the beginning of the discharge reset phase. It is used to pull the scan output terminal of this stage from a high potential to a low potential to ensure that the scan signal is turned off in time after completing the driving of the pixels in this row, avoiding damage caused by scanning. The continuous high level of the signal can prevent pixel miswriting or charge leakage, while preparing for the scan drive of the next frame. One end of the storage capacitor C1 is electrically connected to the first node Q, and the other end of the storage capacitor C1 is electrically connected to the second path terminal of the output transistor TB. When the output transistor TB is turned on and transmits the clock signal to the scan output terminal of this stage, the potential jump of the scan output terminal of this stage is coupled to the first node Q through the storage capacitor C1, so that the potential of the first node Q is further raised to enhance the driving capability of the output transistor TB and maintain the conduction state of the output transistor TB, ensuring the complete output of the scan signal of this stage.

[0067] A backup circuit 20 is connected between the DC high-voltage signal line VDS and the first path terminal of the precharge transistor TA. The backup circuit 20 is configured to enable the precharge transistor TA to provide the precharge backup voltage of the backup circuit 20 to the first node Q under the drive of the previous stage scan signal when the DC high-voltage signal line VDS fails, so as to maintain the normal conduction of the output transistor TB.

[0068] In this embodiment, a gate drive architecture with fault tolerance is constructed by connecting a substitute circuit 20 in parallel between the DC high-voltage signal line VDS and the first path terminal of the pre-charge transistor TA. The substitute circuit 20 is configured to be in standby mode when the DC high-voltage signal line VDS is normal, without affecting the normal operation of the original circuit; however, when the DC high-voltage signal line VDS fails, the substitute circuit 20 is automatically activated, enabling the pre-charge transistor TA to provide the pre-charge substitute voltage of the substitute circuit 20 to the first node Q under the drive of the preceding scan signal, thereby maintaining the normal conduction of the output transistor TB and the continuous output of the scan signal. This design fundamentally solves the problem of scan signal loss caused by VDS failure, blocks the subsequent rise in TFT leakage current and the longitudinal charge migration path caused by scan signal loss, avoids leakage from the bright area to the dark area, effectively suppresses the occurrence of longitudinal crosstalk, significantly improves the fault tolerance capability of the gate drive circuit 10 to the failure of the DC high-voltage signal line VDS, and ensures the display uniformity of the display panel under high-contrast dynamic images.

[0069] Furthermore, in some other feasible embodiments, reference is made to... Figure 4 The substitute circuit 20 includes a first transistor T1 and a second transistor T2; the gate of the first transistor T1 is electrically connected to the DC high-voltage signal line VDS, the first path terminal of the first transistor T1 is electrically connected to a preset high-voltage signal source A, and the second path terminal of the first transistor T1 is electrically connected to the first path terminal of the second transistor T2; the gate of the second transistor T2 is electrically connected to the gate of the pre-charge transistor TA, and the second path terminal of the second transistor T2 is electrically connected to the first node Q.

[0070] In this embodiment, by setting up a substitute circuit 20 including a first transistor T1 and a second transistor T2, accurate detection and automatic replacement of the failure of the DC high-voltage signal line VDS are achieved. Specifically, the gate of the first transistor T1 is directly connected to the DC high-voltage signal line VDS, making the first transistor T1 a real-time sensing element for the DC high-voltage signal line VDS. That is, when the DC high-voltage signal line VDS is normal, the first transistor T1 remains in the off state due to the high level connected to its gate, thereby isolating the substitute circuit 20 from the main circuit and not affecting the normal operation of the original circuit; while when the DC high-voltage signal line VDS fails and is at a low level, the first transistor T1 is automatically turned on due to the low level connected to its gate, introducing the preset high-voltage signal source A as a pre-charge substitute voltage into the substitute path. Simultaneously, the gate of the second transistor T2 is connected to the previous stage scan signal G(n-1), ensuring that the timing of the pre-charge replacement voltage transmission is completely synchronized with the pre-charge timing of the original circuit. That is, the second transistor T2 only conducts when the previous stage scan signal G(n-1) is high, transmitting the pre-charge replacement voltage to the first node Q. This allows the replacement circuit 20 to seamlessly take over the original pre-charge function after the DC high-voltage signal line VDS fails, maintaining the normal conduction of the output transistor TB and the continuous output of the current stage scan signal Gn, fundamentally avoiding longitudinal crosstalk caused by the loss of the scan signal. Furthermore, since the replacement circuit 20 only operates when the DC high-voltage signal line VDS fails and the previous stage scan signal is high, its power consumption is extremely low, and it will not impose an additional burden on the overall power consumption of the display panel.

[0071] It should be noted that the first transistor T1 can be understood as a P-type thin-film transistor or a P-type MOS transistor. This first transistor T1 is used to introduce a preset high-voltage signal source A when the DC high-voltage signal line VDS fails, realizing automatic detection and response to the failure of the DC high-voltage signal line VDS, ensuring that the backup circuit 20 only intervenes when needed and maintains effective isolation from the main circuit. The main circuit is the original gate scanning unit 11 basic architecture that does not include the backup circuit 20, which is the core path for performing row scanning drive when the display panel is working normally.

[0072] The second transistor T2 can be understood as an N-type thin-film transistor or an N-type MOS transistor. The second transistor T2 is used to control the transmission timing of the high-voltage signal source A, ensuring that the pre-charge replacement voltage provided by the high-voltage signal source A is transmitted to the first node Q only when the front-stage scan signal G(n-1) is high, so as to keep the pre-charge timing synchronized with the original circuit of the gate scan unit 11.

[0073] When the DC high voltage signal line VDS fails, the preset high voltage signal source A is controlled by the detection circuit to output high voltage as the pre-charge backup voltage source of the backup circuit 20. When the DC high voltage signal line VDS is normal, the detection circuit controls the high voltage signal source A to output low voltage, so that the entire backup circuit 20 is in standby state.

[0074] In a specific embodiment, refer to Figure 4 and combined Figure 5 In the detection circuit shown, when the DC high-voltage signal line VDS outputs high voltage normally, the gate of the first transistor T1 is connected to a high level, and the first transistor T1 is in the cutoff state. That is, the first and second path terminals of the first transistor T1 are disconnected, thereby cutting off the path of the high-voltage signal source A to the second crystal. At the same time, the detection transistor in the detection circuit is also kept in the cutoff state because its gate is connected to the high level of the DC high-voltage signal line VDS. That is, there is no high-voltage signal injected into the input terminal of the high-voltage signal source A, so the high-voltage signal source A outputs low voltage. At this time, although the second transistor T2 is turned on by the front-stage scanning signal G(n-1) connected to its gate, there is no high-voltage input to the first path terminal of the second transistor T2, so there is no voltage output at the second path terminal of the second transistor T2, and it cannot have any effect on the first node Q. Therefore, the substitute circuit 20 is in a standby state and is completely isolated from the original circuit of the gate scanning unit 11, without affecting the normal operation of the original circuit.

[0075] When a single-sided DC high-voltage signal line VDS fails due to process defects, electrostatic breakdown, or long-term aging, the signal level of that side's DC high-voltage signal line VDS instantly drops from a high level to a low level. At this time, the first transistor T1 is turned on because its gate is connected to a low level, forming a low-impedance path between the first and second path terminals (i.e., source and drain) of the first transistor T1. Simultaneously, the detection transistor in the detection circuit is also turned on because its gate is connected to the low level output of the DC high-voltage signal line VDS. Since the first path terminal of the detection transistor is electrically connected to the connection line from the driver chip to the DC high-voltage signal line VDS, the high-voltage signal output from the driver chip to the DC high-voltage signal line VDS is introduced into the input terminal of the high-voltage signal source A, causing the high-voltage signal source A to output high voltage. The high voltage of the high-voltage signal source A (i.e., the pre-charge replacement voltage) is then transmitted to the first path terminal of the second transistor T2 through the turned-on first transistor T1. At this time, if the previous stage scan signal G(n-1) output from the previous stage gate scan unit 11 arrives, i.e., the previous stage scan signal G(n-1) is at a high level, the second transistor T2 will be turned on due to the high voltage connected to its gate, thereby forming a low-impedance path between the source and drain of the second transistor T2, and then transmitting the pre-charge replacement voltage from the first transistor T1 to the first node Q, completing the pre-charge of the first node Q. After the potential of the first node Q rises, the output transistor TB is turned on, transmitting the clock signal CK from the clock terminal to the scan output terminal of this stage, maintaining the normal output of the scan signal Gn of this stage.

[0076] Through the above process, even if the DC high-voltage signal line VDS completely fails, the gate scanning unit at this stage can still obtain a pre-charge voltage that is completely synchronized with the original timing through the replacement circuit 20, ensuring that the scanning signal is not lost and the pixel driving is not interrupted, thereby completely avoiding dark stripes and longitudinal crosstalk caused by the failure of the DC high-voltage signal line VDS. When the display panel enters the next frame scan, the above replacement process will be repeatedly executed according to the working state of the DC high-voltage signal line VDS (i.e., normal or failed) and the previous stage scanning signal G(n-1), continuously ensuring display uniformity.

[0077] Furthermore, in some feasible embodiments, reference is made to Figure 6The substitute circuit 20 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The gate of the third transistor T3, the first path terminal of the third transistor T3, and the gate of the fifth transistor T5 are respectively electrically connected to a preset high-voltage signal source A. The second path terminal of the third transistor T3 is electrically connected to the first path terminals of the fourth transistor T4 and the fifth transistor T5, respectively. The second path terminal of the fifth transistor T5 is electrically connected to the first path terminal of the sixth transistor T6. The gate of the fourth transistor T4 is electrically connected to the DC high-voltage signal line VDS. The second path terminal of the fourth transistor T4 is electrically connected to a preset low-potential terminal VGL. The gate of the sixth transistor T6 is connected to the pre-stage scanning signal. The second path terminal of the sixth transistor T6 is connected between the first node Q and the gate of the output transistor TB.

[0078] In this embodiment, a backup voltage transmission path with signal isolation and timing synchronization functions is constructed by setting up a backup circuit 20 including a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. Specifically, the gates of the third transistor T3 and the fifth transistor T5 are connected to the high-voltage signal source A, forming a real-time monitoring of the state of the high-voltage signal source A; the gate of the fourth transistor T4 is connected to the DC high-voltage signal line VDS, serving as a detection element for the failure of the DC high-voltage signal line VDS; the gate of the sixth transistor T6 is connected to the pre-stage scanning signal G(n-1), ensuring that the pre-charge backup voltage transmitted by the high-voltage signal source A is strictly synchronized with the pre-charge timing of the original circuit of the gate scanning unit 11. When the DC high-voltage signal line VDS is normal, the fourth transistor T4 is turned on, pulling the first path terminal (i.e., the source) of the fifth transistor T5 down to a low potential, thereby preventing the fifth transistor T5 from turning on, thus cutting off the complete path for the high-voltage signal source A to transmit the pre-charge backup voltage to the first node Q, without affecting the original circuit of the gate scanning unit 11. When the DC high-voltage signal line VDS fails, the fourth transistor T4 switches from the on state to the off state, releasing the blockade of the fifth transistor T5. At this time, if the high-voltage signal source A outputs high voltage, the third transistor T3 and the fifth transistor T5 turn on, transmitting the pre-charge replacement voltage provided by the high-voltage signal source A to the first node Q via the fifth transistor T5 and the sixth transistor T6. The transmission timing is controlled by the pre-stage scan signal G(n-1) connected to the sixth transistor T6, ensuring that the replacement pre-charge is consistent with the original timing. This not only realizes the automatic detection and replacement of the DC high-voltage signal line VDS, but also... Figure 6 The series structure of the multi-stage transistors shown enhances the isolation of the circuit during shutdown, avoids interference from the substitute circuit 20 to the original circuit during normal operation, and further improves the stability and reliability of the circuit.

[0079] It should be noted that the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type thin-film transistors or N-type MOS transistors.

[0080] The low potential terminal VGL refers to the DC low voltage reference point, which is usually a negative voltage or ground potential, and is used to pull down the potential connected to the first path terminal of the fifth thin film transistor.

[0081] In a specific embodiment, refer to Figures 5 to 6 When the DC high-voltage signal line VDS outputs a normal high level, the fourth transistor T4 is turned on because its gate is connected to a high level. A low-impedance path is formed between the first and second path terminals of the fourth transistor T4, precisely pulling the common connection point between the second path terminal of the third transistor T3, the first path terminal of the fourth transistor T4, and the first path terminal of the fifth transistor T5 down to the preset low potential terminal VGL. At this time, the detection transistor in the detection circuit detects that the DC high-voltage signal line VDS is normal and controls the high-voltage signal source A to output a low voltage, so that the gates of the third transistor T3 and the fifth transistor T5 are both connected to the low-voltage signal provided by the high-voltage signal source A. At this time, the gate voltage of the third transistor T3 is low and the common connection point connected to the second path terminal has been pulled low to the low potential VGL. Therefore, the gate-source voltage Vgs of the third transistor T3 is approximately 0, keeping the third transistor T3 in the off state. Similarly, the gate voltage of the fifth transistor T5 is also approximately 0 because its gate is connected to a low voltage and its first path terminal (source) is pulled low to VGL by the fourth transistor T4. This ensures that the fifth transistor T5 is also reliably turned off, guaranteeing that there is no high voltage output at the second path terminal of the fifth transistor T5, and it is in a floating or low potential state. Since the first path terminal of the sixth transistor T6 is connected to the second path terminal of the fifth transistor T5, which has no high voltage output, even if the gate of the sixth transistor T6 is connected to a high-level pre-stage scan signal G(n-1) and turned on, there is no high voltage to be transmitted at the first path terminal of the sixth transistor T6. As a result, the second path terminal of the sixth transistor T6 cannot provide voltage to the first node Q. That is, the sixth transistor T6 is actually in an unconducted state and has no effect on the first node Q. In other words, when the DC high voltage signal line VDS is working normally, the backup circuit 20 not only does not consume any static power, but also does not introduce any interference or additional load to the normal operation of the original circuit of the gate scanning unit 11. At the same time, it is prepared for rapid and accurate intervention when the DC high voltage signal line VDS fails, ensuring that the backup circuit 20 is automatically activated only when needed.

[0082] When a single-sided DC high-voltage signal line VDS fails, the VDS voltage on that side drops to a low level. At this time, the gate of the fourth transistor T4 is connected to this low level, causing it to quickly switch from the on state to the off state, thereby releasing the low-potential clamping on the common connection point between the second path terminal of the third transistor T3, the first path terminal of the fourth transistor T4, and the first path terminal of the fifth transistor T5. Simultaneously, the detection transistor in the detection circuit conducts because its gate is connected to the low level of the DC high-voltage signal line VDS, transmitting the high-voltage signal output from the driver chip to the input terminal of the high-voltage signal source A, causing the high-voltage signal source A to output a high level representing high voltage. The gates of the third transistor T3 and the fifth transistor T5 are simultaneously connected to this high level. Because the gate of the third transistor T3 is at a high level and its first path terminal is connected to the high-voltage signal source A, the third transistor T3 conducts, transmitting the high voltage from the high-voltage signal source A to the common connection point, causing the potential at the common connection point to be pulled up from a low level to a high level. Since the gate of the fifth transistor T5 is at a high level and the first path terminal is connected to the common connection point that has been pulled high, the gate-source voltage Vgs of the fifth transistor T5 is positive and greater than the threshold voltage for the fifth transistor T5 to conduct. Therefore, the fifth transistor T5 also conducts, transmitting the high voltage of the high voltage signal source A to the second path terminal of the fifth transistor T5 through the common connection point, thereby causing the potential of the second path terminal of the fifth transistor T5 to rise to a high level.

[0083] At this time, if the previous stage scan signal G(n-1) is high, the sixth transistor T6 will be turned on due to its gate being connected to a high level. Since the first path terminal of the sixth transistor T6 is connected to the second path terminal of the fifth transistor T5, which is already at a high level, the turned-on sixth transistor T6 pulls the first node Q connected to its second path terminal high, completing the pre-charge of the first node Q. After the potential of the first node Q rises, the output transistor TB turns on, transmitting the clock signal CK from the clock terminal to the scan output terminal Gn of this stage, so that the scan signal Gn of this stage is output normally. This ensures that even if the DC high voltage signal line VDS fails, the gate scan unit of this stage can still maintain normal scan drive function, effectively avoiding longitudinal crosstalk caused by the loss of scan signal.

[0084] Furthermore, in some other feasible embodiments, reference is made to... Figure 6 The crosstalk suppression module includes a detection transistor; the gate of the detection transistor is electrically connected to the DC high-voltage signal line VDS, the first path terminal of the detection transistor is electrically connected to the connection line from the driver chip to the DC high-voltage signal line VDS, and the second path terminal of the detection transistor is electrically connected to the high-voltage signal source A.

[0085] In this embodiment, a real-time monitoring and response mechanism for the operating status of the DC high-voltage signal line VDS is constructed by setting a detection transistor, providing a precise decision signal for the automatic activation of the backup circuit 20. Specifically, the detection transistor can capture the potential change of the DC high-voltage signal line VDS with zero delay. That is, when the DC high-voltage signal line VDS normally outputs a high level, the detection transistor remains off (i.e., in the cutoff state), ensuring that there is no high-voltage input from the high-voltage signal source A, and the backup circuit 20 is in standby mode. When the DC high-voltage signal line VDS fails and drops to a low level, the detection transistor instantly turns on, directly introducing the stable high voltage output from the driver chip into the high-voltage signal source A, so that the high-voltage signal source A outputs a high voltage as the pre-charge backup voltage for the backup circuit 20. In other words, the detection transistor set in this application ensures that the backup circuit 20 can immediately intervene in the first scan cycle after the DC high-voltage signal line VDS fails, fundamentally avoiding the loss of scan signal due to detection delay. At the same time, the detection transistor requires only a very small layout area, does not increase the bezel width of the display panel, and has outstanding advantages of low cost, fast response, and high reliability.

[0086] It should be noted that the detection transistor can be a P-type thin-film transistor or a P-type MOS transistor.

[0087] In a specific embodiment, refer to Figure 5 The gate of the detection transistor is directly connected to the DC high-voltage signal line VDS. The first terminal (source) of the detection transistor is connected to the path through which the driver chip outputs a high-voltage signal to the DC high-voltage signal line VDS. The second terminal (drain) of the detection transistor is connected to the high-voltage signal source A. When in Figure 7 In the normal display state shown, the DC high-voltage signal line VDS stably outputs a high level VGH. At this time, the high level connected to the gate of the detection transistor keeps the detection transistor in a cutoff state. Therefore, the high-voltage signal from the driver chip cannot be transmitted to the high-voltage signal source A through the detection transistor, and the high-voltage signal source A outputs a low level VGL. The backup circuit 20 is in standby mode because the high-voltage signal source A is at a low level, completely isolated from the original circuit of the gate scanning unit 11, and the display panel operates normally without crosstalk. However, when... Figure 7 When the failure moment of the DC high-voltage signal line VDS arrives, the potential of VDS rapidly drops to a low level VGL. Since the source of the detection transistor still maintains the high voltage VGH output by the driver chip, the gate of the detection transistor is connected to the low level provided by the DC high-voltage signal line VDS, making the gate-source voltage Vgs of the detection transistor negative (VGL-VGH), thus causing the detection transistor to turn on instantaneously. Next, the high voltage VGH of the IC is transmitted to the high-voltage signal source A through the turned-on detection transistor, causing the output potential of the high-voltage signal source A to jump from a low level VGL to a high level VGH.

[0088] Furthermore, in some feasible embodiments, the substitute circuit 20 includes a seventh transistor; the gate of the seventh transistor and the first path terminal of the seventh transistor are electrically connected to the DC high voltage signal line VDS, and the second path terminal of the seventh transistor is electrically connected to the gate of the precharge transistor TA.

[0089] In this embodiment, an extremely simple structure is constructed by using a single seventh transistor. Figure 8 The replacement circuit 20 is shown. The seventh transistor utilizes the characteristics of a P-type thin-film transistor or a P-type MOSFET to achieve automatic detection and direct replacement of the failure of the DC high-voltage signal line VDS. Specifically, when the DC high-voltage signal line VDS outputs a normal high level, the seventh transistor is in the off state due to the high level connected to its gate, and is isolated from the original circuit of the gate scanning unit 11; when the DC high-voltage signal line VDS fails and drops to a low level, the seventh transistor automatically turns on, directly introducing the high voltage of the previous stage scanning signal G(n-1) output by the previous stage gate scanning unit 11 into the first node Q, completing the pre-charge of the first node Q, thereby maintaining the normal conduction of the output transistor TB and the output of the current stage scanning signal Gn. No additional high-voltage signal source A and detection circuit are required; fault tolerance can be achieved with only one seventh transistor, which has the outstanding advantages of simple structure and low cost.

[0090] In a specific embodiment, refer to Figure 8 The gate of the seventh transistor is directly connected to the DC high-voltage signal line VDS. The first path terminal (i.e., drain) of the seventh transistor is connected between the first path terminal of the precharge transistor TA and the DC high-voltage signal line VDS. The second path terminal (i.e., source) of the seventh transistor is connected to the pre-stage scan signal G(n-1) output by the previous stage gate scan unit 11. When the DC high-voltage signal line VDS outputs a high level normally, regardless of whether the pre-stage scan signal G(n-1) is high or low, the seventh transistor is in the off state because its gate is high. At this time, under the control of the pre-stage scan signal G(n-1), the pre-charge voltage of the DC high-voltage signal is provided to the first node Q to pre-charge the first node Q normally, so that the output transistor TB is turned on to realize the normal output of the current stage scan signal Gn.

[0091] When the single-sided DC high-voltage signal line VDS fails and drops to a low level, the seventh transistor is turned on due to the low level connected to its gate. At this time, if the previous stage scan signal G(n-1) of the previous stage gate scan unit 11 is high (i.e., the moment when the current stage gate scan unit needs to be pre-charged), the high level of the previous stage scan signal G(n-1) is directly transmitted to the first node Q through the turned-on seventh transistor, causing the potential of the first node Q to rise, thereby turning on the output transistor TB and transmitting the clock signal CK to the output terminal of this stage scan to maintain the normal output of the first node Q of this stage scan signal. Since G(n-1) itself is a signal synchronized with the original pre-charge timing, the substitute pre-charge timing controlled by the seventh transistor is completely consistent with the original circuit of the gate scan unit 11, achieving seamless connection and ensuring that the scan signal is not lost, thereby effectively avoiding longitudinal crosstalk.

[0092] In summary, by incorporating a crosstalk suppression module integrating a gate drive circuit 10 and a substitute circuit 20, this application significantly improves the fault tolerance capability of the display device with the integrated crosstalk suppression module to the failure of the DC high voltage signal line VDS, thereby ensuring the display uniformity of the display device under high contrast. Specifically, the gate drive circuit 10 includes a multi-stage gate scan unit 11. In this stage gate scan unit (i.e., any stage in the multi-stage gate scan unit 11), the gate of the pre-charge transistor TA is connected to the previous stage scan signal output by the previous stage gate scan unit 11. The first path terminal of the pre-charge transistor TA is electrically connected to a preset DC high-voltage signal line VDS. The second path terminal of the pre-charge transistor TA and the gate of the output transistor TB are electrically connected to the first node Q. The first path terminal of the output transistor TB is connected to a preset clock terminal, and the second path terminal of the output transistor TB is the scan output terminal of this stage. This allows the pre-charge transistor TA to pre-charge the first node Q under the drive of the previous stage scan signal by connecting to the pre-charge voltage provided by the DC high-voltage signal line VDS, thereby turning on the output transistor TB and outputting the scan signal of this stage, realizing the normal row scan drive of this stage gate scan unit. When the DC high-voltage signal line VDS fails, the gate of the pre-charge transistor TA is connected to the DC high-voltage signal line VDS to pre-charge the first node Q, thereby turning on the output transistor TB and outputting the scan signal of this stage, realizing the normal row scan drive of this stage gate scan unit. The substitute circuit 20 between line VDS and the first path terminal of precharge transistor TA enables precharge transistor TA to provide precharge substitute voltage to the first node Q under the drive of the previous stage scan signal, so as to maintain the normal conduction of output transistor TB. Since the introduction of precharge substitute voltage does not depend on the failed DC high voltage signal line VDS, and the drive of precharge transistor TA is still controlled by the previous stage scan signal, the gate scan unit of this stage can still maintain normal scan output after the failure of DC high voltage signal line VDS, avoiding dark stripes caused by the loss of scan signal in the pixel row corresponding to the gate scan unit of this stage. At the same time, the problem of increased TFT leakage current caused by increased waveform noise is also eliminated, fundamentally blocking the leakage path from the middle bright area to the dark stripe area, effectively suppressing the occurrence of longitudinal crosstalk, significantly improving the fault tolerance capability of the display device to the failure of DC high voltage signal line VDS, and ensuring that the display device can still present a uniform display effect under high contrast dynamic picture.

[0093] Furthermore, based on the first embodiment of the crosstalk suppression module of this application, a second embodiment of the control method of the crosstalk suppression module of this application is proposed.

[0094] The control method for the crosstalk suppression module of this application is applied to the crosstalk suppression module described above. The control method for the crosstalk suppression module of this application is executed by the display device applied to the crosstalk suppression module. The control method for the crosstalk suppression module of this application includes the following implementation steps S10 to S20.

[0095] Step S10: When the preset DC high voltage signal line is normal, the pre-charge transistor of the current gate scan unit is triggered under the drive of the previous stage gate scan unit's front-stage scan signal. The pre-charge voltage provided by the DC high voltage signal line is connected to pre-charge the first node of the current gate scan unit, so that the output transistor of the current gate scan unit is turned on and outputs the current scan signal.

[0096] In this embodiment, when the preset DC high-voltage signal line outputs a high level normally, the pre-stage scan signal G(n-1) output by the previous stage gate scan unit is at a high level. The pre-charge transistor TA is turned on under the drive of the pre-stage scan signal G(n-1), transmitting the high-voltage pre-charge voltage provided by the DC high-voltage signal line to the first node, causing the potential of the first node to rise. The output transistor is turned on because its gate is connected to a high potential, transmitting the clock signal input at the clock terminal CK to the output terminal of this stage, generating the local stage scan signal Gn. This local stage scan signal Gn drives the pixel transistors of the corresponding row to turn on to write the grayscale voltage, and also serves as the pre-stage scan signal for the next stage gate scan unit, realizing step-by-step transmission. During this process, the substitute circuit is completely isolated from the main circuit and does not participate in any operation.

[0097] And / or, step S20: when the DC high voltage signal line fails, enable the precharge transistor to provide the precharge backup voltage of the backup circuit to the first node under the drive of the front-stage scan signal, so as to maintain the normal conduction of the output transistor.

[0098] In this embodiment, when the DC high-voltage signal line fails and drops to a low level, Figure 5 The detection transistor in the detection circuit is momentarily turned on when its gate is connected to a low level, transmitting the high-voltage signal output by the driver chip to the input of the high-voltage signal source, causing the high-voltage signal source to output high voltage. The backup circuit is automatically activated after receiving the high-voltage signal from the high-voltage signal source. At this time, if the previous stage scan signal G(n-1) is high, the pre-charge transistor is turned on under the drive of the previous stage scan signal G(n-1). Simultaneously, the backup circuit provides the pre-charge backup voltage to the first node, causing the potential of the first node to rise and turn on the output transistor. The clock signal CK is then transmitted to the output of this stage scan through the turned-on output transistor, maintaining the normal output of the scan signal of this stage. Through the above process, even if the DC high-voltage signal line fails completely, the gate scan unit of this stage can still obtain a pre-charge backup voltage synchronized with the original timing by relying on the backup circuit, ensuring that the scan signal is not lost and the pixel drive is not interrupted, thereby effectively avoiding the longitudinal crosstalk phenomenon caused by the failure of the DC high-voltage signal line.

[0099] It should be noted that the pre-charge replacement voltage can come from a high-voltage signal source or directly from a high-level pre-amplifier scan signal G(n-1).

[0100] Furthermore, in some other feasible embodiments, the control method may also include steps A10 to A30.

[0101] Step A10: Detect the operating level of the DC high voltage signal line using the detection transistor in the crosstalk suppression module.

[0102] In this embodiment, refer to Figure 5 The gate of the detection transistor is directly connected to the DC high-voltage signal line. The first terminal of the detection transistor is electrically connected to the connection line from the driver chip to the DC high-voltage signal line, and the second terminal of the detection transistor is electrically connected to the high-voltage signal source. The operating level of the DC high-voltage signal line can be accurately obtained by measuring the switching state of this detection transistor.

[0103] Step A20: When the operating level is low, it is determined that the DC high voltage signal line is faulty.

[0104] In this embodiment, when the switching state of the detection transistor is in the on state, it indicates that the working level of the DC high voltage signal line is low, that is, the DC high voltage signal line has failed. This triggers the backup circuit to enter the working state. That is, the backup circuit can complete the intervention within the first scan cycle after the DC high voltage signal line fails. Synchronously with the previous scan signal G(n-1), it injects the pre-charge backup voltage into the first node, so that the output transistor remains on, thereby realizing the normal output of the scan signal of this stage. This fundamentally avoids the longitudinal crosstalk phenomenon caused by the loss of the scan signal and ensures the display uniformity of the display panel.

[0105] Step A30: When the operating level is high, it is determined that the DC high voltage signal line is normal.

[0106] In this embodiment, when the switching state of the detection transistor is off (i.e., cut-off state), it indicates that the working level of the DC high voltage signal line is high, that is, the DC high voltage signal line is normal, thereby keeping the backup circuit in standby state, fundamentally avoiding interference to the original circuit of the gate scanning unit caused by the backup circuit's accidental intervention, and ensuring the stable operation and display uniformity of the display panel under normal conditions.

[0107] Furthermore, in some feasible embodiments, step A10 above, which involves detecting the operating level of the DC high-voltage signal line through the detection transistor in the crosstalk suppression module, may also include the following implementation steps A101 to A102.

[0108] Step A101: When the detection transistor in the crosstalk suppression module is turned on under the drive of the pre-charge voltage, the operating level of the DC high voltage signal line is determined to be low based on the turned-on detection transistor.

[0109] In this embodiment, since the detection transistor is a P-type thin-film transistor or a P-type MOS transistor, based on the switching characteristics of the detection transistor, it is known that the detection transistor conducts when its gate is connected to a low level. Therefore, when the gate of the detection transistor is connected to the pre-charge voltage provided by the DC high-voltage signal line, the switching state of the detection transistor automatically switches from the off state to the on state. This allows for accurate determination that the current operating level of the pre-charge voltage output by the DC high-voltage signal line is low, indicating that the DC high-voltage signal line has failed. In other words, this application utilizes the inherent switching characteristics of the P-type thin-film transistor or the P-type MOS transistor to achieve zero-delay, high-precision sensing of the failure state of the DC high-voltage signal line. This provides a reliable trigger signal for the automatic activation of the subsequent replacement circuit without requiring additional logic judgment, ensuring that the replacement pre-charge function can be activated in a timely manner when the DC high-voltage signal line fails, maintaining the normal output of the current scan signal.

[0110] Step A102: When the detection transistor in the crosstalk suppression module remains off under the drive of the precharge voltage, the operating level of the DC high voltage signal line is determined to be high based on the off detection transistor.

[0111] In this embodiment, since the detection transistor is a P-type thin-film transistor or a P-type MOS transistor, based on the switching characteristics of the detection transistor, it is known that the detection transistor is turned off when its gate is connected to a high level. Therefore, when the gate of the detection transistor is connected to the pre-charge voltage provided by the DC high-voltage signal line, the switching state of the detection transistor automatically remains in the off state. Thus, it can be accurately determined that the current operating level of the pre-charge voltage output by the DC high-voltage signal line is high, that is, the DC high-voltage signal line is working normally. In other words, this application utilizes the inherent switching characteristics of the P-type thin-film transistor or the P-type MOS transistor to achieve zero-delay, high-precision sensing of the normal state of the DC high-voltage signal line. This ensures that the backup circuit remains in standby mode when the DC high-voltage signal line is working normally, completely isolated from the main circuit. This avoids any interference to the process of the pre-charge transistor in the main circuit normally obtaining the pre-charge voltage from the DC high-voltage signal line, thereby ensuring that the gate scanning unit of this stage can independently and stably complete the pre-charging of the first node and the normal output of the scanning signal of this stage.

[0112] In addition, this application also provides a display panel, the display panel including: a display area; a non-display area, the non-display area including a DC high-voltage signal line and the crosstalk suppression module mentioned above, the gate driving circuits in the crosstalk suppression module being disposed on both sides of the display area, one DC high-voltage signal line corresponding to one gate driving circuit, and each DC high-voltage signal line providing a pre-charge voltage for each stage of the gate scanning unit in the corresponding gate driving circuit.

[0113] In this embodiment, the display panel includes a display area for displaying images and a non-display area surrounding the display area. The non-display area integrates a DC high-voltage signal line and the crosstalk suppression module described in the preceding embodiments. The gate driving circuit in the crosstalk suppression module adopts a dual-drive structure, located on the left and right sides of the display area. Each side's gate driving circuit drives half of the pixel rows of the display area, achieving stable driving of the large-size display panel. Simultaneously, each side's gate driving circuit is independently powered by a corresponding DC high-voltage signal line. Each DC high-voltage signal line provides a stable pre-charge voltage to each stage of the gate scanning unit in the corresponding side's gate driving circuit—that is, the left gate driving circuit is powered by the left DC high-voltage signal line, and the right gate driving circuit is powered by the right DC high-voltage signal line; the two circuits are independently powered and operate independently. This dual-sided independent power supply design ensures that when one side's DC high-voltage signal line fails due to process defects, electrostatic discharge, or long-term aging, only the corresponding gate drive circuit on that side needs to rely on a backup circuit to maintain operation. The other side's gate drive circuit continues to be powered by the normal DC high-voltage signal line, maintaining stable scanning output. Simultaneously, the backup circuit on the failed side automatically activates upon detecting the DC high-voltage signal line failure, taking over the pre-charge function to ensure that each level of the gate scanning unit on that side can still output scanning signals normally. This avoids longitudinal crosstalk on the display panel caused by unilateral failure. By integrating a crosstalk suppression module and independently powered DC high-voltage signal lines in the non-display area, this display panel not only improves its fault tolerance for unilateral DC high-voltage signal line failures and ensures display uniformity under high-contrast dynamic images, but also does not increase the bezel width, thus meeting the requirements of narrow bezel designs.

[0114] In addition, this application also provides a display device. Please refer to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a display device involved in an embodiment of this application. Specifically, the display device in this embodiment may be a device for controlling a locally running crosstalk suppression module.

[0115] The display device includes the display panel described above, and / or a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method for the crosstalk suppression module described above.

[0116] like Figure 9As shown, the display device in this embodiment may include: a crosstalk suppression module, a processor 1001 (e.g., a CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (e.g., a Wi-Fi interface).

[0117] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0118] Those skilled in the art will understand that Figure 9 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0119] like Figure 9 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a driver for a crosstalk suppression module.

[0120] exist Figure 9 In the display device shown, the processor 1001 can be used to call the driver program of the crosstalk suppression module stored in the memory 1005 and execute the steps of the control method of the crosstalk suppression module as described above.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0122] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0123] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0124] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A crosstalk suppression module, characterized in that, The crosstalk suppression module includes: A gate driving circuit includes a multi-stage gate scanning unit. Each gate scanning unit includes a pre-charge transistor, an output transistor, and a first node. The gate of the pre-charge transistor is connected to the previous stage scanning signal output by the previous stage gate scanning unit. The first path terminal of the pre-charge transistor is electrically connected to a preset DC high-voltage signal line. The second path terminal of the pre-charge transistor and the gate of the output transistor are electrically connected to the first node. The first path terminal of the output transistor is connected to a preset clock terminal. The second path terminal of the output transistor is the scan output terminal of this stage. This stage gate scanning unit can be any one of the multiple gate scanning units. The gate scanning unit of this stage is configured to enable the pre-charge transistor to pre-charge the first node by connecting to the pre-charge voltage provided by the DC high-voltage signal line under the drive of the previous stage scanning signal when the DC high-voltage signal line is normal, so that the output transistor is turned on and outputs the scanning signal of this stage. A backup circuit is connected between the DC high-voltage signal line and the first path terminal of the pre-charge transistor. The backup circuit is configured to enable the pre-charge transistor to provide a pre-charge backup voltage to the first node under the drive of the preceding scan signal when the DC high-voltage signal line fails, thereby maintaining the normal conduction of the output transistor. The crosstalk suppression module includes a detection transistor; The gate of the detection transistor is electrically connected to the DC high-voltage signal line, the first path terminal of the detection transistor is electrically connected to the connection line from the driver chip to the DC high-voltage signal line, and the second path terminal of the detection transistor is electrically connected to a preset high-voltage signal source.

2. The crosstalk suppression module as described in claim 1, characterized in that, The substitute circuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the DC high-voltage signal line, the first path terminal of the first transistor is electrically connected to the high-voltage signal source, and the second path terminal of the first transistor is electrically connected to the first path terminal of the second transistor. The gate of the second transistor is electrically connected to the gate of the precharge transistor, and the second path terminal of the second transistor is electrically connected to the first node.

3. The crosstalk suppression module as described in claim 1, characterized in that, The backup circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the third transistor, the first path terminal of the third transistor, and the gate of the fifth transistor are respectively electrically connected to the high-voltage signal source. The second path terminal of the third transistor is respectively electrically connected to the first path terminal of the fourth transistor and the first path terminal of the fifth transistor. The second path terminal of the fifth transistor is electrically connected to the first path terminal of the sixth transistor. The gate of the fourth transistor is electrically connected to the DC high-voltage signal line, the second path terminal of the fourth transistor is electrically connected to a preset low potential terminal, the gate of the sixth transistor is connected to the pre-stage scanning signal, and the second path terminal of the sixth transistor is connected between the first node and the gate of the output transistor.

4. The crosstalk suppression module as described in claim 1, characterized in that, The substitute circuit includes a seventh transistor; The gate of the seventh transistor and the first path terminal of the seventh transistor are electrically connected to the DC high voltage signal line, and the second path terminal of the seventh transistor is electrically connected to the gate of the precharge transistor.

5. A control method for a crosstalk suppression module, characterized in that, The control method is applied to the crosstalk suppression module according to any one of claims 1 to 4, and the control method includes: When the preset DC high-voltage signal line is normal, the pre-charge transistor of the current gate scan unit is triggered under the drive of the previous stage scan signal of the previous stage gate scan unit. The pre-charge voltage provided by the DC high-voltage signal line is used to pre-charge the first node of the current gate scan unit, so that the output transistor of the current gate scan unit is turned on and outputs the current stage scan signal; and / or, When the DC high-voltage signal line fails, the precharge transistor is enabled to provide the precharge backup voltage of the backup circuit to the first node under the drive of the front-stage scan signal, so as to maintain the normal conduction of the output transistor.

6. The control method as described in claim 5, characterized in that, The control method includes: The operating level of the DC high-voltage signal line is detected by the detection transistor in the crosstalk suppression module. When the operating level is low, it is determined that the DC high-voltage signal line is faulty; When the operating level is high, it is determined that the DC high voltage signal line is normal.

7. The control method as described in claim 6, characterized in that, The step of detecting the operating level of the DC high-voltage signal line through the detection transistor in the crosstalk suppression module includes: When the detection transistor in the crosstalk suppression module is turned on under the drive of the precharge voltage, the operating level of the DC high voltage signal line is determined to be low based on the turned-on detection transistor. When the detection transistor in the crosstalk suppression module remains off under the drive of the precharge voltage, the operating level of the DC high voltage signal line is determined to be high based on the off detection transistor.

8. A display panel, characterized in that, The display panel includes: Display area; The non-display area includes a DC high-voltage signal line and a crosstalk suppression module as described in any one of claims 1 to 4. The gate driving circuits in the crosstalk suppression module are disposed on both sides of the display area. One DC high-voltage signal line corresponds to one gate driving circuit. Each DC high-voltage signal line provides a pre-charge voltage for each stage of the gate scanning unit in the corresponding gate driving circuit.

9. A display device, characterized in that, The display device includes the display panel as described in claim 8; and / or, The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method for the crosstalk suppression module as described in claims 5 to 7.

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