Circuit and method for measuring average current of solenoid valve

Abstract

A circuit and method for measuring an average current of a solenoid valve, relating to the technical field of automotive electronics. The circuit comprises a solenoid valve (110), a first power supply (120), a sampling resistor, a field effect transistor drive circuit (130), a current acquisition circuit (140), an integrator circuit (150), and an integration reset circuit (160); the field effect transistor drive circuit (130) is used for controlling an on-off state of a first field effect transistor on the basis of a pulse width modulation gating signal; the first power supply (120) is used for providing a drive current for the solenoid valve (110) when the first field effect transistor is in an on state, and the drive current flows through the sampling resistor; the current acquisition circuit (140) is used for sampling voltage signals on two sides of the sampling resistor, and outputting the voltage signals to the integrator circuit (150); the integrator circuit (150) is used for performing integration processing on the voltage signals, and determining an average current of the solenoid valve (110) on the basis of an integration result; and the integration reset circuit (160) is used for performing periodic reset processing on the integrator circuit (150) on the basis of the pulse width modulation gating signal.

Description

Measurement circuit and method for average current of solenoid valve

[0001] This application claims priority to Chinese Patent Application No. 202411509430.6, filed on October 28, 2024, entitled "Measuring Circuit and Method for Average Current of Electromagnetic Valve", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of automotive electronics technology, and in particular to a circuit and method for measuring the average current of a solenoid valve. Background Technology

[0003] For hydraulic transmissions in automobiles, whether it is a continuously variable transmission (CVT), a dual-clutch transmission (DCT), a dedicated hybrid transmission (DHT), or an 8-speed automatic transmission (8AT), solenoid valves are used to control main hydraulic pressure, clutch hydraulic pressure, synchronizer, cooling flow, etc. In order to obtain more precise pressure control, a precise proportional solenoid valve is usually used, that is, the drive current of the solenoid valve is used as the control target, and the control is completed by the TCU (Transmission Control Unit).

[0004] In related technologies, a software closed-loop control method for solenoid valve drive current is adopted. This method combines discrete MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and microcontroller unit (MCU) software for control. The MCU software collects the real-time drive current flowing through the solenoid valve and TCU MOS transistor, calculates the average current, and then uses the average value for closed-loop control of the software target current.

[0005] The drive frequency of the gearbox solenoid valves is as high as several kilohertz, which means that the TCU needs to collect current values ​​from multiple points within a short period of time for averaging calculations. When multiple solenoid valves need to be controlled simultaneously, the MCU software load will increase significantly, resulting in a decrease in the control effect of the solenoid valves. Summary of the Invention

[0006] This application provides a circuit and method for measuring the average current of a solenoid valve, and the technical solution is as follows.

[0007] On one hand, embodiments of this application provide a circuit for measuring the average current of a solenoid valve, the circuit including a solenoid valve, a first power supply, a sampling resistor, a field-effect transistor driving circuit, a current acquisition circuit, an integration circuit, and an integration reset circuit;

[0008] The field-effect transistor driving circuit is used to control the on / off state of the first field-effect transistor based on a pulse width modulation gating signal.

[0009] The first power supply is used to provide a drive current to the solenoid valve when the first field-effect transistor is in the on state, and the drive current flows through the sampling resistor;

[0010] The current acquisition circuit is used to sample the voltage signal across the sampling resistor and output the voltage signal to the integration circuit.

[0011] The integrating circuit is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result.

[0012] The integral reset circuit is used to perform periodic reset processing on the integral circuit based on the pulse width modulation gating signal.

[0013] Optionally, the field-effect transistor driving circuit includes the first field-effect transistor, a gating signal source, a first inverter, a first gated clock, a first switch, a second gated clock, and a second switch;

[0014] The positive terminal of the gating signal source is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the control terminal of the first switch, the positive terminal of the gating signal source is connected to the control terminal of the second switch, and the negative terminal of the gating signal source is grounded.

[0015] The positive terminal of the first gate clock is connected to the first switch pin of the first switch, and the negative terminal of the first gate clock is grounded; the positive terminal of the second gate clock is connected to the first switch pin of the second switch, and the negative terminal of the second gate clock is grounded.

[0016] The second switch pin of the first switch is connected to the gate of the first field-effect transistor, and the second switch pin of the second switch is connected to the gate of the first field-effect transistor.

[0017] The gating signal source is used to output a gating signal to control the opening and closing states of the first switch and the second switch;

[0018] When the gating signal source does not output a gating signal, the first switch is in the closed state, the second switch is in the open state, and the first gate clock outputs a high duty cycle pulse width modulation gating signal to the gate of the first field-effect transistor.

[0019] When the gating signal source outputs the gating signal, the first switch is in the open state, the second switch is in the closed state, and the second gate clock outputs a low duty cycle pulse width modulation gating signal to the gate of the first field-effect transistor.

[0020] Optionally, the field-effect transistor driving circuit further includes a freewheeling diode, the anode of which is connected to the drain of the first field-effect transistor, the cathode of which is connected to the first power supply, and the source of the first field-effect transistor is grounded.

[0021] The first power supply is connected to the first pin of the solenoid valve, the second pin of the solenoid valve is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the sampling resistor is connected to the drain of the first field-effect transistor.

[0022] When the pulse width modulation gate signal is at a high level, the first field-effect transistor is in the on state, and the first power supply provides driving current to the solenoid valve.

[0023] When the pulse width modulation gate signal is at a low level, the first field-effect transistor is in an off state, and the first power supply does not provide the driving current to the solenoid valve.

[0024] Optionally, the current acquisition circuit includes a first operational amplifier, a feedback resistor, a voltage divider resistor, a filter capacitor, and a second power supply, wherein the second power supply supplies power to the first operational amplifier.

[0025] The non-inverting and inverting input terminals of the first operational amplifier are connected to the voltage divider resistor and the filter capacitor, and the output terminal of the first operational amplifier is connected to the integrator circuit.

[0026] The first resistor pin of the feedback resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the feedback resistor is connected to the output terminal of the first operational amplifier.

[0027] The voltage divider resistor is used to divide the voltage signal and output the divided voltage signal to the first operational amplifier.

[0028] The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integrating circuit.

[0029] Optionally, the voltage divider resistors include a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor; the filter capacitors include a first filter capacitor and a second filter capacitor;

[0030] The first resistor pin of the first voltage divider resistor is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the first voltage divider resistor is connected to the non-inverting input terminal of the first operational amplifier; the first resistor pin of the second voltage divider resistor is connected to the second resistor pin of the sampling resistor, and the second resistor pin of the second voltage divider resistor is connected to the inverting input terminal of the first operational amplifier; the first resistor pin of the third voltage divider resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second resistor pin of the third voltage divider resistor is grounded; the first resistor pin of the fourth voltage divider resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the fourth voltage divider resistor is grounded.

[0031] The first capacitor pin of the first filter capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the second capacitor pin of the first filter capacitor is grounded; the first capacitor pin of the second filter capacitor is connected to the inverting input terminal of the first operational amplifier, and the second capacitor pin of the second filter capacitor is grounded.

[0032] The current acquisition circuit also includes a protection capacitor; the first capacitor pin of the protection capacitor is connected to the first resistor pin of the sampling resistor, and the second capacitor pin of the protection capacitor is grounded.

[0033] Optionally, the integrating circuit includes a second operational amplifier, an integrating resistor, an integrating capacitor circuit, a multiplier, a third power supply, and a fourth power supply, wherein the third power supply powers the second operational amplifier and the fourth power supply powers the multiplier.

[0034] The first resistor pin of the integrating resistor is connected to the current acquisition circuit, the second resistor pin of the integrating resistor is connected to the non-inverting input terminal of the second operational amplifier, the integrating capacitor circuit is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the input terminal of the multiplier.

[0035] The integrating circuit further includes a first proportional resistor, a second proportional resistor, and a third proportional resistor; the first resistor pin of the first proportional resistor is connected to the inverting input terminal of the second operational amplifier, and the second resistor pin of the first proportional resistor is grounded; the first resistor pin of the second proportional resistor is connected to the inverting input terminal of the second operational amplifier, and the second resistor pin of the second proportional resistor is connected to the output terminal of the second operational amplifier; the first resistor pin of the third proportional resistor is connected to the non-inverting input terminal of the second operational amplifier, and the second resistor pin of the third proportional resistor is connected to the output terminal of the second operational amplifier.

[0036] The second operational amplifier is used to perform integration processing on the voltage signal and output the integrated voltage signal to the multiplier;

[0037] The multiplier is used to perform multiplication on the voltage signal after integration and to determine the average current of the solenoid valve based on the multiplication result.

[0038] Optionally, the integrating capacitor circuit includes a second inverter, a second field-effect transistor, a third field-effect transistor, a first integrating capacitor, and a second integrating capacitor;

[0039] The gate of the second field-effect transistor is connected to the integrating reset circuit, the source of the second field-effect transistor is connected to the first capacitor pin of the first integrating capacitor, and the drain of the second field-effect transistor is connected to the second capacitor pin of the first integrating capacitor.

[0040] The input terminal of the second inverter is connected to the integrating reset circuit, and the output terminal of the second inverter is connected to the gate of the third field-effect transistor.

[0041] The source of the third field-effect transistor is connected to the first capacitor pin of the second integrating capacitor, and the drain of the third field-effect transistor is connected to the second capacitor pin of the second integrating capacitor.

[0042] Optional,

[0043] When a high-level signal is received from the integrated reset circuit, the second field-effect transistor is in the on state, the third field-effect transistor is in the off state, the first integrating capacitor is in the short-circuit state, and the second integrating capacitor is used for the integration operation of the voltage signal.

[0044] When a low-level signal is received from the integral reset circuit, the second field-effect transistor is in the off state, the third field-effect transistor is in the on state, the second integrating capacitor is in the short-circuit state, and the first integrating capacitor is used for integral processing of the voltage signal.

[0045] Optionally, the integral reset circuit includes a D flip-flop and a protection resistor. The first resistor pin of the protection resistor is connected to the inverting output of the D flip-flop, the second resistor pin of the protection resistor is grounded, and the clock input of the D flip-flop is connected to the gate of the first field-effect transistor.

[0046] The D flip-flop is a rising-edge flip-flop, and the data input terminal of the D flip-flop is connected to the inverting output terminal, which is connected to the integrating circuit.

[0047] The D flip-flop is used to receive the pulse width modulation gate signal through the clock input terminal;

[0048] The D flip-flop is used to output the inverted signal of the inverting output terminal to the data input terminal when the rising edge of the pulse width modulation gate signal is received, so as to flip the signal state of the inverting output terminal.

[0049] On the other hand, embodiments of this application provide a method for measuring the average current of a solenoid valve. The method is used in a circuit for measuring the average current of a solenoid valve, the circuit including a solenoid valve, a first power supply, a sampling resistor, a field-effect transistor driving circuit, a current acquisition circuit, an integration circuit, and an integration reset circuit.

[0050] The method includes:

[0051] Based on the pulse width modulation gating signal, the conduction state of the first field-effect transistor is controlled by the field-effect transistor driving circuit;

[0052] When the first field-effect transistor is in the on state, the first power supply provides a drive current to the solenoid valve, and the drive current flows through the sampling resistor;

[0053] The current acquisition circuit samples the voltage signal across the sampling resistor and outputs the voltage signal to the integration circuit.

[0054] The voltage signal is integrated by the integrator circuit, and the average current of the solenoid valve is determined based on the integration result.

[0055] Based on the pulse width modulation gating signal, the integral circuit is periodically reset by the integral reset circuit.

[0056] This application proposes a circuit for measuring the average current of a solenoid valve. It directly uses hardware circuitry to measure the average current of the solenoid valve, effectively measuring the average current while reducing the load on the control software. The measurement circuit mainly includes a field-effect transistor (FET) drive circuit, a current acquisition circuit, an integrator circuit, and an integrator-reset circuit. The FET drive circuit uses pulse-width modulation (PWM) gating signals to simulate software output behavior, effectively controlling the on / off state of the first FET. When the first FET is on, a first power supply provides drive current to the solenoid valve. As the drive current flows through the sampling resistor, it is sampled by the current sampling circuit. The integrator circuit integrates the sampled voltage signal, ultimately obtaining the average current of the solenoid valve in a single cycle. Clearly, the measurement circuit uses only relatively conventional electronic components, reducing its cost. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 shows a schematic diagram of the framework of a circuit for measuring the average current of a solenoid valve provided in an exemplary embodiment of this application;

[0059] Figure 2 shows a circuit structure diagram of a field-effect transistor driving circuit provided in an exemplary embodiment of this application;

[0060] Figure 3 shows a circuit structure diagram of a current acquisition circuit provided in an exemplary embodiment of this application;

[0061] Figure 4 shows a circuit structure diagram of an integration circuit provided in an exemplary embodiment of this application;

[0062] Figure 5 shows a circuit structure diagram of an integral reset circuit provided in an exemplary embodiment of this application;

[0063] Figure 6 shows a circuit diagram of a solenoid valve average current measurement circuit provided in an exemplary embodiment of this application;

[0064] Figure 7 shows waveforms of voltage and current signals provided in an exemplary embodiment of this application;

[0065] Figure 8 shows the waveform change of the downward trend when the duty cycle of the pulse width modulation gated signal provided in an exemplary embodiment of this application decreases;

[0066] Figure 9 shows waveform details of voltage and current signals provided in an exemplary embodiment of this application;

[0067] Figure 10 shows a flowchart of a method for measuring the average current of a solenoid valve provided in an exemplary embodiment of this application. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0069] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0070] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0071] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0072] In related technologies, a software closed-loop control method for the solenoid valve drive current is typically used to control the solenoid valve of the gearbox. This method employs a combination of discrete MOSFETs and MCU software for control. The MCU software collects real-time drive current flowing through the solenoid valve and the TCU MOSFET, calculates the average current, and then uses this average value for closed-loop control of the target software current.

[0073] The drive frequency of the gearbox solenoid valves is as high as several kilohertz, which means that the TCU needs to collect current values ​​from multiple points within a short period of time for averaging calculations. When multiple solenoid valves need to be controlled simultaneously, the MCU software load will increase significantly, resulting in a decrease in the control effect of the solenoid valves.

[0074] Based on this, this application proposes a circuit for measuring the average current of a solenoid valve. This circuit uses hardware to measure the average current of the solenoid valve, thereby reducing the load on the control software while effectively measuring the average current. The circuit for measuring the average current of a solenoid valve proposed in this application will be described below through specific embodiments.

[0075] Please refer to Figure 1, which shows a schematic diagram of the framework of a solenoid valve average current measurement circuit provided in an exemplary embodiment of this application.

[0076] As shown schematically in Figure 1, the measurement circuit includes a solenoid valve 110, a first power supply 120, a sampling resistor (not shown), a field-effect transistor (MOS, MOSFET) drive circuit 130, a current acquisition circuit 140, an integration circuit 150, and an integration reset circuit 160.

[0077] The field-effect transistor drive circuit 130 is used to control the on / off state of the first field-effect transistor based on the pulse width modulation gating signal.

[0078] Optionally, for solenoid valves in hybrid vehicle transmissions, pulse width modulation (PWM) is typically used for control. PWM control parameters include frequency and duty cycle. The choice of frequency depends on the controlled object; for automotive hydraulic systems, carrier frequencies ranging from several hundred hertz to several kilohertz are commonly used. Changes in duty cycle and frequency directly affect the solenoid valve's power loss, output pressure stability, and dynamic response characteristics.

[0079] In some embodiments, a field-effect transistor (FET) driving circuit can be set in the measurement circuit. The output behavior in software control can be simulated by the pulse width modulation (PWM) gating signal output by the FET driving circuit, thereby realizing the control of the on / off state of the first FET according to the PWM gating signal.

[0080] The first power supply 120 is used to provide drive current to the solenoid valve 110 when the first field-effect transistor is in the on state, and the drive current flows through the sampling resistor.

[0081] In some embodiments, when the first field-effect transistor is in the on state, the first power supply can provide drive current to the solenoid valve. At this time, the drive current can flow through the sampling resistor so that the current acquisition circuit can sample it.

[0082] Optionally, the voltage of the first power supply can be set to 9–16V.

[0083] The current acquisition circuit 140 is used to sample the voltage signal across the sampling resistor and output the voltage signal to the integration circuit 150.

[0084] In some embodiments, considering that directly measuring the current in the circuit is difficult, while the voltage signal is more stable, the average current of the solenoid valve can be indirectly measured by sampling the voltage signal. Optionally, the current acquisition circuit is connected in parallel across the sampling resistor, thereby allowing sampling of the voltage signal across the sampling resistor.

[0085] Furthermore, in order to determine the average current of the solenoid valve in a single cycle during the solenoid valve control process, it is also necessary to integrate the sampled voltage signal. Therefore, the current acquisition circuit also needs to be connected to the integration circuit and output the acquired voltage signal to the integration circuit.

[0086] The integrating circuit 150 is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result.

[0087] In some embodiments, after receiving the voltage signal output by the current acquisition circuit, the integrator circuit can integrate the voltage signal to obtain the average voltage of the solenoid valve in a single cycle based on the integration result. Furthermore, based on the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be determined.

[0088] The integrator reset circuit 160 is used to perform periodic reset processing on the integrator circuit 150 based on the pulse width modulation gating signal.

[0089] In some embodiments, in order to determine the average current of the solenoid valve in a single cycle and avoid the accumulation of voltage signals over multiple cycles, after determining the average current in a single cycle through the integrator circuit, it is also necessary to perform periodic reset processing on the integrator circuit through the integrator reset circuit according to the PWM gate signal.

[0090] Optionally, integral reset processing refers to the operation of resetting the integration process in the integrating circuit by introducing an external signal or condition, so that it returns to its initial state. In the embodiments of this application, integral reset is to discharge the integrating capacitor in the integrating circuit.

[0091] In summary, this application proposes a measurement circuit for the average current of a solenoid valve, which directly measures the average current of the solenoid valve using hardware circuitry. This effectively measures the average current of the solenoid valve while reducing the load on the control software. The measurement circuit mainly includes a field-effect transistor (FET) drive circuit, a current acquisition circuit, an integrator circuit, and an integrator reset circuit. The FET drive circuit uses pulse-width modulation (PWM) gating signals to simulate software output behavior, effectively controlling the on / off state of the first FET in the FET drive circuit. When the first FET is in the on state, the first power supply provides drive current to the solenoid valve. As the drive current flows through the sampling resistor, it is sampled by the current sampling circuit, and the integrator circuit integrates the sampled voltage signal. Finally, the average current of the solenoid valve in a single cycle can be obtained from the integration result. Clearly, the measurement circuit uses only relatively conventional electronic components, reducing the cost of the measurement circuit.

[0092] The internal circuit structure of each circuit will be explained below.

[0093] Please refer to Figure 2, which shows a circuit structure diagram of a field-effect transistor driving circuit provided in an exemplary embodiment of this application.

[0094] As shown schematically in Figure 2, the field-effect transistor driving circuit includes a first field-effect transistor 250, a gating signal source 260, a first inverter 271, a first gated clock 273, a first switch 272, a second gated clock 275, and a second switch 274.

[0095] Specifically, the first gate clock 273 is used to output a high duty cycle PWM gate signal, and the second gate clock 275 is used to output a low duty cycle PWM gate signal. Optionally, the output frequency of the PWM gate signal can be 3kHz.

[0096] Optionally, the positive terminal of the gating signal source 260 is connected to the input terminal of the first inverter 271, the output terminal of the first inverter 271 is connected to the control terminal of the first switch 272, the positive terminal of the gating signal source 260 is connected to the control terminal of the second switch 274, and the negative terminal of the gating signal source 260 is grounded.

[0097] Optionally, the positive terminal of the first gate clock 273 is connected to the first switch pin of the first switch 272, and the negative terminal of the first gate clock 273 is grounded. The positive terminal of the second gate clock 275 is connected to the first switch pin of the second switch 274, and the negative terminal of the second gate clock 275 is grounded.

[0098] Optionally, the second switch pin of the first switch 272 is connected to the gate of the first field-effect transistor 250, and the second switch pin of the second switch 274 is connected to the gate of the first field-effect transistor 250.

[0099] Optionally, a gating signal source 260 is used to output a gating signal to control the opening and closing states of the first switch and the second switch.

[0100] Optionally, the strobe signal is a high-level signal, used to trigger the gating clock to emit a PWM gating signal. Optionally, the strobe signal source can emit a strobe signal every 5ms.

[0101] Optionally, when the gating signal source does not output a gating signal, the first switch is closed and the second switch is open; when the gating signal source outputs a gating signal, the first switch is open and the second switch is closed. That is, the first gating clock and the second gating clock alternately output PWM gating signals to the first field-effect transistor.

[0102] In one possible scenario, when the gating signal source 260 does not output a gating signal, the control terminal of the second switch 274 does not receive a high-level signal, so the second switch 274 is in the open state. Meanwhile, the input terminal of the first inverter 271 is a low-level signal. After the control terminal of the first switch 272 receives the high-level signal output by the first inverter 271, the first switch 272 is in the closed state. As a result, the positive terminal of the first gate clock 273 is connected to the gate of the first field-effect transistor 250, and the first gate clock 273 can output a high duty cycle pulse width modulation gating signal to the first field-effect transistor 250.

[0103] In another possible approach, when the gating signal source 260 outputs a gating signal, the control terminal of the second switch 274 receives a high-level signal, so the second switch 274 is in a closed state. Since the input terminal of the first inverter 271 is a high-level signal, the control terminal of the first switch 272 receives a low-level output from the first inverter 271, and the first switch 272 is in an open state. Thus, the positive terminal of the second gate clock 275 is connected to the gate of the first field-effect transistor 250, and the second gate clock 275 can output a low duty cycle pulse width modulation gating signal to the first field-effect transistor 250.

[0104] Optionally, considering that the first power supply is based on the PWM gate signal to periodically supply power to the solenoid valve, and the solenoid valve is an inductive load and the current will not change abruptly, a freewheeling diode needs to be connected in parallel on both sides of the solenoid valve so that the solenoid valve can gradually release the current when no drive current is received.

[0105] As shown schematically in Figure 2, the field-effect transistor driving circuit also includes a freewheeling diode 240. The anode of the freewheeling diode 240 is connected to the drain of the first field-effect transistor 250, and the cathode of the freewheeling diode 240 is connected to the first power supply 210, which is connected to the first pin of the solenoid valve 220 (represented by a combination of inductor and resistor in Figure 2). The source of the first field-effect transistor 250 is grounded.

[0106] Optionally, the first power supply 210 is connected to the first pin of the solenoid valve 220, the second pin of the solenoid valve 220 is connected to the first resistor pin of the sampling resistor 230, and the second resistor pin of the sampling resistor 230 is connected to the drain of the first field-effect transistor 250, that is, connected to the anode of the freewheeling diode 240.

[0107] In one possible implementation, when the pulse width modulation gate signal is high, the first field-effect transistor 250 is in a conducting state, at which time the first power supply 210 provides drive current to the solenoid valve 220. As shown in Figure 2, current flows out of the first power supply 210 and into the solenoid valve 220, the current in the solenoid valve 220 increases, then the current flows out of the solenoid valve 220 and through the sampling resistor 230, and finally into the first field-effect transistor 250.

[0108] In another possible approach, when the pulse width modulation gate signal is at a low level, the first field-effect transistor 250 is in an off state, and the first power supply 210 does not provide drive current to the solenoid valve 220. As shown in Figure 2, the solenoid valve 220 releases current, which flows through the sampling resistor 230 and the freewheeling diode 240 and is slowly released, causing the current to decrease.

[0109] In the above embodiments, in the field-effect transistor driving circuit, the on / off state of the first field-effect transistor is controlled by a PWM gating signal, which can achieve the periodic increase and decrease of the current of the solenoid valve. When a larger current is required, a PWM gating signal with a high duty cycle can be output through the first gating clock; when a smaller current is required, a PWM gating signal with a low duty cycle can be output through the second gating clock.

[0110] Please refer to Figure 3, which shows a circuit structure diagram of a current acquisition circuit provided in an exemplary embodiment of this application.

[0111] As shown schematically in Figure 3, the current acquisition circuit includes a first operational amplifier 370, a feedback resistor 350, a voltage divider resistor, a filter capacitor, and a second power supply 360, which supplies power to the first operational amplifier 370.

[0112] In this configuration, the non-inverting and inverting input terminals of the first operational amplifier 370 are connected to a voltage divider resistor and a filter capacitor, and the output terminal of the first operational amplifier 370 is connected to an integrator circuit. The first resistor pin of the feedback resistor 350 is connected to the inverting input terminal of the first operational amplifier 370, and the second resistor pin of the feedback resistor 350 is connected to the output terminal of the first operational amplifier 370.

[0113] The voltage divider resistor is used to divide the voltage signal and output the divided voltage signal to the first operational amplifier.

[0114] Optionally, considering that the sampling voltage across the sampling resistor may not meet the voltage input requirements of the first operational amplifier, a voltage divider resistor needs to be set at the input of the first operational amplifier to avoid damage to the first operational amplifier.

[0115] Optionally, a voltage divider resistor is connected in parallel across the sampling resistor to divide the voltage signal across the sampling resistor and output the divided voltage signal to the first operational amplifier.

[0116] The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integrating circuit.

[0117] Optionally, upon receiving a voltage signal, the first operational amplifier can amplify the voltage signal and output the amplified voltage signal to the integrating circuit. Optionally, the amplification factor is determined based on the resistance values ​​of the voltage divider resistor and the feedback resistor. By setting the resistance values ​​of the voltage divider resistor and the feedback resistor, the amplification factor can be set to ten times.

[0118] As illustrated in Figure 3, the voltage divider resistors may include a first voltage divider resistor 321, a second voltage divider resistor 322, a third voltage divider resistor 323, and a fourth voltage divider resistor 324.

[0119] Specifically, the first resistor pin of the first voltage divider resistor 321 is connected to the first resistor pin of the sampling resistor 310, and the second resistor pin of the first voltage divider resistor 321 is connected to the non-inverting input of the first operational amplifier 370. The first resistor pin of the second voltage divider resistor 322 is connected to the second resistor pin of the sampling resistor 310, and the second resistor pin of the second voltage divider resistor 322 is connected to the inverting input of the first operational amplifier 370. The first resistor pin of the third voltage divider resistor 323 is connected to the non-inverting input of the first operational amplifier 370, and the second resistor pin of the third voltage divider resistor 323 is grounded. The first resistor pin of the fourth voltage divider resistor 324 is connected to the inverting input of the first operational amplifier 370, and the second resistor pin of the fourth voltage divider resistor 324 is grounded.

[0120] As shown schematically in Figure 3, the filter capacitor includes a first filter capacitor 341 and a second filter capacitor 342.

[0121] Specifically, the first capacitor pin of the first filter capacitor 341 is connected to the non-inverting input terminal of the first operational amplifier 370, and the second capacitor pin of the first filter capacitor 341 is grounded. The first capacitor pin of the second filter capacitor 342 is connected to the inverting input terminal of the first operational amplifier 370, and the second capacitor pin of the second filter capacitor 342 is grounded.

[0122] Optionally, the current acquisition circuit also includes a protection capacitor 330, the first capacitor pin of the protection capacitor 330 being connected to the first resistor pin of the sampling resistor 310, and the second capacitor pin of the protection capacitor 330 being grounded.

[0123] In the above embodiments, in the current acquisition circuit, the voltage signal across the sampling resistor is first divided by a voltage divider resistor so that the voltage signal after voltage division meets the input requirements of the first operational amplifier. Then, the voltage signal is amplified by the first operational amplifier so that the subsequent integration circuit can integrate the amplified voltage signal.

[0124] Please refer to Figure 4, which shows a circuit structure diagram of an integrating circuit provided in an exemplary embodiment of this application.

[0125] As illustrated in Figure 4, the integrating circuit includes a second operational amplifier 430, an integrating resistor 410, an integrating capacitor circuit 420, a multiplier 460, a third power supply 451, and a fourth power supply 452. The third power supply 451 supplies power to the second operational amplifier 430, and the fourth power supply 452 supplies power to the multiplier 460.

[0126] Optionally, the first resistor pin of the integrating resistor 410 is connected to the current acquisition circuit, and the second resistor pin of the integrating resistor 410 is connected to the non-inverting input of the second operational amplifier 430. The integrating capacitor circuit 420 is connected to the non-inverting input of the second operational amplifier 430, and the output of the second operational amplifier 430 is connected to the input of the multiplier 460.

[0127] Optionally, in this embodiment, by placing the integrating capacitor circuit at the input terminal of the second operational amplifier, rather than between the input and output terminals, the integrating circuit can be powered by a single power supply, simplifying the design of the integrating circuit.

[0128] Optionally, in order to perform integration of the voltage signal, the integrating circuit may also include a first proportional resistor 441, a second proportional resistor 442, and a third proportional resistor 443.

[0129] Schematic diagram, as shown in Figure 4, the first resistor pin of the first proportional resistor 441 is connected to the inverting input of the second operational amplifier 430, and the second resistor pin of the first proportional resistor 441 is grounded. The first resistor pin of the second proportional resistor 442 is connected to the inverting input of the second operational amplifier 430, and the second resistor pin of the second proportional resistor 442 is connected to the output of the second operational amplifier 430. The first resistor pin of the third proportional resistor 443 is connected to the non-inverting input of the second operational amplifier 430, and the second resistor pin of the third proportional resistor 443 is connected to the output of the second operational amplifier 430.

[0130] The second operational amplifier is used to perform integration processing on the voltage signal and output the integrated voltage signal to the multiplier.

[0131] Optionally, after receiving the voltage signal output from the current acquisition circuit and filtering it through the integrating resistor and integrating capacitor circuits, the second operational amplifier can perform integration on the voltage signal to obtain the integrated voltage signal, which is an integral value containing a scaling factor. Furthermore, to obtain the average voltage over a single cycle, the second operational amplifier also needs to output the integrated voltage signal to the multiplier.

[0132] The multiplier is used to perform multiplication on the voltage signal after integration and to determine the average current of the solenoid valve based on the multiplication result.

[0133] Optionally, after receiving the voltage signal output from the second operational amplifier, the multiplier can use a multiplication factor to perform a multiplication operation on the integral value to obtain the multiplication result, which is the average voltage of the solenoid valve in a single cycle. Then, based on the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be obtained accordingly.

[0134] In some embodiments, in order to obtain the average current of the PWM gate signal for each cycle, it is also necessary to reset the integrator circuit after obtaining the average current of each cycle so that the average current of the solenoid valve can be measured again in the next PWM cycle.

[0135] Optionally, resetting the integrator circuit can be achieved by periodically discharging the integrator capacitor. Alternatively, the integrator capacitor circuit can employ a dual-capacitor series configuration, alternately connected to the second operational amplifier. Under the control of dual MOSFETs, the upper and lower capacitors participate in the integrator circuit in turn; that is, while one capacitor participates in integration, the other capacitor is bypassed by a switch and simultaneously discharged to zero through the switch. Then, at the arrival of the next PWM cycle, the discharged capacitor participates in integration, while the other capacitor is bypassed and discharged. By repeating this process, the average voltage and current for each PWM cycle can be determined through the integrator circuit.

[0136] As shown schematically in Figure 4, the integrating capacitor circuit includes a second inverter 425, a second field-effect transistor 422, a third field-effect transistor 424, a first integrating capacitor 421, and a second integrating capacitor 423.

[0137] In this circuit, the gate of the second field-effect transistor 422 is connected to the integrating reset circuit, the source of the second field-effect transistor 422 is connected to the first capacitor pin of the first integrating capacitor 421, and the drain of the second field-effect transistor 422 is connected to the second capacitor pin of the first integrating capacitor 421. The input of the second inverter 425 is connected to the integrating reset circuit, and the output of the second inverter 425 is connected to the gate of the third field-effect transistor 424. The source of the third field-effect transistor 424 is connected to the first capacitor pin of the second integrating capacitor 423, and the drain of the third field-effect transistor 424 is connected to the second capacitor pin of the second integrating capacitor 423.

[0138] In one possible configuration, upon receiving a high-level signal from the integrating reset circuit, the second field-effect transistor 422 is in the ON state, meaning the first integrating capacitor 421 is short-circuited and discharged. Meanwhile, the third field-effect transistor 424 receives a low-level signal from the second inverter 425 and is in the OFF state. Therefore, the second integrating capacitor 423 can be used to perform integration processing on the voltage signal in the integrating circuit.

[0139] In another possible approach, upon receiving a low-level signal from the integrating reset circuit, the second field-effect transistor 422 is in the off state, allowing the first integrating capacitor 421 to perform integration on the voltage signal in the integrating circuit. Meanwhile, the third field-effect transistor 424 receives a high-level signal from the second inverter 425, turning on the circuit. This means the second integrating capacitor 423 is short-circuited and discharged.

[0140] In the above embodiments, in the integrating circuit, after the voltage signal is integrated by the second operational amplifier, the integrated voltage value is multiplied by the multiplier to obtain the average voltage value of the solenoid valve in a single cycle. Thus, based on the conversion relationship between voltage and current, the average current value in a single cycle can be accurately obtained.

[0141] Optionally, to achieve alternating discharge control of the two capacitors in the integrating capacitor circuit based on the PWM cycle, the integrating capacitor circuit needs to be controlled by an integrating reset circuit. Furthermore, the signal frequency (i.e., the capacitor switching frequency) of the level signal output from the integrating reset circuit to the capacitor integrating circuit needs to be equal to half the frequency of the PWM gate signal, i.e., a frequency divide-by-two.

[0142] Please refer to Figure 5, which shows a circuit structure diagram of an integral reset circuit provided in an exemplary embodiment of this application.

[0143] As illustrated in Figure 5, the integral reset circuit includes a D flip-flop 510 and a protection resistor 520. The first resistor pin of the protection resistor 520 is connected to the inverting output of the D flip-flop 510, the second resistor pin of the protection resistor 520 is grounded, and the clock input of the D flip-flop 510 is connected to the gate of the first field-effect transistor, meaning the clock input of the D flip-flop 510 receives the PWM gate signal.

[0144] Optionally, the D flip-flop is a rising-edge flip-flop, with its data input terminal connected to the inverting output terminal, and the inverting output terminal connected to the integrating circuit.

[0145] Optionally, a D flip-flop 510 is used to receive a pulse width modulation gated signal via a clock input.

[0146] Optionally, the D flip-flop 510 is used to output the inverted signal of the inverting output terminal to the data input terminal when the rising edge of the pulse width modulation gate signal is received, so as to flip the signal state of the inverting output terminal.

[0147] In one possible approach, the initial state of the data input terminal of the D flip-flop 510 is set to 0, resulting in a 1 at the inverting output terminal. When a one-cycle PWM gate signal (high-then-low within a single cycle) is received at the clock input, since the D flip-flop is a rising-edge flip-flop and its data input terminal is connected to its inverting output terminal, the 1 at the inverting output terminal is applied to the data input terminal, switching the data input terminal to 1 and the inverting output terminal to 0. Then, upon receiving the next cycle of the PWM gate signal, the 0 at the inverting output terminal is applied to the data input terminal, switching the data input terminal to 0 and the inverting output terminal to 1. This process repeats, allowing the D flip-flop to flip the signal once upon receiving a one-cycle PWM gate signal, effectively dividing the PWM gate signal by two. This divided PWM gate signal then controls the periodic alternating charging and discharging of the integrating capacitor circuit in the integrating circuit.

[0148] Combining the circuit structure diagrams in the above embodiments, we can obtain the circuit structure diagram of the electromagnetic valve average current measurement circuit provided in an exemplary embodiment of this application, as shown in Figure 6. As can be seen from Figure 6, the current acquisition circuit 620 is connected in parallel with the sampling resistor R1 in the field-effect transistor drive circuit 610, used to acquire the voltage signal across the sampling resistor. Furthermore, the output terminal of the first operational amplifier in the current acquisition circuit 620 is connected to the integrator circuit 630, which can output the acquired voltage signal to the integrator circuit 630, which then performs integration processing on the voltage signal.

[0149] Furthermore, to calculate the average current per cycle, the integrator circuit 630 needs to be connected to the integrator reset circuit 640. The integrator reset circuit 640 outputs a divided-frequency signal of the PWM gate signal to achieve periodic discharge control of the two capacitors in the integrator capacitor circuit. At the same time, the integrator reset circuit 640 also needs to be connected to the field-effect transistor driver circuit 610 to receive the PWM gate signal from the field-effect transistor driver circuit 610.

[0150] By connecting and controlling the field-effect transistor drive circuit, current acquisition circuit, integrator circuit, and integrator reset circuit, the average current of the solenoid valve can be measured, while reducing the design cost of the measurement circuit and the load rate of the control software.

[0151] Please refer to Figure 7, which shows the waveforms of the voltage and current signals provided in an exemplary embodiment of this application.

[0152] As shown in Figure 7, from bottom to top, the first layer is the duty cycle waveform diagram, which includes two duty cycles; the second layer is the waveform diagram of the frequency divider control signal; the third layer is the waveform diagram of the solenoid valve drive current; the fourth layer is the waveform diagram of the converted voltage signal; and the fifth layer is the waveform diagram of the cycle-by-cycle average voltage value.

[0153] Please refer to Figure 8, which shows the downward trend waveform of a pulse width modulation gated signal provided in an exemplary embodiment of this application as the duty cycle decreases.

[0154] As shown in Figure 8, as the duty cycle of the PWM gate signal decreases, the sampled current and voltage both decrease, and the average voltage value of each PWM cycle also decreases.

[0155] Please refer to Figure 9, which shows waveform details of voltage and current signals provided in an exemplary embodiment of this application.

[0156] As shown in Figure 9, at the end of each PWM cycle, the average value reaches its maximum, and this moment is the average value of that cycle. Then, the average value is reset to zero instantly, and the average value is obtained again in the next cycle, finally obtaining the average value of the PWM cycle by cycle.

[0157] Please refer to Figure 10, which shows a flowchart of a method for measuring the average current of a solenoid valve according to an exemplary embodiment of this application. The method is used in a circuit for measuring the average current of a solenoid valve, the circuit including a solenoid valve, a first power supply, a sampling resistor, a field-effect transistor drive circuit, a current acquisition circuit, an integrator circuit, and an integrator reset circuit.

[0158] Step 1001: Based on the pulse width modulation gating signal, the conduction state of the first field-effect transistor is controlled by the field-effect transistor driving circuit.

[0159] Optionally, for solenoid valves in hybrid vehicle transmissions, pulse width modulation (PWM) is typically used for control. PWM control parameters include frequency and duty cycle. The choice of frequency depends on the controlled object; for automotive hydraulic systems, carrier frequencies ranging from several hundred hertz to several kilohertz are commonly used. Changes in duty cycle and frequency directly affect the solenoid valve's power loss, output pressure stability, and dynamic response characteristics.

[0160] In some embodiments, a field-effect transistor (FET) driving circuit can be set in the measurement circuit. The output behavior in software control can be simulated by the pulse width modulation (PWM) gating signal output by the FET driving circuit, thereby realizing the control of the on / off state of the first FET according to the PWM gating signal.

[0161] Step 1002: When the first field-effect transistor is in the on state, the first power supply provides a drive current to the solenoid valve, and the drive current flows through the sampling resistor.

[0162] In some embodiments, when the first field-effect transistor is in the on state, the first power supply can provide drive current to the solenoid valve. At this time, the drive current can flow through the sampling resistor so that the current acquisition circuit can sample it.

[0163] Optionally, the voltage of the first power supply can be set to 9–16V.

[0164] Step 1003: The voltage signal across the sampling resistor is sampled by the current acquisition circuit, and the voltage signal is output to the integration circuit.

[0165] In some embodiments, considering that directly measuring the current in the circuit is difficult, while the voltage signal is more stable, the average current of the solenoid valve can be indirectly measured by sampling the voltage signal. Optionally, the current acquisition circuit is connected in parallel across the sampling resistor, thereby allowing sampling of the voltage signal across the sampling resistor.

[0166] Furthermore, in order to determine the average current of the solenoid valve in a single cycle during the solenoid valve control process, it is also necessary to integrate the sampled voltage signal. Therefore, the current acquisition circuit also needs to be connected to the integration circuit and output the acquired voltage signal to the integration circuit.

[0167] Step 1004: Integrate the voltage signal using an integrating circuit, and determine the average current of the solenoid valve based on the integration result.

[0168] In some embodiments, after receiving the voltage signal output by the current acquisition circuit, the integrator circuit can integrate the voltage signal to obtain the average voltage of the solenoid valve in a single cycle based on the integration result. Furthermore, based on the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be determined.

[0169] Step 1005: Based on the pulse width modulation gating signal, the integrator circuit is periodically reset through the integrator reset circuit.

[0170] In some embodiments, in order to determine the average current of the solenoid valve in a single cycle and avoid the accumulation of voltage signals over multiple cycles, after determining the average current in a single cycle through the integrator circuit, it is also necessary to perform periodic reset processing on the integrator circuit through the integrator reset circuit according to the PWM gate signal.

[0171] Optionally, integral reset processing refers to the operation of resetting the integration process in the integrating circuit by introducing an external signal or condition, so that it returns to its initial state. In the embodiments of this application, integral reset is to discharge the integrating capacitor in the integrating circuit.

[0172] In summary, this application proposes a measurement circuit for the average current of a solenoid valve, which directly measures the average current of the solenoid valve using hardware circuitry. This effectively measures the average current of the solenoid valve while reducing the load on the control software. The measurement circuit mainly includes a field-effect transistor (FET) drive circuit, a current acquisition circuit, an integrator circuit, and an integrator reset circuit. The FET drive circuit uses pulse-width modulation (PWM) gating signals to simulate software output behavior, effectively controlling the on / off state of the first FET in the FET drive circuit. When the first FET is in the on state, the first power supply provides drive current to the solenoid valve. As the drive current flows through the sampling resistor, it is sampled by the current sampling circuit, and the integrator circuit integrates the sampled voltage signal. Finally, the average current of the solenoid valve in a single cycle can be obtained from the integration result. Clearly, the measurement circuit uses only relatively conventional electronic components, reducing the cost of the measurement circuit.

[0173] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0174] The above are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A circuit for measuring the average current of an electromagnetic valve, the circuit comprising an electromagnetic valve, a first power supply, a sampling resistor, a field-effect transistor driving circuit, a current acquisition circuit, an integrating circuit, and an integrating reset circuit; The field-effect transistor driving circuit is used to control the on / off state of the first field-effect transistor based on a pulse width modulation gating signal. The first power supply is used to provide a drive current to the solenoid valve when the first field-effect transistor is in the on state, and the drive current flows through the sampling resistor; The current acquisition circuit is used to sample the voltage signal across the sampling resistor and output the voltage signal to the integration circuit. The integrating circuit is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result. The integral reset circuit is used to perform periodic reset processing on the integral circuit based on the pulse width modulation gating signal.

2. The circuit according to claim 1, wherein, The field-effect transistor driving circuit includes a first field-effect transistor, a gating signal source, a first inverter, a first gated clock, a first switch, a second gated clock, and a second switch. The positive terminal of the gating signal source is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the control terminal of the first switch, the positive terminal of the gating signal source is connected to the control terminal of the second switch, and the negative terminal of the gating signal source is grounded. The positive terminal of the first gate clock is connected to the first switch pin of the first switch, and the negative terminal of the first gate clock is grounded; the positive terminal of the second gate clock is connected to the first switch pin of the second switch, and the negative terminal of the second gate clock is grounded. The second switch pin of the first switch is connected to the gate of the first field-effect transistor, and the second switch pin of the second switch is connected to the gate of the first field-effect transistor. The gating signal source is used to output a gating signal to control the opening and closing states of the first switch and the second switch; When the gating signal source does not output a gating signal, the first switch is in the closed state, the second switch is in the open state, and the first gate clock outputs a high duty cycle pulse width modulation gating signal to the gate of the first field-effect transistor. When the gating signal source outputs the gating signal, the first switch is in the open state, the second switch is in the closed state, and the second gate clock outputs a low duty cycle pulse width modulation gating signal to the gate of the first field-effect transistor.

3. The circuit according to claim 2, wherein, The field-effect transistor driving circuit also includes a freewheeling diode, the anode of which is connected to the drain of the first field-effect transistor, the cathode of which is connected to the first power supply, and the source of the first field-effect transistor is grounded. The first power supply is connected to the first pin of the solenoid valve, the second pin of the solenoid valve is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the sampling resistor is connected to the drain of the first field-effect transistor. When the pulse width modulation gate signal is at a high level, the first field-effect transistor is in the on state, and the first power supply provides driving current to the solenoid valve. When the pulse width modulation gate signal is at a low level, the first field-effect transistor is in an off state, and the first power supply does not provide the driving current to the solenoid valve.

4. The circuit according to claim 1, wherein, The current acquisition circuit includes a first operational amplifier, a feedback resistor, a voltage divider resistor, a filter capacitor, and a second power supply, wherein the second power supply supplies power to the first operational amplifier. The non-inverting and inverting input terminals of the first operational amplifier are connected to the voltage divider resistor and the filter capacitor, and the output terminal of the first operational amplifier is connected to the integrator circuit. The first resistor pin of the feedback resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the feedback resistor is connected to the output terminal of the first operational amplifier. The voltage divider resistor is used to divide the voltage signal and output the divided voltage signal to the first operational amplifier. The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integrating circuit.

5. The circuit according to claim 4, wherein, The voltage divider resistors include a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor; the filter capacitors include a first filter capacitor and a second filter capacitor; The first resistor pin of the first voltage divider resistor is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the first voltage divider resistor is connected to the non-inverting input terminal of the first operational amplifier; the first resistor pin of the second voltage divider resistor is connected to the second resistor pin of the sampling resistor, and the second resistor pin of the second voltage divider resistor is connected to the inverting input terminal of the first operational amplifier; the first resistor pin of the third voltage divider resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second resistor pin of the third voltage divider resistor is grounded; the first resistor pin of the fourth voltage divider resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the fourth voltage divider resistor is grounded. The first capacitor pin of the first filter capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the second capacitor pin of the first filter capacitor is grounded; the first capacitor pin of the second filter capacitor is connected to the inverting input terminal of the first operational amplifier, and the second capacitor pin of the second filter capacitor is grounded. The current acquisition circuit also includes a protection capacitor; the first capacitor pin of the protection capacitor is connected to the first resistor pin of the sampling resistor, and the second capacitor pin of the protection capacitor is grounded.

6. The circuit according to claim 1, wherein, The integrating circuit includes a second operational amplifier, an integrating resistor, an integrating capacitor circuit, a multiplier, a third power supply, and a fourth power supply. The third power supply powers the second operational amplifier, and the fourth power supply powers the multiplier. The first resistor pin of the integrating resistor is connected to the current acquisition circuit, the second resistor pin of the integrating resistor is connected to the non-inverting input terminal of the second operational amplifier, the integrating capacitor circuit is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the input terminal of the multiplier. The integrating circuit further includes a first proportional resistor, a second proportional resistor, and a third proportional resistor; the first resistor pin of the first proportional resistor is connected to the inverting input terminal of the second operational amplifier, and the second resistor pin of the first proportional resistor is grounded; the first resistor pin of the second proportional resistor is connected to the inverting input terminal of the second operational amplifier, and the second resistor pin of the second proportional resistor is connected to the output terminal of the second operational amplifier; the first resistor pin of the third proportional resistor is connected to the non-inverting input terminal of the second operational amplifier, and the second resistor pin of the third proportional resistor is connected to the output terminal of the second operational amplifier. The second operational amplifier is used to perform integration processing on the voltage signal and output the integrated voltage signal to the multiplier; The multiplier is used to perform multiplication on the voltage signal after integration and to determine the average current of the solenoid valve based on the multiplication result.

7. The circuit according to claim 6, wherein, The integrating capacitor circuit includes a second inverter, a second field-effect transistor, a third field-effect transistor, a first integrating capacitor, and a second integrating capacitor. The gate of the second field-effect transistor is connected to the integrating reset circuit, the source of the second field-effect transistor is connected to the first capacitor pin of the first integrating capacitor, and the drain of the second field-effect transistor is connected to the second capacitor pin of the first integrating capacitor. The input terminal of the second inverter is connected to the integrating reset circuit, and the output terminal of the second inverter is connected to the gate of the third field-effect transistor. The source of the third field-effect transistor is connected to the first capacitor pin of the second integrating capacitor, and the drain of the third field-effect transistor is connected to the second capacitor pin of the second integrating capacitor.

8. The circuit according to claim 7, wherein, When a high-level signal is received from the integrated reset circuit, the second field-effect transistor is in the on state, the third field-effect transistor is in the off state, the first integrating capacitor is in the short-circuit state, and the second integrating capacitor is used for the integration operation of the voltage signal. When a low-level signal is received from the integral reset circuit, the second field-effect transistor is in the off state, the third field-effect transistor is in the on state, the second integrating capacitor is in the short-circuit state, and the first integrating capacitor is used for integral processing of the voltage signal.

9. The circuit according to claim 1, wherein, The integral reset circuit includes a D flip-flop and a protection resistor. The first resistor pin of the protection resistor is connected to the inverting output terminal of the D flip-flop, the second resistor pin of the protection resistor is grounded, and the clock input terminal of the D flip-flop is connected to the gate of the first field-effect transistor. The D flip-flop is a rising-edge flip-flop, and the data input terminal of the D flip-flop is connected to the inverting output terminal, which is connected to the integrating circuit. The D flip-flop is used to receive the pulse width modulation gate signal through the clock input terminal; The D flip-flop is used to output the inverted signal of the inverting output terminal to the data input terminal when the rising edge of the pulse width modulation gate signal is received, so as to flip the signal state of the inverting output terminal.

10. A method for measuring the average current of a solenoid valve, the method being used in a circuit for measuring the average current of a solenoid valve, the circuit comprising a solenoid valve, a first power supply, a sampling resistor, a field-effect transistor driving circuit, a current acquisition circuit, an integrating circuit, and an integrating reset circuit. The method includes: Based on the pulse width modulation gating signal, the conduction state of the first field-effect transistor is controlled by the field-effect transistor driving circuit; When the first field-effect transistor is in the on state, the first power supply provides a driving current to the solenoid valve, and the driving current flows through the sampling resistor; The current acquisition circuit samples the voltage signal across the sampling resistor and outputs the voltage signal to the integration circuit. The voltage signal is integrated by the integrator circuit, and the average current of the solenoid valve is determined based on the integration result. Based on the pulse width modulation gating signal, the integral circuit is periodically reset by the integral reset circuit.

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