A fully dynamic delta-sigma modulator circuit
By using a fully dynamic Delta-Sigma modulator circuit, and by employing a floating inverting dynamic amplifier and active noise shaping successive approximation analog-to-digital converter, the challenges of reducing power consumption and improving accuracy of Delta-Sigma analog-to-digital converters are solved, achieving high energy efficiency and second-order noise shaping effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING ZHONGKE MICROELECTRONICS CO LTD
- Filing Date
- 2023-02-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing Delta-Sigma analog-to-digital converters face challenges in reducing power consumption and improving accuracy. Traditional methods, such as continuous-time architectures with feedforward and inverter-based integrators, suffer from instability and high power consumption. The number of comparators and capacitor requirements in quantizers lead to excessive power consumption.
A fully dynamic Delta-Sigma modulator circuit is adopted, and a floating inverting dynamic amplifier is used to form a closed-loop integrator. Combined with an active noise-shaping successive approximation analog-to-digital converter and a dynamic component matching calibration circuit, second-order noise shaping and low power consumption are achieved.
It achieves high energy efficiency in analog-to-digital conversion, reduces power consumption, and improves noise shaping capability, stability, and accuracy, while suppressing nonlinear distortion introduced by capacitor mismatch.
Smart Images
Figure CN115987290B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and more specifically, to a fully dynamic Delta-Sigma modulator circuit. Background Technology
[0002] With the rapid development of the information age, various electronic devices are moving towards digitalization. Direct analog signal processing is gradually being phased out, replaced by large-scale digital signal processing. However, the real world is full of analog signals such as sound, light, temperature, and pressure. Therefore, high-performance analog-to-digital converters (ADCs) have become the bridge connecting the digital and analog worlds. For example, in the audio field, high-precision Delta-Sigma ADCs are widely used in headphones, speakers, microphones, and other high-fidelity audio consumer electronic devices. Wearable portable audio electronic devices also have high power consumption requirements, so the audio field typically uses low-power, high-precision Delta-Sigma ADCs.
[0003] In a Delta-Sigma analog-to-digital converter (ADC), the analog section is a Delta-Sigma modulator, and the digital section is a downsampling digital filter. The Delta-Sigma modulator determines the overall performance of the converter. As process technology continues to evolve towards advanced processes, the intrinsic gain of transistors and the supply voltage continue to decrease, posing a significant challenge to the design of high-precision Delta-Sigma modulators.
[0004] The current mainstream approach to reducing power consumption is to use a continuous-time architecture with feedforward, which avoids the need for large on-chip capacitors to suppress thermal noise. However, the resistors and capacitors in this architecture cannot provide a precise time constant, leading to modulator instability. Furthermore, it is more susceptible to clock jitter and excessive loop delay. The high power consumption of discrete Delta-Sigma modulators is due to the need to drive large on-chip capacitors, which requires a large quiescent current from the operational amplifier.
[0005] Another common low-power approach is to use an inverter-based integrator, whose supply voltage can be as low as below 1V, achieving extremely low power consumption. However, the effective number of bits implemented in this architecture is typically limited to below 14 bits, and the circuit is very sensitive to process, temperature, and voltage variations.
[0006] Furthermore, if a multi-bit quantizer is used, it is typically implemented using a flash analog-to-digital converter (ADC). The number of comparators required by a flash ADC increases exponentially with the number of bits; for example, a 5-bit flash ADC requires 31 comparators. This increase in comparators also consumes a significant amount of power. Moreover, when the quantizer precision is too high, the size of the dynamic element matching circuit also increases exponentially. Therefore, the number of bits in a quantizer is usually less than 6 bits. Summary of the Invention
[0007] To address the shortcomings of existing technologies, this invention provides a fully dynamic Delta-Sigma modulator circuit that utilizes an active noise shaping quantizer to improve the noise shaping capability of a first-order modulator to that of a second-order modulator, and eliminates the modulator's quiescent current, thereby achieving a very high energy efficiency ratio.
[0008] As a first aspect of the present invention, a fully dynamic Delta-Sigma modulator circuit is provided, the fully dynamic Delta-Sigma modulator circuit including a dynamic integrator, a noise-shaping analog-to-digital converter and a dynamic element matching calibration circuit, wherein the input terminal of the dynamic integrator is connected to an analog input signal and the output terminal of the dynamic element matching calibration circuit, the input terminal of the noise-shaping analog-to-digital converter is connected to the analog input signal and the output terminal of the dynamic integrator, and the output terminal of the noise-shaping analog-to-digital converter is connected to the input terminal of the dynamic element matching calibration circuit;
[0009] The dynamic integrator is used to integrate the signal obtained by subtracting the analog input signal from the feedback signal, and output the integrated signal to the noise-shaping analog-to-digital converter.
[0010] The noise-shaping analog-to-digital converter is used to quantize the signal obtained by adding the integrated signal and the analog input signal, and output the quantized digital signal to the dynamic element matching calibration circuit.
[0011] The dynamic element matching calibration circuit is used to calibrate the quantized digital signal and output the feedback signal.
[0012] Furthermore, the dynamic integrator includes a floating inverting dynamic amplifier and a sampling capacitor C. S Integrating capacitor C I The first chopper switch and the second chopper switch, the floating inverting dynamic amplifier includes two symmetrical inverters and an energy storage capacitor C. r ;
[0013] At sampling phase φ1, one end of the sampling capacitor Cs is connected to the analog input voltage signal Vin / Vip, and the analog input voltage signal Vin / Vip is sampled onto the sampling capacitor Cs. The other end of the sampling capacitor Cs is connected to the common-mode level Vcm. One end of the energy storage capacitor Cr is connected to the power supply voltage VDD, and the other end of the energy storage capacitor Cr is connected to ground. The power supply is connected to the energy storage capacitor C. r To charge, the outputs of both inverters are connected to the common-mode level Vcm for reset.
[0014] At the integration phase φ2, one end of the sampling capacitor Cs is connected to the reference level Vref, and the other end of the sampling capacitor Cs is connected to the input terminal of the first chopper switch and the integration capacitor C. I At one end, the charge on the sampling capacitor Cs is forced to transfer to the integrating capacitor C. I Above, the power supply and ground terminals of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr. The output terminals of the two inverters are connected to the second chopper switch. The output terminals of the two inverters are no longer clamped to the common-mode level Vcm. During this period, the floating inverting dynamic amplifier has amplification capability, which enables the integration behavior to be realized.
[0015] At sampling phase φ1 or integration phase φ2, the integrating capacitor C I Both are connected between the input terminal of the first chopper switch and the output terminal of the second chopper switch.
[0016] Furthermore, the noise-shaping analog-to-digital converter includes a switched capacitor array, a dynamic amplifier, a dynamic comparator, and an asynchronous successive approximation logic circuit. One end of the switched capacitor array is connected to the positive input terminal of the dynamic comparator, and the other end of the switched capacitor array is connected to the analog input voltage signal Vin, the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The negative input terminal of the dynamic comparator is connected to the output terminal of the dynamic amplifier. The output terminal of the dynamic comparator is connected to the first terminal of the asynchronous successive approximation logic circuit. The second terminal of the asynchronous successive approximation logic circuit is connected to the switches of the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The third terminal of the asynchronous successive approximation logic circuit is connected to the clock input terminal of the dynamic comparator.
[0017] In phase Φs, capacitor C1 is connected between the two grounds; in phase Φn1, capacitor C1 is connected between one end of the switched capacitor array and ground; in phase Φn2, capacitor C1 is connected between the negative input terminal of the dynamic amplifier and ground; capacitor C2 is always connected across the negative input terminal and the output terminal of the dynamic amplifier, forming a closed-loop negative feedback.
[0018] Furthermore, the asynchronous successive approximation logic circuit includes D flip-flops and logic gate circuits.
[0019] Furthermore, the dynamic element matching calibration circuit includes two full adders, a set of registers, a thermometer code decoder, and a logarithmic shifter. The first input of the first full adder is connected to a 5-bit digital input signal, the second input of the first full adder is connected to the output of the register, the output of the first full adder is connected to the input of the register through the second full adder, the output of the register is connected to the first input of the logarithmic shifter, the second input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the input of the thermometer code decoder is connected to the 5-bit digital input signal.
[0020] Furthermore, the shift quantity input of the logarithmic shifter is connected to the output of the register, the data input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the logarithmic shifter finally outputs the shifted 31-bit data.
[0021] The fully dynamic Delta-Sigma modulator circuit provided by this invention has the following advantages: To reduce the power consumption of the modulator circuit, this invention uses a closed-loop dynamic integrator based on a floating inverting dynamic amplifier to replace the traditional operational amplifier-based integrator. The quantizer section uses an active noise-shaping successive approximation analog-to-digital converter to replace the traditional flash-type analog-to-digital converter, improving the overall circuit's energy efficiency ratio while enhancing the overall noise shaping effect to second order. Furthermore, a dynamic component matching calibration circuit is used to eliminate the nonlinear distortion introduced by capacitor mismatch in the digital-to-analog converter feedback branch; the first-stage integrator uses a bootstrap switch to improve sampling linearity, and a chopper switch to suppress DC offset and low-frequency flicker noise. Attached Figure Description
[0022] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.
[0023] Figure 1 The block diagram of the fully dynamic Delta-Sigma modulator circuit provided by the present invention.
[0024] Figure 2 This is the circuit schematic of a traditional dynamic amplifier.
[0025] Figure 3 The circuit diagram of the dynamic integrator based on the floating inverting dynamic amplifier provided by the present invention.
[0026] Figure 4 The single-ended equivalent circuit diagram of the noise-shaping analog-to-digital converter provided by the present invention.
[0027] Figure 5The schematic diagram of the dynamic element matching calibration circuit provided by the present invention.
[0028] Figure 6 The schematic diagram of the asynchronous successive approximation logic circuit provided by the present invention. Detailed Implementation
[0029] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of the fully dynamic Delta-Sigma modulator circuit proposed according to the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0031] In explaining this invention, it should be noted that the terms "installation," "connection," and "linking" should be interpreted broadly unless otherwise specified. For example, a connection can be a fixed connection, a connection through a special interface, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0032] This embodiment provides a fully dynamic Delta-Sigma modulator circuit, such as... Figure 1 As shown, the fully dynamic Delta-Sigma modulator circuit includes a dynamic integrator, a noise-shaping analog-to-digital converter, and a dynamic element matching calibration circuit. The input terminal of the dynamic integrator is connected to the analog input signal and the output terminal of the dynamic element matching calibration circuit, respectively. The input terminal of the noise-shaping analog-to-digital converter is connected to the analog input signal and the output terminal of the dynamic integrator, respectively. The output terminal of the noise-shaping analog-to-digital converter is connected to the input terminal of the dynamic element matching calibration circuit.
[0033] The dynamic integrator is used to integrate the signal obtained by subtracting the analog input signal from the feedback signal, and output the integrated signal to the noise-shaping analog-to-digital converter.
[0034] The noise-shaping analog-to-digital converter is used to quantize the signal obtained by adding the integrated signal and the analog input signal, and output the quantized digital signal to the dynamic element matching calibration circuit.
[0035] The dynamic element matching calibration circuit is used to calibrate the quantized digital signal and output the feedback signal.
[0036] Specifically, after subtracting the analog input signal from the feedback signal, the signal is fed into a dynamic integrator for integration. The integrated signal is then added to the analog input signal and quantized by an active noise-shaping successive approximation analog-to-digital converter. The quantized signal is output as a 5-bit digital signal, which is then calibrated by a dynamic element matching and calibration circuit before being fed back to the input.
[0037] In this embodiment of the invention, the fully dynamic Delta-Sigma modulator circuit adopts a single-loop first-order modulator architecture with feedforward. The closed-loop dynamic integrator is composed of a floating inverting amplifier, and the integrator adopts bootstrap switching technology and chopping technology. The quantizer adopts an active noise-shaping successive approximation analog-to-digital converter, and is fed back to the input of the integrator after passing through a dynamic element matching and calibration circuit.
[0038] It should be noted that the input to the dynamic integrator is zero during normal operation, and the integrator provides a very high loop gain at low frequencies, so the analog input signal and feedback signal are approximately equal at low frequencies. The noise transfer function exhibits high-pass characteristics, so the quantization noise is shaped to a higher frequency band after passing through the modulator. Because it uses a dynamic amplifier, it does not require additional quiescent current, hence the name dynamic integrator.
[0039] It should be noted that the active noise-shaping successive approximation analog-to-digital converter can not only quantize the input signal like a Nyquist-type analog-to-digital converter, but also exhibits first-order noise shaping characteristics. Since the dynamic integrator provides first-order noise shaping capability, the overall Delta Sigma modulator exhibits second-order noise shaping.
[0040] It should be noted that there is a mismatch between the unit capacitors in the feedback branch of the digital-to-analog converter (DAC), which introduces nonlinear distortion. This distortion cannot be shaped to high frequencies like quantization noise, so the mismatch needs to be calibrated. A dynamic component matching circuit is used to calibrate the nonlinear distortion introduced by the capacitor mismatch in the DAC feedback branch.
[0041] The fully dynamic Delta-Sigma modulator circuit provided by this invention consists of an integrator composed of a floating inverting dynamic amplifier, a bootstrap switch for sampling to improve sampling linearity, and a chopper switch to eliminate offset and low-frequency flicker noise. The entire integrator operates dynamically, providing a sufficiently large loop gain while significantly reducing power consumption. The quantizer is implemented by a five-bit active noise-shaping successive approximation analog-to-digital converter, which improves the overall noise shaping effect to second order and further reduces the overall power consumption of the circuit.
[0042] Because operational amplifiers in traditional pipelined analog-to-digital converters (ADCs) and Delta-Sigma ADCs consume a significant amount of power, dynamic amplifiers have been a hot research topic over the past decade. One type of traditional dynamic amplifier, such as... Figure 2 As shown, in the reset phase φ rst The output node is pre-charged to the supply voltage; once the amplification phase φ is reached... en The output discharges at varying rates, depending on the input voltage. This amplifier operates dynamically, achieving high energy efficiency. However, it faces several limitations in practical applications. First, its gain is very limited, and amplification ceases once the output common-mode voltage drops to ground; this limited gain leads to inaccurate closed-loop behavior. Second, the tail current source contributes noise during the amplification phase, primarily because the dynamic amplifier cannot provide a high common-mode rejection ratio. Third, the unstable output common-mode voltage, caused by the drop from the power supply to ground, makes it difficult to stabilize the closed-loop system. Finally, the output common-mode voltage is highly sensitive to process, voltage, and temperature variations, requiring additional calibration circuitry to stabilize it.
[0043] This invention employs a closed-loop integrator based on a floating inverting dynamic amplifier, the schematic of which is shown below. Figure 3 As shown, the dynamic integrator includes a floating inverting dynamic amplifier and a sampling capacitor C. S Integrating capacitor C I The first chopper switch and the second chopper switch, the floating inverting dynamic amplifier includes two symmetrical inverters and an energy storage capacitor C. r Where φ1 and φ2 are two non-overlapping clocks, φ 1e and φ 2e The advance clocks φ1 and φ2 are used to implement sampling of the sampling capacitor, φ c1 and φ c2 It is the clock of the chopper switch. Setting the phase advance is to eliminate the effects of charge injection and clock feedthrough by using the base plate sampling method. The chopper switch is used to eliminate amplifier offset and low-frequency flicker noise.
[0044] At sampling phase φ1, one end of the sampling capacitor Cs is connected to the analog input voltage signal Vin / Vip, and the analog input voltage signal Vin / Vip is sampled onto the sampling capacitor Cs. The other end of the sampling capacitor Cs is connected to the common-mode level Vcm. One end of the energy storage capacitor Cr is connected to the power supply voltage VDD, and the other end of the energy storage capacitor Cr is connected to ground. The power supply is connected to the energy storage capacitor C. r To charge, the outputs of both inverters are connected to the common-mode level Vcm for reset.
[0045] Specifically, during the reset phase, switch φ1 is closed, and sampling capacitor C... S Sampling is performed on the energy storage capacitor C. r During pre-charging, the outputs of both inverters are reset to the common-mode level Vcm.
[0046] At the integration phase φ2, one end of the sampling capacitor Cs is connected to the reference level Vref, and the other end of the sampling capacitor Cs is connected to the input terminal of the first chopper switch and the integration capacitor C. I At one end, due to charge conservation, the charge on the sampling capacitor Cs is forced to transfer to the integrating capacitor C. I Above, the power supply and ground terminals of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr. The output terminals of the two inverters are connected to the second chopper switch. The output terminals of the two inverters are no longer clamped to the common-mode level Vcm. During this period, the floating inverting dynamic amplifier has amplification capability, which enables the integration behavior to be realized.
[0047] At sampling phase φ1 or integration phase φ2, the integrating capacitor C I Both are connected between the input terminal of the first chopper switch and the output terminal of the second chopper switch.
[0048] It should be noted that φc1 and φc2 are chopping phases. In phase φc1, the two chopper switches act as wires; in phase φc2, the two chopper switches invert their respective input signals.
[0049] Specifically, during the integration phase, switch φ2 is closed, and the integrating capacitor C... I Integration is performed at the virtual ground of the amplifier, and the two power rails of the inverter are connected to the energy storage capacitor C. r The two ends of the energy storage capacitor C r Powering two inverters requires that the current flowing into and out of the energy storage capacitor be strictly equal, forcing zero current flowing from the output point to the load capacitor. This ensures that the common-mode level Vcm at the output point is stable when the inverters are in amplification mode. This closed-loop integration mode is similar to the integrator of a traditional op-amp with common-mode feedback, where the integration coefficient is determined by the capacitor ratio C. S / C IThe decision-making process, using CMOS technology, can achieve very high precision. The accuracy of the closed-loop integrator depends not only on the amplifier's open-loop gain but also on its bandwidth. During the integration phase, the energy storage capacitor powers the two inverters, and its supply voltage decreases over time. Therefore, the amplifier's bandwidth also decreases over time. However, as long as the system's speed requirements are met within half a cycle, the closed-loop integration behavior will be stably established.
[0050] It should be noted that the chopper switch is used in the closed-loop integrator to modulate low-frequency offset and flicker noise to the high-frequency range, and then filters them out using the downstream digital filter and quantization noise. The bootstrap switch is used in the closed-loop integrator to suppress the nonlinear distortion introduced by the sampling switch.
[0051] The closed-loop integrator based on a floating inverting dynamic amplifier provided by this invention adopts a parasitic-insensitive closed-loop integrator structure, compared to... Figure 2 This structure offers several advantages. First, the PMOS and NMOS input differential pairs of the floating inverting dynamic amplifier multiplex the current, improving current utilization. Second, this structure provides a constant output common-mode voltage, achieving this without the need for additional common-mode feedback circuitry. Furthermore, thanks to the stable output common-mode voltage, the amplifier's performance is insensitive to variations in clock frequency, process technology, voltage, and temperature.
[0052] The quantizer used in this invention is an active noise-shaping successive approximation analog-to-digital converter, and its single-sided equivalent circuit diagram is shown below. Figure 4 As shown, the noise-shaping analog-to-digital converter includes a switched capacitor array, a dynamic amplifier, a dynamic comparator, and an asynchronous successive approximation logic circuit, where Φ s It is the sampling phase, Φ c It is a phase transition, Φ sum Located in the time slot of sampling and phase conversion, used for feedforward summation, Φ n1 It is the residual sampling phase, Φ n2 It is the phase of the residual integral.
[0053] One end of the switched capacitor array is connected to the positive input terminal of the dynamic comparator, and the other end of the switched capacitor array is connected to the analog input voltage signal Vin, the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The negative input terminal of the dynamic comparator is connected to the output terminal of the dynamic amplifier. The output terminal of the dynamic comparator is connected to the first terminal of the asynchronous successive approximation logic circuit. The second terminal of the asynchronous successive approximation logic circuit is connected to the switches of the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The third terminal of the asynchronous successive approximation logic circuit is connected to the clock input terminal of the dynamic comparator. The control switch for Vin and Vout is Φs, and the switches for the other levels are controlled by the successive approximation logic circuit.
[0054] At sampling phase Φs, capacitor C1 is connected between the two grounds; at phase Φn1, capacitor C1 is connected between one end of the switched capacitor array and ground; at phase Φn2, capacitor C1 is connected between the negative input terminal of the dynamic amplifier and ground; capacitor C2 is always connected across the negative input terminal and the output terminal of the dynamic amplifier, forming a closed-loop negative feedback.
[0055] During sampling phase Φs, the integrator output signal Vout is connected to the top plate of the capacitor array for sampling, and the modulator input Vin is connected to the bottom plate for sampling. The feedforward operation is embedded in the two non-overlapping time slots. When sampling phase, during the non-overlapping summation phase Φsum, the bottom plate of the capacitor array is connected to the Vcm voltage, so that the feedforward summation operation is automatically completed before conversion. Then, successive approximation conversion is performed. After the conversion phase Φc is completed, the residual voltage on the top plate of the capacitor array is the quantization residual voltage. In phase Φn1, the residual voltage is sampled onto capacitor C1, and then in phase Φn2, the plate of C1 is connected to the input of the dynamic amplifier, and the residual voltage is integrated onto capacitor C2. Finally, it is sent to the dynamic comparator to complete the summation and comparison.
[0056] In this embodiment of the invention, the dynamic amplifier uses a floating inverting dynamic amplifier. The introduction of feedforward reduces the swing of the integrator output, and similarly reduces the oscillation of the quantizer input, thus reducing the nonlinear effect of the quantizer and making it closer to a linear system, thereby improving the overall stability of the modulator system. However, the introduction of feedforward also makes the circuit more complex. The usual approach is to use an operational amplifier to implement feedforward summation, while... Figure 4 The structure samples the integrator's output voltage V using a switched capacitor array top plate sampling method before the conversion begins. out Simultaneously, the input V of the feedforward branch is sampled using a base plate method. in Sampling is performed, then Φ before the transition phase arrives. sum The phase is connected to the base plate of all capacitors via a common-mode voltage V. cmThis allows for automatic summation before the conversion. At this point, the residual voltage from this conversion is stored on the top plate of the capacitor array, and then the residual voltage is sampled at phase Φ. n1 The residual voltage is sampled, and the residual integral phase Φ is... n2 Integrate the residual voltage. At the transition phase Φ c The process begins with successive approximation conversion. After each comparison, the dynamic comparator automatically generates its comparison clock using digital logic. After five comparisons, the final conversion result is obtained. Due to the fully dynamic operation of the quantizer, high energy efficiency is maintained.
[0057] The active noise-shaping successive approximation analog-to-digital converter provided by this invention is used as a multi-bit quantizer, which greatly improves the noise-shaping capability of the first-order modulator, reduces the design difficulty of the amplifier in the integrator, and performs input feedforward summation operation before conversion, eliminating one amplifier and maintaining low power consumption.
[0058] like Figure 6 As shown, the asynchronous successive approximation logic circuit mainly consists of standard unit circuits such as D flip-flops, delay units, and basic logic gates. The comparator's clock is automatically generated by the asynchronous successive approximation logic circuit, therefore no external high-frequency synchronous clock is required. The conversion process is handled by Φ C Triggered by the rising edge, the comparator completes its operation with the rising edge of the XOR gate. The D flip-flop 3 latches the comparator's output OP and generates the switching clock S based on the comparison result. Vrefp,i S Vrefn,i Used to connect the high-level capacitor base plate to Vrefp and Vrefn respectively. D flip-flop 2 generates the switching clock S. Vcm,i Used to connect the remaining capacitor base plates to Vcm. The charge redistribution time is controlled by the delay unit, with a delay time of T. R After all comparisons are completed, the transformation result D is... i The output is parallel to the four D flip-flops. The comparator's clock Φ COMP It is automatically generated by the logic circuit after the last comparison and does not require an external high-frequency synchronous clock.
[0059] Specifically, when the sampling clock Φ S High level, switching clock Φ C When the signal is low, D flip-flops 1, 2, and 3 are reset, control signals R0 to R4 become high, and the clock Φ of the dynamic comparator... COMP A low level indicates the comparator is also in a reset state. When the conversion clock Φ... C When it is high, the comparator's clock Φ COMPWhen the XOR gate output goes high, the comparator is activated to compare the input signal. Then, the XOR gate output goes high, causing D flip-flop 1 to operate. The outputs of D flip-flop 1, Q4 and QB4, change from low to high. The falling edge of QB4 activates D flip-flop 3. D flip-flop 3 latches the comparator output OP and generates the switching clock S for reference levels Vrefp and Vrefn based on the comparison result. Vrefp,4 S Vrefn,4 Used to connect the highest-order capacitor, while the base plates of the other corresponding capacitors should remain connected to the Vcm voltage. D flip-flop 2 generates the switching clock S for Vcm. Vcm,4 Used to connect the remaining capacitors; simultaneously, control signal R4 first changes from high to low, then is delayed by T. R After a certain time, the level returns to high. During this delay, the comparator is reset and completes the first charge redistribution. After the delay ends, the comparator is activated again for the second comparison. This process continues until the final comparison is completed, at which point the conversion result D is obtained. i The output is parallel to the D flip-flop 4.
[0060] Multi-bit quantization offers a range of benefits, including reduced quantization noise, reduced quantizer nonlinearity, lower amplifier design requirements, and improved modulator loop stability. However, it also presents a problem that needs to be addressed: capacitor mismatch in the digital-to-analog converter introduces nonlinearity, which severely degrades the output signal-to-noise ratio. This invention employs a data-weighted averaging dynamic component matching calibration circuit. This part is a digital circuit, and its main block diagram is shown below. Figure 5 As shown, the dynamic element matching calibration circuit includes two full adders, a set of registers, a thermometer code decoder, and a logarithmic shifter. The first input of the first full adder is connected to a 5-bit digital input signal, the second input of the first full adder is connected to the output of the register, the output of the first full adder is connected to the input of the register through the second full adder, the output of the register is connected to the first input of the logarithmic shifter, the second input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the input of the thermometer code decoder is connected to the 5-bit digital input signal.
[0061] Specifically, the shift quantity input of the logarithmic shifter is connected to the output of the register, the data input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the logarithmic shifter finally outputs the shifted 31-bit data.
[0062] In this embodiment of the invention, the output data of the noise-shaping analog-to-digital converter is converted into thermometer code by a decoder to drive the switching of the digital-to-analog converter. The switching sequence is periodically cyclical according to a polling algorithm, where adders, registers, and logarithmic shifters are used to implement this algorithm. The register latches the result of the previous summation and uses it as the shift amount in the next cycle, shifting the thermometer code cyclically by a specified amount. After passing through the dynamic component matching calibration circuit, the nonlinear distortion introduced by capacitor mismatch is effectively suppressed.
[0063] In this embodiment of the invention, the closed-loop integrator composed of a floating inverting dynamic amplifier operates dynamically, providing excellent noise shaping performance like a traditional operational amplifier-based closed-loop integrator, with extremely low power consumption. Furthermore, because the common-mode output of the floating inverting dynamic amplifier is stable, the closed-loop integrator is insensitive to clock frequency, process, temperature, and voltage.
[0064] The first-stage integrator introduces a chopper switch to shift low-frequency flicker noise and DC offset to a higher frequency band outside the signal band, which can be eliminated by the digital filter at the modulator back end along with quantization noise.
[0065] A feedforward path for the input signal exists before the quantizer, and this feedforward summation operation is embedded within a successive approximation analog-to-digital converter (ADC). The introduction of the feedforward path ensures that the input signal to the quantizer is almost entirely dependent on the quantization noise, reducing the correlation between the quantizer and modulator input signals, thereby improving loop stability and lowering the design requirements of the dynamic amplifier in the second-stage integrator. The quantizer employs an active noise-shaping successive approximation ADC, improving the overall noise shaping effect to second order and reducing the output swing at the integrator output, thus lowering the design requirements of the internal amplifier. Combined with the feedforward path, a simple single-stage dynamic amplifier can meet the performance requirements.
[0066] The dynamic component matching calibration circuit effectively suppresses the nonlinear distortion introduced by the capacitor mismatch in the feedback branch of the digital-to-analog converter.
[0067] In summary, the fully dynamic Delta-Sigma modulator circuit provided by this invention eliminates quiescent current, achieving high performance while maintaining very low power consumption.
[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A fully dynamic Delta-Sigma modulator circuit, characterized in that, The fully dynamic Delta-Sigma modulator circuit includes a dynamic integrator, a noise-shaping analog-to-digital converter, and a dynamic element matching calibration circuit. The input of the dynamic integrator is connected to the analog input signal and the output of the dynamic element matching calibration circuit, respectively. The input of the noise-shaping analog-to-digital converter is connected to the analog input signal and the output of the dynamic integrator, respectively. The output of the noise-shaping analog-to-digital converter is connected to the input of the dynamic element matching calibration circuit. The dynamic integrator is used to integrate the signal obtained by subtracting the analog input signal from the feedback signal, and output the integrated signal to the noise-shaping analog-to-digital converter. The noise-shaping analog-to-digital converter is used to quantize the signal obtained by adding the integrated signal and the analog input signal, and output the quantized digital signal to the dynamic element matching calibration circuit. The dynamic element matching calibration circuit is used to calibrate the quantized digital signal and output the feedback signal; The dynamic integrator includes a floating inverting dynamic amplifier and a sampling capacitor C. S Integrating capacitor C I The first chopper switch and the second chopper switch, the floating inverting dynamic amplifier includes two symmetrical inverters and an energy storage capacitor C. r ; At sampling phase φ1, one end of the sampling capacitor Cs is connected to the analog input voltage signal Vin / Vip, and the analog input voltage signal Vin / Vip is sampled onto the sampling capacitor Cs. The other end of the sampling capacitor Cs is connected to the common-mode level Vcm. One end of the energy storage capacitor Cr is connected to the power supply voltage VDD, and the other end of the energy storage capacitor Cr is connected to ground. The power supply is connected to the energy storage capacitor C. r To charge, the outputs of both inverters are connected to the common-mode level Vcm for reset. At the integration phase φ2, one end of the sampling capacitor Cs is connected to the reference level Vref, and the other end of the sampling capacitor Cs is connected to the input terminal of the first chopper switch and the integration capacitor C. I At one end, the charge on the sampling capacitor Cs is forced to transfer to the integrating capacitor C. I Above, the power supply and ground terminals of the two inverters are respectively connected to the two ends of the energy storage capacitor Cr. The output terminals of the two inverters are connected to the second chopper switch. The output terminals of the two inverters are no longer clamped to the common-mode level Vcm. During this period, the floating inverting dynamic amplifier has amplification capability, which enables the integration behavior to be realized. At sampling phase φ1 or integration phase φ2, the integrating capacitor C I Both are connected between the input terminal of the first chopper switch and the output terminal of the second chopper switch.
2. The fully dynamic Delta-Sigma modulator circuit according to claim 1, characterized in that, The noise-shaping analog-to-digital converter includes a switched capacitor array, a dynamic amplifier, a dynamic comparator, and an asynchronous successive approximation logic circuit. One end of the switched capacitor array is connected to the positive input terminal of the dynamic comparator, and the other end of the switched capacitor array is connected to the analog input voltage signal Vin, the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The negative input terminal of the dynamic comparator is connected to the output terminal of the dynamic amplifier. The output terminal of the dynamic comparator is connected to the first terminal of the asynchronous successive approximation logic circuit. The second terminal of the asynchronous successive approximation logic circuit is connected to the switches of the positive reference level Vrefp, the negative reference level Vrefn, and the common-mode level Vcm. The third terminal of the asynchronous successive approximation logic circuit is connected to the clock input terminal of the dynamic comparator. In phase Φs, capacitor C1 is connected between the two grounds; in phase Φn1, capacitor C1 is connected between one end of the switched capacitor array and ground; in phase Φn2, capacitor C1 is connected between the negative input terminal of the dynamic amplifier and ground; capacitor C2 is always connected across the negative input terminal and the output terminal of the dynamic amplifier, forming a closed-loop negative feedback.
3. The fully dynamic Delta-Sigma modulator circuit according to claim 2, characterized in that, The asynchronous successive approximation logic circuit includes D flip-flops and logic gates.
4. The fully dynamic Delta-Sigma modulator circuit according to claim 2, characterized in that, The dynamic element matching calibration circuit includes two full adders, a set of registers, a thermometer code decoder, and a logarithmic shifter. The first input of the first full adder is connected to a 5-bit digital input signal, the second input of the first full adder is connected to the output of the register, the output of the first full adder is connected to the input of the register through the second full adder, the output of the register is connected to the first input of the logarithmic shifter, the second input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the input of the thermometer code decoder is connected to the 5-bit digital input signal.
5. A fully dynamic Delta-Sigma modulator circuit according to claim 4, characterized in that, The shift quantity input of the logarithmic shifter is connected to the output of the register, the data input of the logarithmic shifter is connected to the output of the thermometer code decoder, and the logarithmic shifter finally outputs the shifted 31-bit data.