Pulse distortion compensation for pulse width modulation based converters

Abstract

Circuits and methods are disclosed for eliminating narrow pulses and compensating for the elimination, and compensating for dead time and non-ideal characteristics in converters, including voltage drops across switches and busbars, pulse distortions caused by delays, unequal rise and fall times, and DC busbar voltage drops. The method can be used for a converter with two complementary switches. A circuit embodiment includes three parts. The first portion calculates a deviation from a reference voltage using a dead time. The second portion includes a controller that adds a compensation value based on a difference between the converter output and the reference voltage. The third section cancels the narrow pulse and compensates for the cancellation by accumulating the difference between the reference signal and the output signal using an integrator, and adds a compensation value using a quantizer without introducing a new narrow pulse. The disclosed system eliminates narrow pulses to reduce loss, extend life, reduce EMI and improve output power quality.

Description

Technical Field

[0001] This disclosure relates to a method for compensating for pulse distortion in a converter with pulse width modulation (PWM). Background Technology

[0002] Power converters play a vital role in all aspects of our lives, including transportation, entertainment, energy, and the food chain, with applications encompassing, but not limited to, electric drives, electric vehicles (EVs), renewable energy harvesting, power regulation, and robotics. A power converter is a device that includes a control section implemented by electronic components (such as microcontrollers and operational amplifiers) and other components that control the structure (power section) of a power semiconductor switch by sending on / off commands to the gate driver of the power switch. A power converter can be viewed as an analog-to-digital (A / D) converter that creates a series of discrete values ​​from an analog waveform. For example, Figure 1 This illustrates a two-level bridge arm (pole), a building block for two-level AC / DC, DC / AC, or certain DC / DC converters, at the output terminal. V0 A series of signals relative to the midpoint of the DC link are generated at that location. V DC / 2 and- V DC / 2 It can be digitally represented as "1" and "0" to synthesize an analog reference signal. Figures 2A-2C The ideal and non-ideal output waveforms of this bridge arm are shown. S1 is referred to as the high-side switch, and S2 is referred to as the low-side switch.

[0003] The switches of this bridge arm cannot be turned on simultaneously; otherwise, a short circuit will occur between the positive (+) bus and the negative (-) bus. However, in the case of instantaneous switching between the high-side and low-side switches, there is a high possibility of overlapping conduction states due to component delays and non-ideal characteristics. To avoid this, an intentionally set dead time is inserted between the switching of the high-side and low-side switches, during which neither switch is turned on. This intentionally set turn-off time introduces distortion into the output voltage waveform. Voltage drops on the switches and buses, as well as non-ideal characteristics of electronic components (such as delays, different slew rates, different rise and fall rates), also cause output waveform distortion and degrade power quality.

[0004] Another source of distortion is the elimination of narrow pulses, which occurs at low and / or high modulation indices to reduce losses and protect the power switches. Depending on the modulation method, this task can also cause output waveform distortion in the high modulation index (MI) region and sometimes in the low MI region.

[0005] In converters with high switching frequencies, distortion accounts for a significant portion of the entire switching cycle and produces substantial deviations in the output waveform; therefore, compensating for pulse distortion is crucial. These distortions should be considered and compensated for in order to generate an output waveform that precisely matches the desired reference signal.

[0006] Methods for compensating for these errors have been proposed in existing literature. For example, US Patent 6714424 by Deng et al. (“Deng”) proposes adding a constant voltage to a reference voltage based on the current direction to compensate for voltage errors caused by dead time. Deng’s method delays the PWM pulse by a quarter of the switching cycle and generates four pulses, from which two are selected to trigger the switching of the bridge arm (leg) of the converter. In addition to the computational burden, this method requires a large number of microcontroller peripheral modules. Furthermore, this method does not consider the actual voltage drops across the switches and diodes, which introduce errors into the output voltage waveform. In another example, US Patent 8901864 by Chi et al. (“Chi”) proposes a dead time compensation method for V / F control drivers, which adds a smoothing value based on the detected current and dead time. However, in Chi’s method, the dead time is a predetermined value, and the system cannot operate properly in systems with variable dead times, such as auxiliary resonant commutator (ARCP) circuits. In any case, Chi’s method cannot compensate for other deviations caused by factors such as, but not limited to, non-ideal characteristics of components and minimum pulse width.

[0007] The advent of fast-switching devices such as silicon carbide (SiC) and gallium nitride (GaN) devices has enabled manufacturers to design converters with high switching frequencies. However, in such converters, even small deviations in the PWM pulses can lead to significant anomalies in the output voltage waveform and power quality.

[0008] The goal is to mitigate the aforementioned problems and, by compensating for introduced errors (such as added dead time, eliminated narrow pulses, and system nonlinearity and non-ideal characteristics), synthesize the reference waveform at the converter output with minimal distortion. Summary of the Invention

[0009] According to one aspect of this disclosure, a system is provided for eliminating narrow pulses from a power converter, compensating for the effects of such elimination, and outputting a desired voltage. The system includes: a sensor section for sensing electrical characteristics of a structure comprising two semiconductor devices arranged to switch in a complementary mode; and a control section including a modulator, the control section being in electrical communication with the sensor section and the structure, and for synthesizing a reference waveform (V) based on one or more of dead time, minimum acceptable pulse width (MAPW), and a desired pulse width. ref ); and the compensation portion, through V refAdd or subtract compensation values ​​to compensate the reference waveform V ref Relative to the desired voltage V o The deviation, so that the output is equal to the desired voltage V o Equivalent compensation voltage.

[0010] According to one aspect of this disclosure, a method for eliminating narrow pulses generated in a converter is provided. The method includes: receiving a reference minimum acceptable pulse width (MAPW); using a narrow pulse width detector to detect narrow pulses with a width narrower than MAPW; eliminating the narrow pulse; using an accumulator to accumulate the value of the eliminated narrow pulse; and using a quantizer to modify pulses in the converter's output waveform based on the accumulated value in the accumulator to compensate for the eliminated pulse, wherein the width of each pulse in the output waveform is greater than or equal to MAPW.

[0011] According to one aspect of this disclosure, a method for compensating dead time in a converter using a controller is provided. The method includes: receiving dead time values, load current, and current direction from a structure in the converter comprising two semiconductor devices arranged to switch in a complementary mode; calculating a compensation voltage based on one or more of the dead time value, load current, and current direction; and modifying a reference voltage based on the calculated compensation voltage.

[0012] These and other features, aspects and advantages of the invention will become more apparent to those skilled in the art from the following drawings and description. Attached Figure Description

[0013] To better understand the embodiments described herein and to more clearly demonstrate how to implement them, reference will now be made to the accompanying drawings by way of example only, wherein: Figure 1 The existing single-bridge arm structures of conventional AC-DC / DC-AC and some DC-DC converters are described; Figure 2A The ideal switching waveform in the bridge arm is depicted; Figure 2B An ideal switching waveform in the bridge arm, showing the dead time, is depicted; Figure 2C The non-ideal switching waveforms in the bridge arm, showing dead time, delay, and rise and fall times, are depicted. Figure 3A A general compensation architecture according to a first embodiment is described, which illustrates a dead time and non-ideal characteristic compensation (DTNIC) module; Figure 3B A general compensation architecture according to a second embodiment is depicted, which illustrates a narrow pulse cancellation and compensation (NPEC) module; Figure 3C A general compensation architecture according to a third embodiment is described, which includes two modules: DTNIC and NPEC. Figure 4 It is a flowchart depicting an algorithm for a dead time and other physical error compensation method according to embodiments of the present disclosure; Figure 5A A block diagram depicts an embodiment of NPEC that directly detects and compensates for pulse width; and Figure 5B A block diagram depicts an embodiment of an NPEC that performs a reference voltage detection and compensation operation.

[0014] Unless otherwise specified, the parts depicted in the accompanying drawings are not necessarily drawn to scale. Detailed Implementation

[0015] This disclosure relates to circuitry and methods for compensating for the effects of narrow pulses. Specific embodiments of the disclosed method can also compensate for dead time and non-ideal characteristics, including but not limited to voltage drops on switches and buses, pulse distortion due to delayed and unequal rise and fall times, and DC bus voltage drops. The method can be applied to any converter with two complementary switches in its configuration. Embodiments of this disclosure comprise three main parts. The first part uses a dead time value determined in the control and the load current to calculate the voltage deviation relative to a reference voltage and adds an appropriate compensation value to the reference signal. The second part has a controller, which may be a proportional-integral (PI), integral (I), or other error accumulator, and adds a compensation value to the reference waveform based on the difference between the actual voltage at the converter output and the reference voltage. This part compensates for output deviations caused by DC bus voltage oscillations, voltage drops on switches and buses, and other sources of deviation such as switch delays and distorted PWM pulses. If a particular converter does not have a sensor at the output, this part can use an approximate model of the system to calculate the compensation value. The third part is responsible for narrow pulse elimination and compensation for these eliminated pulses. The third part uses an integrator to accumulate the difference between the reference signal and the output signal after narrow pulse cancellation. A quantizer adds an appropriate value to the waveform after minimum pulse cancellation to compensate for the cancelled pulse without generating pulses with widths smaller than acceptable. This disclosure allows for the cancellation of short-width pulses and compensates for the effects of cancelling these pulses, as well as other non-ideal characteristics such as dead time, delay, pulse distortion, voltage drops on switches and buses, and DC link voltage oscillations. This helps reduce losses, extend lifespan, lower EMI, and improve output power quality.

[0016] Dead time and narrow pulse cancellation (NPE) can lead to distortion of the converter output voltage waveform and poor power quality. This is especially true in converters with high switching frequencies and / or large dead time intervals (e.g., but not limited to converters with wide bandgap devices and ARCP-based converters). To obtain an accurately synthesized voltage waveform and high power quality at the converter output, these distortions, as well as other distortions caused by nonlinearity and non-ideal characteristics, should be compensated for.

[0017] This paper describes a compensation method for narrow pulse cancellation. This method reduces losses, noise, and stress on power switches while maintaining the desired output voltage. It also enables higher DC link utilization, achieves a higher modulation index, and reduces output voltage distortion.

[0018] In some embodiments of this document, a method for compensating for dead time is provided, which can be performed in a system or circuit having a constant or variable dead time.

[0019] By using appropriate sensors or a system model at the converter output, the method described in this paper can also additionally compensate for output waveform deviations arising from non-ideal and / or nonlinear characteristics of the system, including but not limited to voltage drops across the switches and different rise / fall times of the switches.

[0020] For clarity, and where deemed appropriate, reference numerals may be repeated in the drawings to indicate corresponding or similar elements. Furthermore, numerous specific details are set forth to provide a thorough understanding of the embodiments described herein. However, those skilled in the art will understand that the embodiments described herein can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail so as not to obscure the embodiments described herein. It should first be understood that although exemplary embodiments are shown in the drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether currently known or unknown. This disclosure should in no way be limited to the exemplary implementations and techniques shown in the drawings and described below.

[0021] Unless the context otherwise requires, the various terms used throughout this specification shall be read and understood as follows: “or” as used throughout is inclusive, as if written as “and / or”; singular articles and pronouns as used throughout include their plural forms and vice versa; similarly, gender pronouns include their corresponding pronouns, and therefore the pronouns shall not be construed as limiting anything described herein to a single gender in terms of use, implementation, performance, etc.; “exemplary” shall be understood as “illustrative” or “exemplary”, and not necessarily “better” than other embodiments. Further definitions of terms may be set forth herein; these definitions will apply to prior and subsequent instances of these terms, as will become clear from reading this specification. It should also be noted that unless expressly stated otherwise, or unless the context clearly implies “an”, the use of the terms “a” or “an” shall in all cases be understood to mean “at least one”.

[0022] Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of this disclosure. For example, components of the systems and apparatuses may be integrated or separated. Furthermore, the operation of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Moreover, the steps may be performed in any suitable order. As used herein, "each" means each member of a set or each member of a subset of a set.

[0023] Figure 3A , Figure 3B and Figure 3C Block diagrams depicting different configurations of the systems and apparatus disclosed herein are provided. For example... Figure 3A , Figure 3B and Figure 3C As shown, embodiments may include one or more compensators, such as DTNIC and / or NPEC modules.

[0024] exist Figure 3A In this system 300a, there are application-level control system 340a, control section 330a, sensor section 320a, power section 310a, and gate driver section 350a. The control section 330a includes DTNIC 331a and modulator 333a.

[0025] exist Figure 3B In this system 300b, there are application-level control system 340b, control section 330b, sensor section 320b, power section 310b, and gate driver section 350b. The control section 330b includes NPEC 332b and modulator 333b.

[0026] exist Figure 3CIn this system 300c, the application-level control system 340c, the control section 330c, the sensor section 320c, the power section 310c, and the gate driver section 350c are included. The control section 330c includes a DTNIC 331c, an NPEC 332c, and a modulator 333c.

[0027] exist Figure 3A , Figure 3B and Figure 3C In this diagram, similar components are identified by similar reference numerals. Systems 300a, 300b, and 300c can be individually or collectively referred to as "System 300". Application-level control systems 340a, 340b, and 340c can be individually or collectively referred to as "Control System 340". Control sections 330a, 330b, and 330c can be individually or collectively referred to as "Control Section 330". Sensor sections 320a, 320b, and 320c can be individually or collectively referred to as "Sensor Section 320". Power sections 310a, 310b, and 310c can be individually or collectively referred to as "Power Section 310", and gate driver sections 350a, 350b, and 350c can be individually or collectively referred to as "Gate Driver Section 350". DTNIC 331a and 331c can be individually or collectively referred to as "DTNIC 331". NPEC 332b and 332c can be individually or collectively referred to as "NPEC ​​332". Modulators 333a, 333b, and 333c can be referred to individually or collectively as "modulator 333".

[0028] The power section 310 uses switches in a complementary state in its structure; these switches can be one or more switch arms (such as...). Figure 1 As shown, it can also be a structure with additional switches (such as an auxiliary resonant commutator (ARCP)) or a structure with multiple switches operating in complementary modes on a phase (such as a multilevel inverter). The sensor section 320 measures the required parameters, filters the measured parameters, and provides the necessary feedback to the depicted control system. The control section 330 uses the reference signal provided by the application-level control system 340 and modulates it at the gate of the power switch after applying protection and compensation measures through the gate driver section 350. If the required signal is already used in the application-level control system 340, a separate sensor section is not required and can be omitted.

[0029] In some embodiments (e.g.) Figure 3C In one embodiment, the control section 330 includes a DTNIC 331c, an NPEC section 332c, and a modulator 333c. In other embodiments (e.g.) Figure 3A In one embodiment, the control section 330 includes a DTNIC 331a and a modulator 333a. In other embodiments (e.g.) Figure 3BIn the embodiment, control section 330b includes NPEC section 332b and modulator 333b. Modulator 333b performs a pulse width modulation-based modulation method (including but not limited to sinusoidal pulse width modulation (SPWM) and space vector modulation (SVM)) that converts input analog waveforms (e.g., from a motor control algorithm) into equivalent digitally gated waveforms to control the power switching of the converter. For clarity, the order of the components constituting part of control section 330b is interchangeable.

[0030] Figure 4 A block diagram of an embodiment of a dead-time compensation system 400 and related methods is shown. In block 410, the average voltage deviation for the next PWM cycle is calculated based on the load current direction. In the two-level bridge arms (such as...) Figure 1 In the diagram (shown), this calculation is determined by the current direction. When the load current flows to the converter during the dead time interval, the high-side diode conducts. Therefore, if a transition occurs from the low-side switch to the high-side switch, the dead time has no effect on the output waveform, and the average deviation is zero. During the transition from the upper switch to the lower switch, since the upper switch is conducting, and the dead time is inserted by delaying the gate pulse of the switch to be turned on, there is +VDC / 2 at the output during the dead time duration, while the desired value is -VDC / 2, resulting in an average voltage deviation of +VDC. In other converter structures, the mechanism of block 410 should be modified accordingly. For example, although for soft-switching converters such as those with auxiliary resonant commutation poles, the voltage does not have the two-level shape of hard-switching converters, and the voltage change during the dead time is continuous, the average voltage deviation can be calculated using current values ​​and system parameters, or using the closed-loop control feedback signal described in U.S. Application US63524976, filed July 5, 2023, the contents of which are incorporated herein by reference.

[0031] In another embodiment, a model-based estimator can replace block 410. The method then calculates the volt-second quantity at block 420, considering a dead time duration that may be variable or constant, and subtracts an appropriate amount from the reference value at block 430 by considering the switching cycle. Adder block 440 adds a compensation voltage to the reference voltage waveform. By adding block 450 to this control section, deviations caused by DC link voltage oscillations can be compensated. In a multilevel inverter, this section should be modified to take corrective action based on internal parameters such as clamping point voltage or cell voltage. The signal is then passed to block 460. In this embodiment, block 460 is intended to be input to the NPEC; in other embodiments, block 460 may be a pulse generator.

[0032] Figure 5AA block diagram of system 500 and related methods is shown, wherein cancellation and compensation can be performed after the modulator, in which case cancellation and compensation are based on the actual pulse width. In this embodiment, the duty cycle value is a per-unit value, with the base value being the full duty cycle, meaning the full duty cycle is one time unit. In this case, in block 510, narrow pulses with a width less than the minimum permissible pulse width (MAPW) are cancelled. Since the switch of one bridge arm is in complementary mode, reference pulses with a width greater than (1 - MAPW) will also be saturated to a width value equal to (1 - MAPW). This eliminates narrow pulses on both the low-side and high-side switches.

[0033] Next, in block 520, the difference between the actual width of the reference pulse and the modified pulse width is calculated. Block 570 calculates the difference between the feedback of the output of 520 and the output of 540 to generate an error signal. In block 530, this error is accumulated. In block 540, the accumulated error is quantized into two values ​​such that adding these two values ​​to the modified pulse will not produce a pulse narrower than allowed on the high-side or low-side switch. When the accumulated error is positive, these values ​​are 0 or MAWP; when the accumulated error is negative, these values ​​are 0 or (-MAPW). These compensation values ​​(the output of the quantizer at block 540) are added to the modified reference pulse through block 550, clamping the output voltage to one of the DC link buses throughout the switching cycle and compensating for the error between the actual and modified reference pulses over a period of time depending on the modulation index. If the compensation value is added to the output, the negative feedback subtracts it from the error accumulator in block 560. Ultimately, the compensated value is used to generate trigger pulses in the controller's PWM module.

[0034] Figure 5BAnother embodiment of the NPEC system 500b is shown. Considering a certain average voltage (AV_MAPW) caused by MAWP, in block 510b, the reference waveform is saturated from the top and bottom to eliminate the occurrence of narrow pulses on the high-side and low-side switches. Depending on the modulation method, the region where narrow pulses occur may differ; for example, SVM has no narrow pulses at low modulation indices, while discontinuous PWM (DPWM) has narrow pulses at both low and high modulation indices. Therefore, block 510b can be modified according to the modulation method and the region where narrow pulses occur. Next, in block 520b, the difference between the actual reference signal and the modified reference signal is calculated. Block 570b calculates the difference between the feedback of the output of 520b and the output of 540b to generate an error signal. In block 530b, this error is accumulated. In block 540b, the accumulated error is quantized into two values ​​according to its sign, such that adding these two values ​​to the modified reference voltage does not produce a pulse narrower than the permissible value. For example, these values ​​are 0 or +AV_MAPW when the accumulated error is positive; and 0 or -AV_MAPW when the accumulated error is negative. This compensation signal (output of the quantizer in block 540b) is added to the modified reference waveform (output of block 510b) via block 550b, compensating for the error between the actual and modified reference signals over a period of time, depending on the modulation index. Negative feedback then subtracts the compensation signal from the error accumulator 570b. Finally, the compensated value is used in the modulator algorithm 560b (e.g., SVM).

[0035] Simultaneously increasing or decreasing the voltage of all phases has no effect on the load. This fact can also be used to eliminate narrow pulses without affecting the output waveform quality by eliminating the narrow pulse and adding the same duration to the pulses of other phases. However, this is not feasible in all cases. Therefore, in another embodiment, two-stage narrow pulse elimination can be used. If increasing the pulse width of other phases by an amount equal to the pulse width of the phase with the narrow pulse does not result in narrow pulses on those phases or a duty cycle exceeding 100%, then narrow pulse elimination is accomplished by simply eliminating the pulse with the smallest pulse width and subtracting the same duration from the pulse width of the other phases; otherwise, the algorithm shown in Figure 5 is run to eliminate and compensate for the narrow pulse.

[0036] The methods disclosed herein can improve converter performance and reliability by compensating for narrow pulses and compensating for dead time, DC link voltage oscillations, voltage drops on power switches and buses. While specific advantages are listed above, various embodiments may include some, exclude, or include all of these advantages. Any aspect or portion of any embodiment discussed in this specification may be implemented in combination with or in conjunction with any other aspect or portion of any embodiment discussed in this specification. Although specific embodiments have been described above, it should be understood that other embodiments are possible and intended to be included herein. Modifications and adjustments can be apparent to those skilled in the art to the embodiments not shown above.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, any references cited herein should not be construed as an admission that such references are prior art to this disclosure.

[0038] Those skilled in the art will understand that many other possible alternative implementations and modifications exist, and the examples above are merely illustrative of one or more implementations. The scope of the claims should not be limited to the exemplary embodiments set forth herein, but should be given the broadest interpretation consistent with the description throughout the specification.

Claims

1. A system for eliminating narrow pulses from a power converter, compensating for the effects of eliminating the narrow pulses from the power converter, and outputting a desired voltage, the system comprising: The sensor section is used to sense the electrical characteristics of a structure comprising two semiconductor devices arranged to switch in a complementary mode. The control section includes a modulator, which is in electrical communication with the sensor section and the structure, and is capable of synthesizing a reference waveform (V) based on one or more of dead time, minimum acceptable pulse width (MAPW), and desired pulse width. ref ); as well as The compensation portion, which is used to compensate V ref Add or subtract a compensation value to compensate the reference waveform V ref Relative to the desired voltage V o The deviation is used to output the desired voltage V. o Equivalent compensation voltage.

2. The system according to claim 1, wherein, The electrical characteristics include one or more of the load current, phase voltage, and DC link voltage.

3. The system according to claim 1, wherein, The control unit includes at least one of the following: Dead time and non-ideal characteristic compensation (DTNIC) module, and Narrow Pulse Elimination and Compensation (NPEC) module.

4. The system according to claim 3, wherein, The control section includes the dead time and non-ideal characteristic compensation (DTNIC) module.

5. The system according to claim 3, wherein, The control section includes the Narrow Pulse Elimination and Compensation (NPEC) module.

6. The system according to claim 1, wherein, The control unit sends one or more instructions to a gate driver that is in electrical communication with one or more gates of the semiconductor device.

7. A method for eliminating narrow pulses generated in a converter, the method comprising: Receive reference minimum acceptable pulse width (MAPW); A narrow pulse width detector is used to detect narrow pulses with a width narrower than the MAPW; Eliminate the narrow pulse; Use an accumulator to accumulate the value of the eliminated narrow pulse; as well as The quantizer is used to modify the pulses in the converter's output waveform based on the accumulated value in the accumulator to compensate for the eliminated pulses. Wherein, the width of each pulse of the output waveform is greater than or equal to the MAPW.

8. The method according to claim 7, wherein, The output waveform is fed to a pulse generator.

9. The method according to claim 7, wherein, The output waveform is fed to the Narrow Pulse Elimination and Compensation (NPEC) module.

10. The method according to claim 7, wherein, The narrow pulse detector detects the narrow pulse directly from the reference voltage waveform.

11. A method for compensating dead time in a converter, the method comprising: The converter receives dead time values, load current, and current direction from a structure comprising two semiconductor devices arranged to switch in a complementary mode. The compensation voltage is calculated based on one or more of the dead time value, the load current, and the current direction; and The reference voltage is modified based on the compensation voltage.

12. The method according to claim 11, wherein, The calculation of the compensation voltage includes using the average voltage deviation calculated in the previous cycle.

13. The method according to claim 11, wherein, The calculation of the compensation voltage includes the use of a model-based estimator.

14. The method according to claim 11, wherein, The modification of the reference voltage includes using an adder to add the compensation voltage to the reference voltage.

15. A two-stage narrow pulse cancellation and compensation method, comprising: The first stage is used to eliminate narrow pulses with a duration W narrower than the minimum acceptable pulse width (MAPW) and to subtract the same duration W from the pulse width of other phases. as well as The second stage, comprising the method according to claim 7; Specifically, the first stage is used when it is determined that eliminating a narrow pulse with a duration W will not result in a narrow pulse appearing on the phase or cause the duty cycle to exceed 100%; otherwise, the second stage is used.

16. A zero-voltage switching converter, comprising: The system according to any one of claims 1 to 6; The structure includes two semiconductor devices arranged to switch in a complementary mode; as well as An auxiliary circuit that communicates with the structure to allow zero-voltage switching.

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