Method of predicting remaining life of a non-volatile memory device and storage device

Abstract

Methods of predicting a remaining life of a non-volatile memory device and a storage device performing the same are provided. In a method of predicting a remaining life of a non-volatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, at least one of the plurality of read operations being sequentially performed until read data stored in the non-volatile memory device is successfully obtained. A sequence class and error correction code (ECC) decoding information are generated. A life phase of the non-volatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When the non-volatile memory device is determined to correspond to a first life phase, a coarse prediction of the remaining life of the non-volatile memory device is performed. When the non-volatile memory device is determined to correspond to a second life phase after the first life phase, a fine prediction of the remaining life of the non-volatile memory device is performed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0181856, filed on December 23, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to a method for predicting the remaining lifetime of a non-volatile memory device and a memory device for performing the method. Background Technology

[0004] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices based on whether the stored data is lost when power is off. Volatile memory devices have faster read and write speeds; however, the stored data is lost when power is not supplied. On the other hand, non-volatile memory devices retain stored data even when power is not supplied. Therefore, non-volatile memory devices are used to store data that needs to be preserved, regardless of whether power is supplied. With the widespread use of non-volatile memory devices, various methods for predicting the remaining lifetime of non-volatile memory devices have been studied. Summary of the Invention

[0005] At least some exemplary embodiments of the present invention can provide a method and apparatus for non-volatile memory devices that can improve the speed and accuracy of predicting the remaining lifetime of non-volatile memory devices.

[0006] According to at least some exemplary embodiments conceived in this invention, a method for predicting the remaining lifetime of a non-volatile memory device is provided. The method includes: iteratively performing one or more read operations until read data stored in the non-volatile memory device is successfully obtained; generating sequence category and error correction code (ECC) decoding information, the sequence category corresponding to a successful read operation, the successful read operation being one of the one or more read operations based on its successful acquisition of the read data; determining a lifetime stage of the non-volatile memory device based on at least one of the sequence category and the ECC decoding information; in response to determining that the non-volatile memory device corresponds to a first lifetime stage, performing a coarse prediction of the remaining lifetime of the non-volatile memory device based on the sequence category and the ECC decoding information; and in response to determining that the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, performing a fine prediction of the remaining lifetime of the non-volatile memory device based on the sequence category, the ECC decoding information, and threshold voltage information of the non-volatile memory device.

[0007] According to at least some exemplary embodiments of the present invention, a storage device includes: a non-volatile memory device and a storage controller processor configured to control the non-volatile memory device, wherein the storage controller processor is further configured to: iteratively execute one or more read operations until read data stored in the non-volatile memory device is successfully obtained; generate sequence category and error correction code (ECC) decoding information, the sequence category corresponding to a successful read operation, the successful read operation being a read operation among the one or more read operations based on its successful acquisition of the read data; determine a lifetime stage of the non-volatile memory device based on at least one of the sequence category and the ECC decoding information; in response to determining that the non-volatile memory device corresponds to a first lifetime stage, perform a coarse prediction of the remaining lifetime of the non-volatile memory device based on the sequence category and the ECC decoding information; and in response to determining that the non-volatile memory device corresponds to a second lifetime stage after the first lifetime stage, perform a fine prediction of the remaining lifetime of the non-volatile memory device based on the sequence category, the ECC decoding information, and threshold voltage information of the non-volatile memory device.

[0008] In the method for predicting the remaining lifetime of a non-volatile memory device according to at least some exemplary embodiments of the present invention, the remaining lifetime of the non-volatile memory device can be determined efficiently. When it is determined that the non-volatile memory device corresponds to a first lifetime stage, only a coarse prediction is performed; when it is determined that the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, a fine prediction, which is more accurate than the coarse prediction, is performed. That is, by adaptively performing different predictions according to the lifetime stage of the non-volatile memory device, the speed and accuracy of the prediction can be improved. Attached Figure Description

[0009] The above and other features and advantages of the exemplary embodiments of the inventive concept will become more readily understood by referring to the accompanying drawings. The drawings are intended to depict exemplary embodiments of the inventive concept and should not be construed as limiting the intended scope of the claims. Unless explicitly stated otherwise, the drawings should not be considered to be drawn to scale.

[0010] Figure 1 This is a flowchart illustrating a method for predicting the remaining lifetime of a non-volatile storage device according to at least some exemplary embodiments of the present invention.

[0011] Figure 2 This is a block diagram illustrating a non-volatile storage device and a storage device including the non-volatile storage device, based on at least some exemplary embodiments of the concept according to the present invention.

[0012] Figure 3This is a block diagram illustrating at least some exemplary embodiments of a non-volatile storage device according to the present invention.

[0013] Figure 4 It is shown Figure 3 A perspective view of an example of a memory block included in a memory cell array of a non-volatile memory device.

[0014] Figure 5 It is shown Figure 4 The circuit diagram of the equivalent circuit of the storage block.

[0015] Figure 6 It is shown as Figure 2 A block diagram of an example storage controller included in a storage device.

[0016] Figure 7 and Figure 8 It is shown Figure 1 A flowchart of an example embodiment of multiple read operations.

[0017] Figure 9 and Figure 10 It is shown Figure 7 and Figure 8 A flowchart of an example embodiment of multiple read operations.

[0018] Figure 11 It is shown Figure 1 A flowchart of an example embodiment for determining the lifetime stage of a non-volatile storage device.

[0019] Figure 12 and Figure 13 It is used to describe Figure 11 A diagram illustrating the process of determining the lifetime stages of a non-volatile storage device.

[0020] Figure 14 It is shown Figure 1 A flowchart of an example embodiment for determining the lifetime stage of a non-volatile storage device.

[0021] Figure 15 It is used to describe Figure 14 A diagram illustrating the process of determining the lifetime stages of a non-volatile storage device.

[0022] Figure 16 and Figure 17 It is used to describe Figure 1 A diagram illustrating the coarse and fine predictions for the execution of non-volatile memory devices.

[0023] Figure 18 and Figure 19 It is used to describe Figure 1 A diagram showing the threshold voltage information.

[0024] Figure 20 , Figure 21 and Figure 22 It is shown as Figure 1 An illustration of an artificial neural network used as an example of an AI model for predicting the remaining lifetime of non-volatile storage devices.

[0025] Figure 23 This is a block diagram illustrating at least some exemplary embodiments of a storage device and a storage system including the storage device according to a concept of the present invention. Detailed Implementation

[0026] As is customary in the field of this invention, embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of an embodiment can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0027] Figure 1 This is a flowchart illustrating a method for predicting the remaining lifetime of a non-volatile storage device according to at least some exemplary embodiments of the present invention.

[0028] Reference Figure 1 A method for predicting the remaining lifetime of a non-volatile memory device is performed by a memory controller that controls the non-volatile memory device, which comprises multiple memory cells. The structure of a memory system including the non-volatile memory device and the memory controller, and the corresponding memory device, will be described later. Figures 2 to 6 as well as Figure 23 Describe it.

[0029] In the method for predicting remaining lifetime, a read sequence (S100) comprising multiple read operations is executed. For example, as will be referred to below at least... Figures 7 to 10 and Figures 12 to 13 In more detail, operation S100 may include iteratively performing one or more read operations until the read data stored in the non-volatile storage device is successfully retrieved based on one of the read operations. Therefore, according to at least some exemplary embodiments of the invention, the read sequence may include 1 to n read operations, depending on the number of read operations that occur before the data, the target of the read operation, is successfully retrieved, where n is a positive integer greater than 1. Furthermore, the read operation among the one or more iteratively performed read operations that successfully retrieves the data stored in the non-volatile storage device may be referred to herein as a successful read operation.

[0030] According to at least some exemplary embodiments of the present invention, read data can be stored in a region of a non-volatile storage device. For example, read data can be stored in a page comprising multiple memory cells included in a non-volatile storage device.

[0031] According to at least some exemplary embodiments of the present invention, a read sequence can be executed to obtain read data stored in a region of a non-volatile memory device. For example, a read sequence can be executed to obtain first read data stored in a first region of the non-volatile memory device. After successfully obtaining the first read data, the read sequence can be executed again to obtain second read data stored in a second region different from the first region. (Refer to...) Figures 7 to 10 Describe the sequence to be read.

[0032] Generate sequence class and error correction code (ECC) decoding information (S200). The sequence class corresponds to the successful read operation among multiple read operations through which the read data was successfully obtained.

[0033] According to at least some exemplary embodiments of the present invention, multiple read operations can each correspond to multiple sequence categories. For example, when data is successfully obtained through a successful read operation, even if two or more read operations are performed, a single sequence category corresponding to the successful read operation can be determined.

[0034] According to at least some exemplary embodiments of the present invention, ECC decoding information can be generated corresponding to multiple read operations. For example, when two or more read operations are performed, two or more ECC decoding information can be generated corresponding to each of the multiple read operations.

[0035] The lifetime stage of the non-volatile storage device is determined based on at least one of the sequence type and ECC decoding information (S300).

[0036] According to at least some exemplary embodiments of the present invention, the lifetime phase of a non-volatile memory device may include a first lifetime phase and a second lifetime phase following the first lifetime phase. The first lifetime phase may correspond to the period between a first time point and a second time point. The first time point may be the time at which the non-volatile memory device is manufactured, and the second time point may be any time point between the first time point and a third time point at the end of the entire lifetime of the non-volatile memory device. The second lifetime phase may correspond to the period between the second time point and the third time point.

[0037] According to at least some exemplary embodiments of the present invention, the lifetime stages of a non-volatile memory device can be divided into an early stage, a mid-stage, and a late stage. For example, a first lifetime stage may correspond to the early stage, and a second lifetime stage may correspond to the mid-stage and the late stage. Figure 1 In the example, the lifetime stages of a non-volatile memory device can be described by dividing it into a first lifetime stage and a second lifetime stage. (Referring to...) Figure 16 and Figure 17 In the examples described, the lifetime stages of a non-volatile storage device can be described by dividing them into early, mid, and late stages.

[0038] When it is determined that the non-volatile memory device corresponds to the first lifetime stage (S300: Yes), a coarse prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category and ECC decoding information (S400). When it is determined that the non-volatile memory device corresponds to the second lifetime stage after the first lifetime stage (S300: No), a fine prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category, ECC decoding information, and the threshold voltage information of the non-volatile memory device (S500).

[0039] According to at least some exemplary embodiments of the invention, fine prediction can perform predictions of the remaining lifetime of non-volatile memory devices more accurately than coarse prediction.

[0040] According to at least some exemplary embodiments of the present invention, a coarse prediction can be determined based on sequence category and ECC decoding information, and a fine prediction can be determined based not only on sequence category and ECC decoding information but also on threshold voltage information of non-volatile memory devices.

[0041] According to at least some example embodiments of the present invention, coarse and fine predictions can be performed by or using an artificial intelligence (AI) model. According to at least some example embodiments of the present invention, the AI ​​model can be pre-learned before performing steps S100, S200, S300, S400, and S500.

[0042] According to at least some exemplary embodiments of the present invention, the AI ​​model can be one of the following: a neural network-based system (e.g., convolutional neural network (CNN) and recurrent neural network (RNN)), support vector machine (SVM), linear regression, logistic regression, Naive Bayes classification, random forest, decision tree and k-nearest neighbor (KNN) algorithm, but the present disclosure is not limited thereto.

[0043] According to at least some exemplary embodiments of the present invention, sequence category, ECC decoding information, and threshold voltage information can be input as input data to an AI model. According to at least some exemplary embodiments of the present invention, feature values ​​extracted from each of the sequence category, ECC decoding information, and threshold voltage information can be input as input data to an AI model.

[0044] According to at least some exemplary embodiments of the present invention, the sequence category may include an index value corresponding to a successful read operation, and the ECC decoding information may include the number of error bits calculated as a result of performing ECC decoding on the read data. The threshold voltage information may include the difference between a first threshold voltage distribution and a second threshold voltage distribution. The first threshold voltage distribution can be measured immediately after the read data is programmed into a memory cell included in a non-volatile memory device. The second threshold voltage distribution can be measured immediately after successfully obtaining the read data.

[0045] According to at least some exemplary embodiments of the present invention, when the time point at which the lifetime stage of a non-volatile memory device is determined exceeds a predetermined time or optionally a desired time from the time point at which the non-volatile memory device is manufactured, only fine prediction may be performed instead of coarse prediction.

[0046] In the method for predicting the remaining lifetime of a non-volatile storage device according to the example embodiment, the remaining lifetime of the non-volatile storage device can be effectively determined by performing steps S100, S200, S300, S400 and S500.

[0047] When a non-volatile memory device is determined to correspond to a first lifetime stage, a coarse prediction can be performed. When the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, a fine prediction, which is more accurate than the coarse prediction, can be performed. Therefore, by adaptively performing either coarse or fine prediction based on the lifetime stage of the non-volatile memory device, the speed and accuracy of prediction can be improved.

[0048] Figure 2 This is a block diagram illustrating a non-volatile storage device and a storage device including the non-volatile storage device, based on at least some exemplary embodiments of the concept according to the present invention.

[0049] Reference Figure 2 The storage device 10 includes a memory controller 20 and a non-volatile storage device 40. The storage device 10 may also include multiple signal lines 30 electrically connected between the memory controller 20 and the non-volatile storage device 40.

[0050] The memory controller 20 provides overall control over the operation of the non-volatile storage device 40. For example, the memory controller 20 may be based on data from a host device (e.g., Figure 23 The request of 1100 in the middle is to write (e.g., program) data to or read data from the non-volatile storage device 40.

[0051] The multiple signal lines 30 may include control lines, command lines, address lines, data lines, and power lines.

[0052] According to at least some exemplary embodiments of the present invention, the memory controller 20 can send commands (CMD), addresses (ADDR), and control signals (CTRL) to the non-volatile memory device 40 via command lines, address lines, and control lines. The memory controller 20 can send and receive data signals (DAT) with the non-volatile memory device 40 via data lines. The memory controller 20 can provide a power supply voltage (PWR) to the non-volatile memory device 40 via power lines. Although not shown, the plurality of signal lines 30 may also include a DQS line for transmitting data strobe signals (e.g., DQS signals). Some or all of the signal lines 30 may be referred to as a channel.

[0053] Figure 3 This is a block diagram illustrating at least some exemplary embodiments of a non-volatile storage device according to the present invention.

[0054] Reference Figure 3 The non-volatile storage device 100 includes a memory cell array 110, an address decoder 120, a page buffer circuit 130, a data input / output (I / O) circuit 140, a voltage generator 150, and a control circuit 160.

[0055] The memory cell array 110 is connected to the address decoder 120 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 110 is also connected to the page buffer circuitry 130 via multiple bit lines (BL). The memory cell array 110 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). The memory cell array 110 may be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each memory block comprising memory cells. Furthermore, each of the multiple memory blocks BLK1, BLK2, ..., BLKz may be divided into multiple pages.

[0056] In some example embodiments, such as referring to Figure 4 and Figure 5 As described, the memory cell array 110 can be a three-dimensional (3D) memory cell array formed on a substrate in a three-dimensional structure (or vertical structure). In this example, the memory cell array 110 may include a plurality of vertically oriented cell strings (e.g., a plurality of vertical NAND strings) such that at least one memory cell is situated on top of another memory cell.

[0057] The control circuit 160 receives commands CMD and addresses ADDR from an external source (e.g., from a memory controller) and controls erase, program, and read operations of the non-volatile memory device 100 based on the commands CMD and ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0058] For example, control circuit 160 can generate control signal CON for controlling voltage generator 150, and can generate control signal PBC for controlling page buffer circuit 130 based on command CMD, and can generate row address R_ADDR and column address C_ADDR based on address ADDR. Control circuit 160 can provide row address R_ADDR to address decoder 120 and column address C_ADDR to data I / O circuit 140.

[0059] Control circuit 160 can execute reference Figure 1 The method described herein is for predicting the remaining lifetime of a non-volatile storage device according to at least some example embodiments of the invention.

[0060] Address decoder 120 can be connected to memory cell array 110 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0061] For example, in a data erase / write / read operation, the address decoder 120 can determine at least one word line among multiple word lines WL as the selected word line based on the row address R_ADDR, and can determine the remaining word lines or unselected word lines among multiple word lines WL other than the selected word line as unselected word lines.

[0062] Furthermore, during data erase / write / read operations, the address decoder 120 can determine at least one of the multiple string select lines SSL as the selected string select line based on the row address R_ADDR, and can determine the remaining string select lines or unselected string select lines among the multiple string select lines other than the selected string select line.

[0063] Furthermore, during data erase / write / read operations, the address decoder 120 can determine at least one of the multiple ground selection lines GSL as the selected ground selection line based on the row address R_ADDR, and can determine the remaining ground selection lines or unselected ground selection lines in the multiple ground selection lines GSL other than the selected ground selection line as unselected ground selection lines.

[0064] Voltage generator 150 can generate the voltage VS required for the operation of non-volatile memory device 100 based on power supply PWR and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 120. Furthermore, voltage generator 150 can generate the erase voltage VERS required for data erase operations based on power supply PWR and control signal CON. Erasing voltage VERS can be applied directly or via bit line BL to memory cell array 110.

[0065] For example, during an erase operation, voltage generator 150 can apply an erase voltage VERS to the common source line and / or bit line BL of the memory block (e.g., a selected memory block), and can apply an erase permission voltage (e.g., ground voltage) to all or some word lines of the memory block via address decoder 120. Furthermore, during an erase verification operation, voltage generator 150 can apply an erase verification voltage VEVFY simultaneously to all word lines of the memory block, or sequentially to word lines one by one.

[0066] For example, during programming operations, voltage generator 150 can apply a programming voltage to a selected word line via address decoder 120, and can apply a programming pass voltage to an unselected word line. Furthermore, during programming verification operations, voltage generator 150 can apply a programming verification voltage to a selected word line via address decoder 120, and can apply a verification pass voltage to an unselected word line.

[0067] Furthermore, during normal read operations, voltage generator 150 can apply a read voltage to the selected word line via address decoder 120, and can also apply a read pass voltage to the unselected word line. During data recovery read operations, voltage generator 150 can apply a read voltage to the word line adjacent to the selected word line via address decoder 120, and can also apply a recovery read voltage to the selected word line.

[0068] Page buffer circuitry 130 can be connected to memory cell array 110 via multiple bit lines BL. Page buffer circuitry 130 may include multiple page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines.

[0069] Page buffer circuit 130 can store data DAT to be programmed into memory cell array 110 or can read data DAT sensed from memory cell array 110. In other words, depending on the operating mode of non-volatile memory device 100, page buffer circuit 130 can operate as a write driver or a sense amplifier.

[0070] Data I / O circuit 140 can be connected to page buffer circuit 130 via data line DL. Based on column address C_ADDR, data I / O circuit 140 can provide data DAT from outside non-volatile memory device 100 to memory cell array 110 via page buffer circuit 130, or can provide data DAT from memory cell array 110 to outside non-volatile memory device 100.

[0071] Figure 4 yes Figure 3 A perspective view of an example of a memory block included in a memory cell array of a non-volatile memory device.

[0072] Reference Figure 4 The memory block BLKi includes multiple cell strings (e.g., multiple vertical NAND strings) formed on a substrate in a three-dimensional structure (or vertical structure). The memory block BLKi includes a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0073] A substrate 111 is provided. For example, a well containing a first type of charge carrier impurity (e.g., a first conductivity type) may be present in the substrate 111. For example, the substrate 111 may have a p-well formed by implanting a Group 3 element such as boron (B). Specifically, the substrate 111 may have a bag-shaped p-well disposed within an n-well. In at least one exemplary embodiment of the invention, the substrate 111 has a p-type well (or a p-type bag-shaped well). However, the conductivity type of the substrate 111 is not limited to p-type.

[0074] A plurality of doped regions 311, 312, 313, and 314 arranged along a second direction D2 are disposed in / on a substrate 111. These plurality of doped regions 311 to 314 may have a second type of charge carrier impurity (e.g., a second conductivity type) different from a first type of the substrate 111. In at least one exemplary embodiment of the invention, the first to fourth doped regions 314 may be n-type. However, the conductivity type of the first to fourth doped regions 314 is not limited to n-type.

[0075] A plurality of insulating materials 112 extending along a first direction D1 are sequentially disposed along a third direction D3 on the region between a first doped region 311 and a second doped region 312 of a substrate 111. For example, the plurality of insulating materials 112 are arranged to be spaced at a specific distance along the third direction D3. For example, the insulating materials 112 may include insulating materials such as oxide layers.

[0076] Multiple pillars 113 penetrating the insulating material along a third direction D3 are sequentially disposed in the region between the first doped region 311 and the second doped region 312 of the substrate 111 along a first direction D1. For example, the multiple pillars 113 penetrate the insulating material 112 to contact the substrate 111.

[0077] In some exemplary embodiments, each pillar 113 may comprise a variety of materials. For example, the channel layer 114 of each pillar 113 may comprise a silicon material having a first conductivity type. For example, the channel layer 114 of each pillar 113 may comprise a silicon material having the same conductivity type as the substrate 111. In at least one exemplary embodiment of the present invention, the channel layer 114 of each pillar 113 comprises p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0078] The internal material 115 of each column 113 includes an insulating material. For example, the internal material 115 of each column 113 may include an insulating material such as silicon oxide. In some examples, the internal material 115 of each column 113 may include an air gap. As discussed herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0079] An insulating layer 116 is disposed in the region between the first doped region 311 and the second doped region 312 along the exposed surfaces of the insulating material 112, the pillars 113, and the substrate 111. For example, as shown, the insulating layer 116 disposed on the surface of the insulating material 112 may be located between the pillars 113 and a plurality of stacked first conductive materials 211, 221, 231, 241, 251, 261, 271, 281, and 291. In some examples, the insulating layer 116 does not need to be disposed between the pillars 113 and the first conductive materials 211 to 291 corresponding to the ground select line GSL (e.g., 211) and the string select line SSL (e.g., 291). In this example, the ground select line GSL is the bottommost first conductive material among the stacked first conductive materials 211 to 291, and the string select line SSL is the topmost first conductive material among the stacked first conductive materials 211 to 291.

[0080] In the region between the first doped region 311 and the second doped region 312, a plurality of first conductive materials 211 to 291 are disposed on the surface of the insulating layer 116. For example, the first conductive material 211 extending along the first direction D1 is disposed between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, the first conductive material 211 extending along the first direction D1 is disposed between the insulating layer 116 located at the bottom of the insulating material 112 adjacent to the substrate 111 and the substrate 111.

[0081] A first conductive material extending along the first direction D1 is disposed between an insulating layer 116 located at the top of a specific insulating material and an insulating layer 116 located at the bottom of a specific insulating material within the insulating material 112. For example, a plurality of first conductive materials 221 to 281 extending along the first direction D1 are disposed between the insulating materials 112, and it can be understood that the insulating layer 116 is disposed between the insulating material 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 may be formed of a conductive metal, but in other embodiments of the invention, the first conductive materials 211 to 291 may include a conductive material such as polycrystalline silicon.

[0082] A structure identical to that on the first doped region 311 and the second doped region 312 can be provided in the region between the second doped region 312 and the third doped region 313. In the region between the second doped region 312 and the third doped region 313, a plurality of insulating materials 112 are provided, extending along a first direction D1. Furthermore, a plurality of pillars 113 are provided, sequentially arranged along the first direction D1, and penetrating the plurality of insulating materials 112 along a third direction D3. An insulating layer 116 is provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 211 to 291 extend along the first direction D1. Similarly, a structure identical to that on the first doped region 311 and the second doped region 312 can be provided in the region between the third doped region 313 and the fourth doped region 314.

[0083] Multiple drain regions 320 are respectively disposed on multiple pillars 113. The drain regions 320 may comprise silicon material doped with a second type of charge carrier impurity. For example, the drain regions 320 may comprise silicon material doped with an n-type dopant. In at least one exemplary embodiment of the present invention, the drain regions 320 comprise n-type silicon material. However, the drain regions 320 are not limited to n-type silicon material.

[0084] On the drain region, a plurality of second conductive materials 331, 332, and 333 are disposed, extending along a second direction D2. The second conductive materials 331 to 333 are spaced apart from each other along a first direction D1. The second conductive materials 331 to 333 are respectively connected to the drain region 320 in their respective regions. The drain region 320 and the second conductive materials 333 extending along the second direction D2 can be connected via each contact plug. For example, each contact plug can be a conductive plug formed of a conductive material such as metal. The second conductive materials 331 to 333 may include metallic materials. The second conductive materials 331 to 333 may include conductive materials such as polycrystalline silicon.

[0085] exist Figure 4 In the example, first conductive materials 211 to 291 can be used to form word lines WL, serial select lines SSL, and ground select lines GSL. For example, first conductive materials 221 to 281 can be used to form word lines WL, wherein conductive materials belonging to the same layer can be interconnected. Second conductive materials 331 to 333 can be used to form bit lines BL. The number of layers of first conductive materials 211 to 291 can be varied depending on the process and control technology.

[0086] Figure 5 It is shown Figure 4 The circuit diagram of the equivalent circuit of the storage block.

[0087] Figure 5 It shows a reference. Figure 4 The circuit diagram of the equivalent circuit of the described memory block.

[0088] Figure 5 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0089] Reference Figure 5 The memory block BLKi may include multiple NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each NAND string NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST. For example, bit lines BL1 to BL3 may correspond to... Figure 4 The second conductive materials 331 to 333 in the common source line CSL can be interconnected. Figure 4 The first doped region 311 to the fourth doped region 314 are formed in the middle.

[0090] Each string select transistor (SST) can be connected to a corresponding string select line (SSL1, SSL2, and SSL3). Multiple memory cells MC1 to MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground select transistor (GST) can be connected to a corresponding ground select line (GSL1, GSL2, and GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1 to BL3), and each ground select transistor (GST) can be connected to the common source line CSL. Figure 5 In the example, some string select transistors SST are connected to the same bit line (e.g., one of BL1 to BL3) to connect the corresponding NAND strings to the same bit line for proper selection via selection voltages applied to the appropriate string select lines SSL1 to SSL3 and ground select lines GSL1 to GSL3.

[0091] Cell strings connected to a single bit line can form a column, and cell strings connected to a single string select line can form a row. For example, cell strings NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, and cell strings NS11, NS12, and NS13 connected to the first string select line SSL1 can form the first row.

[0092] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separate. Memory cells located on the same semiconductor layer share a single word line. Strings of cells in the same row share a string select line. The common source line CSL is connected to all cell strings.

[0093] exist Figure 5 In the example, memory block BLKi is shown connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, and NAND strings NS11 to NS33 are each shown to include eight memory cells MC1 to MC8. However, the example embodiment is not limited to this. In some example embodiments, each memory block may be connected to any number of word lines and bit lines, and each NAND string may include any number of memory cells.

[0094] A three-dimensional vertical array structure may include vertically oriented vertical NAND strings, such that at least one memory cell is situated above another memory cell. At least one memory cell may include a charge trapping layer. Suitable configurations of memory cell arrays including 3D vertical array structures are described by reference in their entirety in the following patent documents: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0095] Although the array of memory cells included in at least some exemplary embodiments of the non-volatile memory device according to the present invention is described based on NAND flash memory devices, the non-volatile memory device according to at least some exemplary embodiments of the present invention can be any non-volatile memory device, such as phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.

[0096] Figure 6 It is shown as Figure 2 A block diagram of an example memory controller included in a storage device.

[0097] Reference Figure 6 The storage controller 400 may include a storage controller processor 410, a memory 420, a remaining lifetime predictor 430, a host interface (I / F) 440, an ECC engine 450, a memory interface 460, and an Advanced Encryption Standard (AES) engine 470.

[0098] According to at least some exemplary embodiments of the present invention, the storage controller processor 410 may be or may include: hardware including logic circuitry; a hardware / software combination executing software; or a combination thereof. For example, the storage controller processor 410 may more specifically include, but is not limited to, one or more of the following: a central processing unit (CPU), a processor core, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The storage controller processor 410 may be configured via hardware and / or software (e.g., firmware) to perform and / or control any operations described in the specification performed by the storage controller processor, storage controller, storage device, or its components (e.g., memory 420, remaining lifetime predictor 430, host interface 440, ECC engine 450, memory interface 460, and / or Advanced Encryption Standard (AES) engine 470). Furthermore, any or all of the remaining lifetime predictor 430, host interface 440, ECC engine 450, memory interface 460, and AES engine 470 of the storage controller 400 can be implemented by one or more circuits or circuit systems. Therefore, the ECC engine 450, memory interface 460, AES engine 470, and storage controller 400 may be referred to in this specification as ECC engine circuit 450, memory interface circuit 460, AES engine circuit 470, and storage controller circuit 400, respectively.

[0099] Storage controller processor 410 can respond to data from a host device (e.g., via host interface 440) Figure 23 The storage controller processor 410 receives commands to control the operation of the storage controller 400. For example, the storage controller processor 410 can control storage devices (e.g., storage devices, storage controllers ... Figure 2 The storage controller processor 410 can additionally perform the operations described above (referring to 10), and components 420, 430, 440, 450, 460, and 470 can be controlled by employing firmware for driving storage device 10. Figure 1 S100 is described.

[0100] Memory 420 may store instructions and data executed and processed by memory controller processor 410. For example, memory 420 may be implemented as volatile memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0101] The memory 420 may store various types of data necessary for performing a method for predicting the remaining lifetime of a non-volatile memory device according to at least some example embodiments of the present invention.

[0102] The remaining lifetime predictor 430 may include multiple components for performing a method of predicting the remaining lifetime of a non-volatile memory device according to at least some example embodiments of the present invention. For example, the remaining lifetime predictor 430 may include an information collection circuit ICC 432, a lifetime stage determination circuit LSDC 434, and a remaining lifetime prediction circuit RLPC 436.

[0103] According to at least some exemplary embodiments of the invention, the storage controller processor 410 can execute a read sequence comprising multiple read operations. For example, one or more read operations can be executed iteratively until read data stored in the non-volatile storage device is successfully obtained based on one of the read operations.

[0104] According to at least some exemplary embodiments of the present invention, the information collection circuit 432 can generate sequence category and ECC decoding information. The sequence category can correspond to a successful read operation in which data was successfully obtained among multiple read operations.

[0105] According to at least some exemplary embodiments of the present invention, the lifetime stage determination circuit 434 can determine the lifetime stage of a non-volatile memory device based on at least one of sequence category and ECC decoding information.

[0106] According to at least some exemplary embodiments of the present invention, when it is determined that the non-volatile memory device corresponds to a first lifetime stage, the remaining lifetime prediction circuit 436 can perform a coarse prediction of the remaining lifetime of the non-volatile memory device based on the sequence type and ECC decoding information. When it is determined that the non-volatile memory device corresponds to a second lifetime stage after the first lifetime stage, the remaining lifetime prediction circuit 436 can perform a fine prediction of the remaining lifetime of the non-volatile memory device based on the sequence type, ECC decoding information, and threshold voltage information of the non-volatile memory device.

[0107] According to at least some exemplary embodiments of the invention, part or all of the remaining lifetime predictor 430 may be implemented in hardware or in software (e.g., a program).

[0108] The ECC engine 450 for error correction can perform ECC encoding and ECC decoding by means of or using coding modulation such as Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, Turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), or other error-correcting codes.

[0109] Host interface 440 can provide host devices (e.g., Figure 23The physical connection between the host interface 440 (1100) and the storage device 10. That is, the host interface 440 can provide interface communication with the storage device 10 in response to the bus format of the host device.

[0110] According to at least some exemplary embodiments of the present invention, the bus format of the host device may be SCSI or SAS. According to at least some exemplary embodiments of the present invention, the bus format of the host device may be USB, PCIe Fast Peripheral Component Interconnect (PCIe), ATA, PATA, SATA, NVMe, etc.

[0111] Memory interface 460 can be with Figure 2 The memory interface 460 exchanges data with the non-volatile storage device 40. The memory interface 460 can send data to the non-volatile storage device 40 and can receive data read from the non-volatile storage device 40. For example, the memory interface 460 can be implemented to conform to standard protocols such as Toggle or ONFI.

[0112] The AES engine 470 can use a symmetric key algorithm to perform at least one of encryption and decryption operations on data input to the storage controller 400. Although not described in detail, the AES engine 470 may include an encryption module and a decryption module. According to at least some exemplary embodiments of the present invention, the encryption module and the decryption module may be implemented as separate modules or as a single module.

[0113] Figure 7 and Figure 8 It is shown Figure 1 A flowchart of an example embodiment of multiple read operations.

[0114] Reference Figure 7 ,according to Figure 1 Step S100, as shown, can sequentially execute multiple read operations until the read data stored in the non-volatile storage device is successfully obtained. The multiple read operations can form a read sequence. For example, in the read sequence, a first read operation (S110) can be executed, and a second read operation can be executed after the first read operation is completed (S130). After the second read operation is completed, an Xth read operation (e.g., X is a natural number greater than or equal to 3) can be executed (S150).

[0115] According to at least some exemplary embodiments of the present invention, during a typical data I / O process of a non-volatile memory device, when read data stored in the non-volatile memory device is obtained, a first read operation to an Xth read operation can be performed. The first read operation to the Xth read operation can correspond to the above-mentioned references. Figure 3 One of the described read operations. That is, the first read operation through the Xth read operation can be either a normal read operation or a recovery read operation.

[0116] According to at least some exemplary embodiments of the present invention, a first read operation to an Xth read operation can be executed sequentially, and when it is determined that the Kth read operation among the first read operation to the Xth read operation is a successful read operation, the (K+1)th read operation to the Xth read operation after the Kth read operation among the first read operation to the Xth read operation may not be executed, where K is a natural number greater than or equal to 1 and less than or equal to X.

[0117] According to at least some exemplary embodiments of the present invention, the first read operation to the Xth read operation can all have an inherent read latency.

[0118] Reference Figure 8 Multiple read operations and multiple determine operations can form a read sequence. For example, in a read sequence, a first read operation can be performed (S110), and it can be determined whether the first read operation was successful (S115). When the first read operation fails (S115: No), a second read operation can be performed (S130), and it can be determined whether the second read operation was successful (S135). When the second read operation fails (S135: No), an Xth read operation can be performed, for example, X is 3 (S150), and it can be determined whether the Xth read operation was successful (S155).

[0119] When it is determined that one of the first to the Xth read operations is a successful read operation (S115, S135, S155: Yes), the read data corresponding to the successful read operation can be output (S190). On the other hand, when it is determined that none of the first to the Xth read operations are successful read operations, the read sequence can be determined to have failed (S170).

[0120] According to at least some exemplary embodiments of the present invention, in each of the first to the Xth read operations, hard decision data and soft decision data can be generated by using a predetermined or optionally desired read level voltage for reading the read data and a plurality of read level voltages near the predetermined or optionally desired read level voltage. ECC decoding can be performed based on the hard decision data and the soft decision data. (Refer to...) Figure 12 , Figure 13 and Figure 15 Describes the sequence category and ECC decoding information.

[0121] Figure 9 and Figure 10 It is shown Figure 7 and Figure 8 A flowchart of an example embodiment of multiple read operations.

[0122] exist Figure 9 and Figure 10 The diagram illustrates an example of a first read operation among multiple read operations. However, this disclosure is not limited thereto. Read operations other than the first read operation can also be configured similarly to the first read operation.

[0123] Reference Figure 9 The system can perform a first read operation (S110) and perform ECC decoding on the read data according to the first read operation (S111).

[0124] According to at least some example embodiments of the present invention, ECC decoding can be performed on read data with inherent read latency.

[0125] As a result of ECC decoding, it can be determined whether error correction of the read data is feasible (S112). When it is determined that error correction of the read data is feasible based on the result of ECC decoding (S112: Yes), error correction of the read data can be performed, and the corrected read data can be output as valid read data (S113). When it is determined that error correction of the read data is not feasible based on the result of ECC decoding (S112: No), it can be determined that the first read operation failed (S115).

[0126] For ease of explanation, Figure 9 The diagram shows multiple steps S111, S112, S113, and S114 to distinguish them from the first read operation S110. However, these multiple steps S111, S112, S113, and S114 can be included within the first read operation S110. That is, steps S111, S112, S113, and S114 can be organized as the first read operation and can correspond to the steps described above. Figure 7 , Figure 8 and Figure 9 S110 is described.

[0127] Reference Figure 10 Steps S110, S111-1, S112-1, and S113-1 can correspond to the above reference. Figure 9 The described steps are S110, S111, S112, and S113. That is, in... Figure 10 In the example of the first read operation shown, only steps S114, S111-2, S112-2, and S113-2 are further executed.

[0128] A first read operation can be performed (S110), and a first ECC decoding can be performed on the first read data according to the first read operation (S111-1).

[0129] According to at least some example embodiments of the present invention, a first ECC decoding can be performed on the first read data with an inherent read latency.

[0130] As a result of the first ECC decoding, it can be determined whether error correction of the first read data is feasible (S112-1). When it is determined that error correction of the first read data is feasible based on the result of the first ECC decoding (S112-1: Yes), error correction of the first read data can be performed, and the error-corrected first read data can be output as valid read data (S113-1). When it is determined that error correction of the read data is not feasible based on the result of the first ECC decoding (S112-1: No), a recovery read operation can be performed. In the recovery read operation, the recovered read data is obtained by changing the read level voltage of the first read operation (S114), and a second ECC decoding can be performed on the recovered read data obtained through the recovery read operation (S111-2). When it is determined that error correction of the recovered read data is feasible based on the result of the second ECC decoding (S112-2: Yes), the error-corrected recovered read data can be output as valid read data (S113-2). When it is determined, based on the result of the second ECC decoding, that error correction to recover the read data is not feasible (S112-2: No), the first read operation can be determined to have failed (S115).

[0131] Figure 11 It is shown Figure 1 A flowchart of an example embodiment for determining the lifetime stage of a non-volatile storage device. Figure 12 and Figure 13 It is used to describe Figure 11 A diagram illustrating the process of determining the lifetime stages of a non-volatile storage device.

[0132] Reference Figure 11 It can be determined by or using sequence categories. Figure 1 The lifetime stage of the non-volatile storage device. Specifically, when the index value included in the sequence category is less than or equal to the reference index value (S310: Yes), it can be determined that the non-volatile storage device corresponds to the first lifetime stage (S330). When the index value is greater than the reference index value (S310: No), it can be determined that the non-volatile storage device corresponds to the second lifetime stage (S350). The sequence category will be described below.

[0133] Reference Figure 12 Sequence categories SC1, SC2, SC3, and SCX can correspond to read operations (from the first read operation to the Xth read operation). The sequence categories can be referenced above. Figure 8 and Figure 9The example of the described read sequence is generated. For example, sequence category SC1 may correspond to the first read operation, sequence category SC2 may correspond to the second read operation, sequence category SC3 may correspond to the third read operation, and sequence category SCX may correspond to the Xth read operation.

[0134] According to at least some exemplary embodiments of the present invention, sequence categories SC1, SC2, SC3, and SCX may each include an index value. For example, sequence category SC1 may include "1" as an index value, sequence category SC2 may include "2" as an index value, sequence category SC3 may include "3" as an index value, and sequence category SCX may include "X" as an index value.

[0135] According to at least some exemplary embodiments of the present invention, one of the first to the Xth read operations can be a successful read operation. The index value corresponding to the successful read operation included in the sequence category can be as described above. Figure 12 The index value described.

[0136] Reference Figure 13 The sequence categories SC1, SC1R, SC2, SC2R, SC3, SC3R, SCX, and SCXR can correspond to read operations (from the first read operation to the Xth read operation, and from the first recovery read operation to the Xth recovery read operation), respectively. The sequence categories can be referenced above. Figure 8 and Figure 10 Examples of the described read sequences are generated. For example, sequence class SC1 may correspond to the first read operation, and sequence class SC1R may correspond to the first recovery read operation. Sequence class SC2 may correspond to the second read operation, and sequence class SC2R may correspond to the second recovery read operation. Sequence class SC3 may correspond to the third read operation, and sequence class SC3R may correspond to the third recovery read operation. Sequence class SCX may correspond to the Xth read operation, and sequence class SCXR may correspond to the Xth recovery read operation.

[0137] According to at least some exemplary embodiments of the present invention, sequence categories SC1, SC1R, SC2, SC2R, SC3, SC3R, SCX, and SCXR may each include an index value. For example, sequence category SC1 may include "1" as an index value, and sequence category SC1R may include "2" as an index value. Similarly, sequence categories SC2, SC2R, SC3, SC3R, SCX, and SCXR may respectively include "3", "4", "5", "6", "2X-1", and "2X" as index values.

[0138] According to at least some exemplary embodiments conceived in this invention, the index value (in) Figure 12 The example shown uses numbers from "1" to "X". Figure 13 In the example shown, one of the values ​​from "1" to "2X" can be set as the reference index value.

[0139] Figure 14 It is shown Figure 1 A flowchart of an example embodiment for determining the lifetime stage of a non-volatile storage device. Figure 15 It is used to describe Figure 14 A diagram illustrating the process of determining the lifetime stages of a non-volatile storage device.

[0140] Reference Figure 14 It can be determined by or using sequence category and ECC decoding information. Figure 1 The lifetime stage of the non-volatile storage device. Specifically, when the index value included in the sequence category is less than or equal to the reference index value (S310: Yes) and when the number of error bits included in the ECC decoding information is less than or equal to the reference number of error bits (S315: Yes), it can be determined that the non-volatile storage device corresponds to the first lifetime stage (S330). When the index value is greater than the reference index value (S310: No) or when the number of error bits is greater than the reference number of error bits (S315: No), it can be determined that the non-volatile storage device corresponds to the second lifetime stage (S350). The ECC decoding information will be described below.

[0141] Reference Figure 15 The ECC decoding information may include the number of error bits calculated as a result of performing ECC decoding on the read data. For example, the ECC decoding information may include the number of error bits E1 as a result of performing ECC decoding on ECCD1, the number of error bits E2 as a result of performing ECC decoding on ECCD2, and the number of error bits E3 as a result of performing ECC decoding on ECCD3. Similarly, the ECC decoding information may include the number of error bits E4, E5, and E6 as a result of performing ECC decoding on ECCD4, ECCD5, and ECCD6, respectively.

[0142] Figure 16 and Figure 17 It is used to describe Figure 1 A diagram illustrating the coarse and fine predictions for the execution of non-volatile memory devices.

[0143] Reference Figure 1 and Figure 16 When a non-volatile memory device is determined to correspond to a first lifetime stage (e.g., an early stage), a coarse prediction can be performed. When a non-volatile memory device is determined to correspond to a second lifetime stage (e.g., a mid-term or late-term stage) following the first lifetime stage, a fine prediction can be performed.

[0144] According to at least some exemplary embodiments conceived in this invention, in Figure 13 In the example shown, when the reference index value is set to 6 and the non-volatile storage device corresponds to one of the sequence classes SC1, SC1R, SC2, SC2R, SC3, and SC3R with an index value less than or equal to the reference index value, a coarse prediction can be performed to predict the remaining lifetime of the non-volatile storage device. When the reference index value is set to 6 and the non-volatile storage device corresponds to one of the sequence classes SCX and SCXR with an index value greater than the reference index value, a fine prediction can be performed to predict the remaining lifetime of the non-volatile storage device.

[0145] In this scenario, sequence category and ECC decoding information can be used as input data for an artificial intelligence (AI) model to perform coarse predictions, while sequence category, ECC decoding information, and threshold voltage information can be used as input data for an AI model to perform fine predictions.

[0146] Furthermore, performing coarse predictions may include using sequence category and ECC decoding information as input data to an AI model to predict the remaining lifetime of non-volatile memory devices, while performing fine predictions may include using sequence category, ECC decoding information, and threshold voltage information as input data to an AI model to predict the remaining lifetime of non-volatile memory devices.

[0147] According to at least some exemplary embodiments of the present invention, coarse and fine predictions may include the confidence level of data stored in a non-volatile memory device. The remaining lifetime of the non-volatile memory device may include at least one of the remaining program / erase (P / E) cycles or the remaining retention time of the non-volatile memory device.

[0148] According to at least some exemplary embodiments conceived in this invention, when in Figure 13 In the example shown, when the reference index value is set to 6, when in Figure 15 In the example shown, when the reference error bit number is set to 3, a coarse prediction can be performed to predict the remaining lifetime of the non-volatile memory device when the non-volatile memory device corresponds to one of the sequence categories SC1, SC1R, SC2, SC2R, SC3, and SC3R with an index value less than or equal to the reference index value, and when the number of error bits is less than or equal to the reference error bit number (e.g., one of E1, E2, and E3).

[0149] According to at least some exemplary embodiments of the present invention, fine prediction can be performed to predict the remaining lifetime of the non-volatile memory device when the reference index value is set to 6, when the number of reference error bits is set to 3, when the non-volatile memory device corresponds to one of the sequence categories SCX and SCXR with an index value greater than the reference index value, or when the number of error bits is greater than the number of reference error bits.

[0150] Figure 18 and Figure 19 It is used to describe Figure 1 A diagram showing the threshold voltage information.

[0151] exist Figure 18 and Figure 19 The threshold voltage distribution of a non-volatile memory device including memory cells with a triple-level cell (TLC) structure is shown in the figure.

[0152] Reference Figure 18 The memory cells included in the non-volatile storage device may have an erase state E and one of the first programming states P1 to the seventh programming states P7.

[0153] According to at least some exemplary embodiments of the present invention, considering the characteristics of the storage cell, the read level voltages VRD1 to VRD7 can be predetermined values, or optionally desired values.

[0154] According to at least some exemplary embodiments of the present invention, read level voltages VRD1 to VRD7 can be determined based on the threshold voltage distribution immediately following the programming of the memory cell. According to at least some exemplary embodiments of the present invention, read level voltages VRD1 to VRD7 can be determined based on the threshold voltage distribution after a predetermined time or optionally a desired time has elapsed since the memory cell was programmed (e.g., after the memory cell has stabilized). In this case, the threshold voltage information can be used as input data for an AI model to perform fine predictions of the remaining lifetime of non-volatile memory devices.

[0155] The remaining lifetime of a non-volatile memory device may include at least one of the remaining program / erase (P / E) cycles or the remaining retention time of the non-volatile memory device.

[0156] Furthermore, the remaining lifetime of a non-volatile memory device can be predicted based on sequence category, ECC decoding information, threshold voltage information, and Self-Monitoring, Analysis and Reporting Technology (SMART) attribute information. SMART attribute information may include at least one of reallocated sectors count, seek error rate, spin retry count, reallocation event count, and current pending sectors count. In this case, the method for predicting the remaining lifetime of a non-volatile memory device according to at least some example embodiments of the present invention may further include acquiring SMART attribute information. Furthermore, it may further include generating an AI model based on learned sequence category, learned ECC decoding information, and learned threshold voltage information.

[0157] Reference Figure 19 When the physical characteristics of the memory cells included in a non-volatile memory device change due to external factors, the threshold voltage distribution can change as follows: Figure 19 As shown.

[0158] For example, in charge-trapped flash memory (CTF) cells, an initial verify shift (IVS) phenomenon may occur, in which the threshold voltage distribution of the cell decreases over time. Furthermore, due to a sudden power outage (SPO) during cell programming, the threshold voltage distribution of the cell can be... Figure 19 The overlap is shown. Therefore, when reading read data stored in non-volatile storage devices based on read level voltages VRD1 to VRD7, the read data may include multiple errors.

[0159] Figure 20 , Figure 21 and Figure 22 It is shown as Figure 1 An illustration of an artificial neural network used as an example of an AI model for predicting the remaining lifetime of non-volatile storage devices.

[0160] Reference Figure 20 A typical neural network (e.g., an ANN) may include an input layer IL, multiple hidden layers HL1, HL2, ..., HLn, and an output layer OL.

[0161] The input layer (IL) can include i input nodes x1, x2, ..., xn.i Where i is a natural number. Input data of length i (e.g., vector input data) IDAT can be input into input nodes x1, x2, ..., x... i This ensures that each element of the input data IDAT is input into the input nodes x1, x2, ..., x3. i The corresponding input node in.

[0162] Multiple hidden layers HL1, HL2, ..., HLn can include n hidden layers, where n is a natural number, and can include multiple hidden nodes h. 1 1. h 1 2. h 1 3、……、h 1 m h 2 1. h 2 2. h 2 3、……、h 2 m h n 1. h n 2. h n 3、……、h n m For example, the hidden layer HL1 can include m hidden nodes h. 1 1. h 1 2. h 1 3、……、h 1 m The hidden layer HL2 can include m hidden nodes h 2 1. h 2 2. h 2 3、……、h 2 m The hidden layer HLn can include m hidden nodes h n 1. h n 2. h n 3、……、h n m , where m is a natural number.

[0163] The output layer OL can include j output nodes y1, y2, ..., y3. j Where j is a natural number. Output nodes y1, y2, ..., y3. j Each output node in the layer can correspond to a corresponding category in the categories to be classified. The output layer OL can output an output value (e.g., a category score or a simple score) associated with the input data IDAT for each category. The output layer OL can be called a fully connected layer and can indicate, for example, the probability that the input data IDAT corresponds to one of the candidates for the remaining lifetime of a non-volatile storage device.

[0164] Figure 20 The structure of the neural network shown can be represented by information about the branches (or connections) between nodes, shown as lines, with weights (not shown) assigned to each branch. Nodes within a layer may not be connected to each other, but nodes in different layers may be fully or partially connected to each other.

[0165] Each node (e.g., node h) 1 1) It can receive the output of a previous node (e.g., node x1), perform computational operations or calculations on the received output, and input the result of the computational operation or calculation as the output to the next node (e.g., node h). 2 1) Each node can compute the value to be output by applying the input to a specific function (e.g., a non-linear function).

[0166] Typically, the structure of a neural network is pre-set, and the weights of the connections between nodes are appropriately set using data with known answers indicating which category the data belongs to. This data with known answers is called "training data," and the process of determining the weights is called "training." The neural network "learns" during the training process. A set of independently trainable structures and weights is called a "model," and the process of predicting which category the input data belongs to using the model with defined weights and then outputting the predicted value is called the "testing" process.

[0167] Figure 20 The general neural network shown may not be suitable for processing input image data (or input sound data) because each node (e.g., node h) 1 1) Connect to all nodes in the previous layer (e.g., nodes x1, x2, ..., x in layer IL). i Then, the number of weights increases dramatically with the increase of the input image data size. Therefore, CNNs, which combine filtering techniques with general neural networks, have been studied to efficiently train two-dimensional images (e.g., input image data).

[0168] Reference Figure 21 A CNN can include multiple layers: CONV1, RELU1, CONV2, RELU2, POOL1, CONV3, RELU3, CONV4, RELU4, POOL2, CONV5, RELU5, CONV6, RELU6, POOL3, and FC.

[0169] Unlike typical neural networks, each layer of a CNN can have three dimensions: width, height, and depth. Therefore, the data input to each layer can be volume data with these three dimensions. For example, if... Figure 21The input image has a width of 32 (e.g., 32 pixels), a height of 32, and the size of three color channels R, G, and B. The input data IDAT corresponding to the input image can have a size of 32*32*3. Figure 21 The input data IDAT in the input can be referred to as input body data or input activation body.

[0170] Convolutional layers CONV1, CONV2, CONV3, CONV4, CONV5, and CONV6 can all perform convolution operations on input volume data. In image processing, convolution operations represent operations that process image data based on a mask: the mask has weight values, and the output value is obtained by multiplying the input value by the weight values ​​and summing the total multiplications. The mask can be called a filter, window, or kernel.

[0171] Specifically, the parameters of each convolutional layer can consist of a set of learnable filters. Each filter can be small in space (along width and height) but can extend to the entire depth of the input volume. For example, during the forward pass, each filter can slide (more precisely, convolve) across the width and height of the input volume, and a dot product can be computed between the filter's terms and the input at any location. As the filters slide across the width and height of the input volume, a two-dimensional activation map can be generated, which gives the response of the filter at each spatial location. As a result, the output volume can be generated by stacking these activation maps along the depth dimension. For example, if input volume data of size 32*32*3 passes through a convolutional layer CONV1 with four zero-padding filters, the output volume data of convolutional layer CONV1 can be 32*32*12 in size (e.g., the depth of the volume data increases).

[0172] RELU layers RELU1, RELU2, RELU3, RELU4, RELU5, and RELU6 can all perform corrected linear unit (RELU) operations, which correspond to an activation function defined by, for example, a function f(x) = max(0, x) (e.g., for all negative inputs x, the output is zero). For example, if a volume of input data of size 32*32*12 is processed by RELU layer RELU1, the output volume of RELU layer RELU1 can have a size of 32*32*12 (e.g., maintaining the size of the volume data).

[0173] Pooling layers POOL1, POOL2, and POOL3 can all perform downsampling operations on the input volume data along the spatial dimensions of width and height. For example, four input values ​​arranged in a 2x2 matrix can be transformed into a single output value based on a 2x2 filter. For example, the maximum value among four input values ​​arranged in a 2x2 matrix can be selected based on 2x2 max pooling, or the average value of four input values ​​arranged in a 2x2 matrix can be obtained based on 2x2 average pooling. For example, if input volume data of size 32x32x12 passes through pooling layer POOL1 with a 2x2 filter, the output volume data of pooling layer POOL1 can have a size of 16x16x12 (e.g., the width and height of the volume data are reduced, while the depth of the volume data is maintained).

[0174] Typically, a convolutional layer (e.g., CONV1) and a ReLU layer (e.g., RELU1) can form a pair of CONV / RELU layers in a CNN. The pairs of CONV / RELU layers can be repeatedly arranged in the CNN, and pooling layers can be periodically inserted into the CNN to reduce the spatial size of the image and extract the features of the image.

[0175] The output layer, or fully connected (FC) layer, can output the result of the input volume data IDAT (e.g., class score) for each class. For example, with repeated convolution and downsampling operations, the input volume data IDAT corresponding to a two-dimensional image can be transformed into a one-dimensional matrix or vector. For instance, a fully connected FC layer can represent the probability that the input volume data IDAT corresponds to a car, truck, airplane, ship, and horse.

[0176] The types and number of layers included in a CNN are not limited to those referenced. Figure 21 The examples described may be modified, and at least some of the exemplary embodiments conceived in this invention may be altered. Furthermore, although in Figure 21 Although not shown in the diagram, CNNs may also include other layers, such as a softmax layer for converting the scores corresponding to the prediction results into probability values, a bias-adding layer for adding at least one bias, etc.

[0177] refer to Figure 22 RNNs can include those used in Figure 22 The left side shows a repeating structure of a specific node or unit N.

[0178] Figure 22The structure shown on the right can be represented as the recursive connections of the RNN shown on the left being expanded (or unrolled). The term "expanded" means that the network is written out or shown for the complete or entire sequence including all nodes NA, NB, and NC. For example, if the sequence of interest is a sentence of 3 words, the RNN can be expanded into a 3-layer neural network, one layer for each word (e.g., no recursive connections or no loops).

[0179] exist Figure 22 In an RNN, X represents the input of the RNN. For example, X t It can be the input at time step t, X t-1 and X t+1 The inputs can be at time steps t-1 and t+1, respectively.

[0180] exist Figure 22 In an RNN, S represents the hidden state. For example, S t It can be the hidden state at time step t, S t-1 and S t+1 These can be the hidden states at time steps t-1 and t+1, respectively. The hidden state can be computed based on the previous hidden state and the input at the current step. For example, S t =f(UX) t +WS t-1 For example, the function f can typically be a nonlinear function, such as tanh or ReLU. The S required to compute the first hidden state... -1 It can usually be initialized to all zeros.

[0181] exist Figure 22 In an RNN, O represents the RNN's output. For example, O t It can be the output at time step t, O t-1 and O t+1 These can be outputs at time steps t-1 and t+1, respectively. For example, if you need to predict the next word in a sentence, it will be a probability vector from the vocabulary. For example, O t =softmax(VS t ).

[0182] exist Figure 22 In an RNN, the hidden state can be considered the network's "memory." In other words, an RNN can have a "memory" that captures information about what has been computed so far. Hidden state S tIt can capture information about what happened in all previous time steps. The output Ot can be computed independently based on the memory of the current time step t. Furthermore, unlike traditional neural networks that use different parameters in each layer, RNNs can share the same parameters across all time steps. This represents the fact that the same task can be performed at each step, only the input differs. This can significantly reduce the total number of parameters that need to be trained or learned.

[0183] Based on at least some exemplary embodiments of the present invention, references can be made to the above. Figure 2 The described memory controller and reference Figure 6 The described storage controller is used to perform and process various services and / or applications, such as coarse or fine predictions of the remaining lifetime of non-volatile storage devices.

[0184] Figure 23 This is a block diagram illustrating at least some exemplary embodiments of a storage device and a storage system including the storage device according to a concept of the present invention.

[0185] Reference Figure 23 The storage system 1000 may include a host device 1100 and a storage device 1200.

[0186] The host device 1100 controls the overall operation of the storage system 1000. Although not in... Figure 23 As shown, host device 1100 may include a host processor and host memory. The host processor can control the operation of host device 1100. For example, the host processor can execute an operating system (OS). Host memory can store instructions and / or data executed and / or processed by the host processor. For example, the operating system executed by the host processor may include a file system for file management and device drivers for controlling peripheral devices including storage device 1200 at the operating system level.

[0187] Storage device 1200 is accessed by host device 1100. Storage device 1200 includes storage controller 1210, multiple non-volatile memories (NVMs) 1220a, 1220b and 1220c, and buffer memory 1230.

[0188] Storage controller 1210 can control the operation of storage device 1200 and / or multiple non-volatile memories 1220a, 1220b, and 1220c based on commands and data received from host device 1100. The multiple non-volatile memories 1220a, 1220b, and 1220c can store multiple data. For example, the multiple non-volatile memories 1220a, 1220b, and 1220c can store metadata, various user data, etc. Buffer memory 1230 can store instructions and / or data executed and / or processed by storage controller 1210, and can temporarily store data stored or to be stored in the multiple non-volatile memories 1220a, 1220b, and 1220c. Figure 2 The storage device 10 can be implemented as a storage device 1200. For example, the storage controller 1210 can correspond to... Figure 2 The memory controller 20, and the non-volatile memories 1220a, 1220b, and 1220c can correspond to Figure 2 The non-volatile storage device 40 in the middle.

[0189] The remaining lifetime predictor (RP) 1212 included in the storage controller 1210 can correspond to Figure 6 The remaining lifetime predictor 430 is included. In some example embodiments, the storage controller 1210 may also include a neural processing unit (NPU) 1214 for detecting I / O patterns of written data.

[0190] In some example embodiments, storage device 1200 may be a solid-state drive (SSD), universal flash memory (UFS), multimedia card (MMC), or embedded multimedia card (eMMC). In other example embodiments, storage device 1200 may be one of a secure digital card (SD), micro SD card, memory stick, chip card, universal serial bus (USB) card, smart card, compact flash memory (CF) card, etc.

[0191] As described above, in the method for predicting the remaining lifetime of a non-volatile memory device according to at least some exemplary embodiments of the present invention, the remaining lifetime of the non-volatile memory device can be effectively determined by executing steps S100, S200, S300, S400, and S500. When it is determined that the non-volatile memory device corresponds to a first lifetime stage, only a coarse prediction is performed; when it is determined that the non-volatile memory device corresponds to a second lifetime stage after the first lifetime stage, a fine prediction, which is more accurate than the coarse prediction, is performed. That is, by adaptively performing different predictions according to the lifetime stage of the non-volatile memory device, the speed and accuracy of the prediction can be improved.

[0192] At least some exemplary embodiments of the present invention can be applied to a variety of electronic devices and systems, including non-volatile storage devices and storage devices. For example, the present invention can be applied to systems such as: personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0193] Exemplary embodiments of the inventive concept have been described, and it will be apparent that they can be modified in various ways. Such modifications should not be considered as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and it will be apparent to those skilled in the art that all such modifications are intended to be included within the scope of the appended claims.

Claims

1. A method for predicting the remaining lifetime of a non-volatile storage device, the method comprising: Iteratively perform one or more read operations until the read data stored in the non-volatile storage device is successfully obtained; Generate sequence category and error correction code decoding information, wherein the sequence category corresponds to a successful read operation, the successful read operation is one of the one or more read operations that successfully obtains the read data, and the error correction code is ECC; The lifetime stage of the non-volatile storage device is determined based on at least one of the sequence category and the ECC decoding information; In response to determining that the non-volatile storage device corresponds to a first lifetime stage, a coarse prediction of the remaining lifetime of the non-volatile storage device is performed based on the sequence category and the ECC decoding information; as well as In response to determining that the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, a fine prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category, the ECC decoding information, and the threshold voltage information of the non-volatile memory device.

2. The method according to claim 1, wherein: The sequence category includes an index value corresponding to the successful read operation. The ECC decoding information includes the number of error bits calculated as a result of performing ECC decoding on the read data, and The threshold voltage information includes the difference between a first threshold voltage distribution and a second threshold voltage distribution, the first threshold voltage distribution being measured immediately after the read data is programmed into the memory cell included in the non-volatile storage device, and the second threshold voltage distribution being measured immediately after the read data is successfully obtained.

3. The method according to claim 2, wherein, The determination of the lifetime stage of the non-volatile storage device includes: In response to the index value being less than or equal to the reference index value, it is determined that the non-volatile storage device corresponds to the first lifetime stage; and In response to the index value being greater than the reference index value, it is determined that the non-volatile storage device corresponds to the second lifetime stage.

4. The method according to claim 2, wherein, The determination of the lifetime stage of the non-volatile storage device includes: In response to determining that the index value is less than or equal to a reference index value and the number of error bits is less than or equal to a reference number of error bits, it is determined that the non-volatile storage device corresponds to the first lifetime stage; and In response to determining that the index value is greater than the reference index value or determining that the number of error bits is greater than the reference number of error bits, the non-volatile storage device is determined to correspond to the second lifetime stage.

5. The method according to claim 1, in, The aforementioned rough prediction includes: The coarse prediction is performed using the sequence category and the ECC decoding information as input data to the artificial intelligence model, and The aforementioned fine-grained prediction includes: The fine prediction is performed using the sequence category, the ECC decoding information, and the threshold voltage information as input data to the artificial intelligence model.

6. The method according to claim 5, in, The aforementioned coarse prediction further includes: The sequence category and the ECC decoding information are used as input data to the artificial intelligence model to predict the remaining lifetime of the non-volatile storage device. The aforementioned detailed prediction further includes: The remaining lifetime of the non-volatile memory device is predicted using the sequence category, the ECC decoding information, and the threshold voltage information as input data to the artificial intelligence model.

7. The method according to claim 6, wherein, The remaining lifetime of the non-volatile memory device includes at least one of the remaining program / erase cycles and the remaining retention time of the non-volatile memory device.

8. The method according to claim 6, further comprising: The system acquires self-monitoring, analysis, and reporting technical attribute information, which includes at least one of the following: remapped sector count, seek error rate, rotational retry count, reallocation event count, and current unmapped sector count. The remaining lifetime of the non-volatile storage device is predicted based on the sequence category, the ECC decoding information, the threshold voltage information, and the self-monitoring, analysis, and reporting technical attribute information.

9. The method according to claim 6, further comprising: The artificial intelligence model is generated based on the learned sequence category, learned ECC decoding information, and learned threshold voltage information.

10. The method according to claim 1, wherein, The one or more read operations include multiple read operations. The plurality of read operations include a first read operation to an Xth read operation executed sequentially, wherein X is a natural number greater than or equal to 2, and in response to determining that the Kth read operation among the first read operation to the Xth read operation is the successful read operation, the (K+1)th read operation to the Xth read operation after the Kth read operation among the first read operation to the Xth read operation is not executed, wherein K is a natural number greater than or equal to 1 and less than or equal to X.

11. The method of claim 10, wherein, In each of the first to the Xth read operations, ECC decoding is performed on the read data with an inherent read latency, and In response to the determination that error correction of the read data is feasible based on the result of the ECC decoding, the error correction of the read data is performed, and the error-corrected read data is output as valid read data.

12. The method according to claim 10, wherein, The first read operation to the Xth read operation all include: Hard decision data and soft decision data are generated using a first read level voltage used to obtain the read data, and The ECC decoding is performed based on the hard decision data and the soft decision data.

13. The method according to claim 10, wherein, In each of the first to the Xth read operations, a first ECC decoding is performed on the read data with an inherent read delay. In response to the determination that error correction of the read data is not feasible based on the result of the first ECC decoding, a recovery read operation is performed. In this recovery read operation, recovered read data is obtained by changing the read level voltage used for the read data, and a second ECC decoding is performed on the recovered read data obtained through the recovery read operation. In response to the determination that error correction of the recovered read data is feasible based on the result of the second ECC decoding, error-corrected recovered read data is generated by performing error correction on the recovered read data, and the error-corrected recovered read data is output as valid read data.

14. The method according to claim 1, wherein: In response to the time point at which the lifetime stage of the non-volatile memory device is determined exceeds a predetermined time point from the time point at which the non-volatile memory device is manufactured, The rough prediction is not performed, and Perform the detailed prediction.

15. A storage device, comprising: Non-volatile storage devices; as well as A storage controller processor configured to control the non-volatile storage device. The storage controller processor is further configured to, Iteratively perform one or more read operations until the read data stored in the non-volatile storage device is successfully obtained. Generate sequence category and error correction code decoding information. The sequence category corresponds to a successful read operation, which is one of the one or more read operations that successfully obtains the read data. The error correction code is ECC. The lifetime stage of the non-volatile storage device is determined based on at least one of the sequence category and the ECC decoding information. In response to determining that the non-volatile memory device corresponds to a first lifetime stage, a coarse prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category and the ECC decoding information, and In response to determining that the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, a fine prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category, the ECC decoding information, and the threshold voltage information of the non-volatile memory device.

16. The storage device according to claim 15, in, The storage controller processor is further configured to, The coarse prediction is performed using the sequence category and the ECC decoding information as input data to the artificial intelligence model. The fine prediction is performed using the sequence category, the ECC decoding information, and the threshold voltage information as input data to the artificial intelligence model.

17. The storage device according to claim 15, wherein, The sequence category includes an index value corresponding to the successful read operation. The ECC decoding information includes the number of error bits calculated as a result of performing ECC decoding on the read data, and The threshold voltage information includes the difference between a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is a threshold voltage distribution measured immediately after the read data is programmed into the memory cell included in the non-volatile memory device, and the second threshold voltage distribution is a threshold voltage distribution measured immediately after the read data is successfully obtained.

18. The storage device according to claim 17, wherein: The storage controller processor is further configured to, In response to determining that the index value is less than or equal to the reference index value, it is determined that the non-volatile storage device corresponds to an early stage. In response to determining that the index value is greater than the reference index value, it is determined that the non-volatile storage device corresponds to one of the intermediate stage and the late stage.

19. The storage device according to claim 17, wherein: The storage controller processor is further configured to, In response to determining that the index value is less than or equal to the reference index value and the number of error bits is less than or equal to the reference number of error bits, it is determined that the non-volatile storage device corresponds to an early stage; and In response to determining that the index value is greater than the reference index value or determining that the number of error bits is greater than the reference number of error bits, the non-volatile storage device is determined to correspond to one of the intermediate stage and the late stage.

20. A method for predicting the remaining lifetime of a non-volatile storage device, the method comprising: Iteratively perform one or more read operations until the read data stored in the non-volatile storage device is successfully obtained; Generate sequence category and error correction code decoding information, wherein the sequence category corresponds to a successful read operation, the successful read operation is one of the one or more read operations that successfully obtains the read data, and the error correction code is ECC; The lifetime stage of the non-volatile storage device is determined based on at least one of the sequence category and the ECC decoding information; In response to determining that the non-volatile storage device corresponds to a first lifetime stage, a coarse prediction of the remaining lifetime of the non-volatile storage device is performed based on the sequence category and the ECC decoding information; as well as In response to determining that the non-volatile memory device corresponds to a second lifetime stage following the first lifetime stage, a fine prediction of the remaining lifetime of the non-volatile memory device is performed based on the sequence category, the ECC decoding information, and the threshold voltage information of the non-volatile memory device. The sequence category includes an index value corresponding to the successful read operation. The determination of the lifetime stage of the non-volatile storage device includes: in response to determining that the index value is less than or equal to the reference index value, determining that the non-volatile storage device corresponds to the first lifetime stage. The coarse prediction includes: performing the coarse prediction using the sequence category and the ECC decoding information as input data to the artificial intelligence model; and predicting the remaining lifetime of the non-volatile storage device using the sequence category and the ECC decoding information as input data to the artificial intelligence model. The remaining lifetime of the non-volatile memory device includes at least one of the remaining programming / erasing cycles and the remaining retention time of the non-volatile memory device.

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