Data encoding method and apparatus

Abstract

This invention provides a data encoding method and apparatus. The method includes: acquiring data to be transmitted; performing quasi-cyclic LDPC encoding on the data to be transmitted to obtain an LDPC codeword sequence; interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence; performing cyclic bit selection on the interleaved LDPC codeword sequence starting from a starting position to obtain a rate-matched codeword sequence, wherein the starting position is determined according to predetermined parameters; and transmitting the rate-matched codeword sequence. This method solves the problem of unstable transmission after quasi-cyclic LDPC encoding of transmitted data in related technologies, and achieves stable transmission after quasi-cyclic LDPC encoding.

Description

[0001] This application is a divisional application of Chinese patent application No. 201710687764.6, filed on August 11, 2017, entitled “Data Encoding Method and Apparatus”. Technical Field

[0002] This invention relates to the field of communications, and more specifically, to a data encoding method and apparatus. Background Technology

[0003] In related technologies, to address the issue that excessive padding bits in quasi-cyclic LDPC coding can reduce the coding / decoding efficiency of LDPC codes, a TBS table design rule is provided to minimize or eliminate padding bits during LDPC coding. Furthermore, to address the bottleneck effect caused by unequal numbers of code blocks within different code block groups in a transport block, a Kmax design method in code block segmentation is provided to ensure an equal number of code blocks in each code block group, preventing some code block groups from having too many code blocks and resulting in poor overall performance. Finally, to address the performance issues of quasi-cyclic LDPC coding under high-order modulation or fading channels, a codeword interleaving method is provided to improve the performance of quasi-cyclic LDPC coding.

[0004] In digital communication systems based on relevant technologies, there are generally three parts: the transmitter, the channel, and the receiver. The transmitter performs channel coding on the information sequence to obtain coded codewords, interleaves the coded codewords, and maps the interleaved bits to modulation symbols. Then, it processes and transmits the modulation symbols according to the communication channel information. In the channel, factors such as multipath propagation and motion cause specific channel responses, all of which distort data transmission. Noise and interference further degrade data transmission. The receiver receives the modulation symbol data after it has passed through the channel. At this point, the modulation symbol data is distorted and requires specific processing to recover the original information sequence.

[0005] Based on the encoding method of the information sequence at the transmitting end, the receiving end can process the received data accordingly to reliably recover the original information sequence. Generally, the encoding processing method is based on forward error correction (FEC) coding, where forward error correction coding adds some redundant information to the information sequence, and the receiving end can use this redundant information to reliably recover the original information sequence.

[0006] Some common FEC codes include convolutional codes, Turbo codes, and Low Density Parity Check (LDPC) codes. In FEC coding, a k-bit information sequence is FEC-coded to obtain an n-bit FEC codeword (with nk redundant bits), and the FEC coding rate is k / n. LDPC codes are linear block codes that can be defined using a very sparse parity check matrix or a bipartite graph. It is precisely by utilizing the sparsity of its parity check matrix that low-complexity encoding and decoding can be achieved, thus making LDPC practical. Through various practical and theoretical proofs, LDPC codes have demonstrated to be the best-performing channel code in Additive White Gaussian Noise (AWGN) channels, with performance very close to the Shannon limit. In the parity check matrix of an LDPC code, each row is a parity check code. If the element at a certain index position in each row is equal to 1, it means that the bit participates in the parity check code; if it is equal to 0, it means that the bit at that position does not participate in the parity check code.

[0007] Quasi-cyclic LDPC codes, due to their structured characteristics, have gradually become mainstream applications, finding widespread use in IEEE 802.11ac, IEEE 802.11ad, IEEE 802.11aj, IEEE 802.16e, IEEE 802.11n, microwave communication, and fiber optic communication, and have been adopted as a data channel coding scheme in 5G mobile communication. The parity check matrix H of a quasi-cyclic LDPC code is an M×Z row and N×Z column matrix, composed of M×N submatrices. Each submatrix is ​​a different power of a Z×Z fundamental permutation matrix, obtained by cyclically shifting a Z×Z identity matrix by several values. To more easily describe the cyclic shift of the identity matrix mathematically, the parity check matrix of a quasi-cyclic LDPC code can be described by the following mathematical formula:

[0008]

[0009] If hb ij If == -1, then we have It is a Z×Z matrix of all zeros; otherwise, It is a non-negative integer power of the standard permutation matrix P, which is shown below:

[0010]

[0011] By this definition, Z and the power hb ijEach block matrix can be uniquely identified. If a block matrix is ​​all zeros, it can be represented by "-1", a null value, or other forms; if it is obtained by cyclic shifting 's' of the identity matrix, then it is equal to 's'. All hb ij The fundamental matrix Hb of a quasi-cyclic LDPC code can be constructed, and the fundamental matrix Hb of the LDPC code can be represented as follows:

[0012]

[0013] Therefore, the base matrix Hb contains two types of elements: 1. elements indicating the all-zero square matrix; 2. elements indicating the cyclic shift size of the identity matrix, generally represented by integers from 0 to (Z-1). The base matrix Hb can also be called the base parity matrix, shift value matrix, permutation value matrix, basic parity check matrix, or parity check matrix. In the base matrix Hb, if the elements representing the all-zero matrix are replaced with "0" elements and other elements are replaced with "1" elements, the base graph matrix or template matrix of the quasi-cyclic LDPC encoding can be obtained. The base graph matrix can also be described in tabular form, for example, using row and column index pairs to indicate the position of the "1" in the corresponding base graph matrix or the position of the element indicating the cyclic shift size of the identity matrix in the base matrix. Therefore, the base matrix of the quasi-cyclic LDPC encoding can be determined based on the template matrix of the quasi-cyclic LDPC code and a set of shift values ​​(or coefficients). Furthermore, the dimension Z of the basic permutation matrix or all-zero square matrix can be defined as the shift size, expansion factor, or submatrix size.

[0014] Therefore, a structured LDPC code can be uniquely determined by the fundamental parity-check matrix Hb and the lift value Z. For example, the fundamental matrix Hb (2 rows and 4 columns) is as follows, and the corresponding lift value z is equal to 4.

[0015]

[0016] The corresponding template matrix is:

[0017]

[0018] Then, based on the fundamental matrix Hb and the lifting value Z, the parity check matrix H is obtained as follows:

[0019]

[0020] In quasi-cyclic LDPC encoding, encoding can be performed directly based on the parity check matrix determined by the fundamental matrix Hb and the boost value Z. According to the definition of LDPC code, H×C=0, where H includes [Hs Hp], where Hs is the systematic column part of the parity check matrix, Hp is the parity check column part of the parity check matrix, and C can include [Cs Cp], where Cs is the systematic bit sequence (information bits, known bits) of the LDPC code, and Cp is the parity check bit sequence (unknown bits) of the LDPC code. The LDPC encoding process is essentially the calculation of the parity check bit sequence; therefore, Hs×Cs=Hp×Cp; then, the parity check bit sequence can be calculated as Cp=Hp⁻¹×Hs×Cs. Therefore, the parity check column part of the parity check matrix must be a square matrix and binary invertible; thus, the quasi-cyclic LDPC encoded sequence can be obtained as [Cs Cp]. Alternatively, it can be calculated by cyclically shifting each Z bit block.

[0021] In practical communication systems, the number of bits in the actual transport block to be transmitted may not equal the system bit length supported by the quasi-cyclic LDPC coding matrix. Therefore, it is necessary to segment the transport block and add padding bits. For LDPC codes, padding bits are used to assist in encoding or decoding and are not actually transmitted. However, if there are too many padding bits during encoding and decoding, the encoder or decoder will perform more useless operations, thereby reducing the encoding and decoding speed and increasing energy consumption. Furthermore, if the transport block length is large, the number of code blocks is also large. To facilitate feedback and improve processing efficiency, all LDPC code blocks need to be divided into multiple code block groups. Each code block group contains several LDPC code blocks, and the receiving end performs feedback on whether the reception is correct and data retransmission operations on a code block group basis. If the code block group design is not considered during the code block segmentation process, the number of code blocks in the code block group will be unequal, resulting in some bottleneck effects and affecting the robustness of data communication. Furthermore, since quasi-cyclic LDPC coding itself has certain structured characteristics, LDPC codes may have some performance problems in some high-order modulations or fading channels. It is necessary to interleave codeword bits to randomize burst noise in order to improve the performance of quasi-cyclic LDPC codewords under burst noise.

[0022] There is currently no effective solution to the problem of unstable transmission after quasi-cyclic LDPC encoding of transmitted data in related technologies. Summary of the Invention

[0023] This invention provides a data encoding method and apparatus to at least solve the problem of unstable transmission after quasi-cyclic LDPC encoding of transmitted data in related technologies.

[0024] According to an embodiment of the present invention, a low-density parity-check data encoding method is provided, comprising: performing quasi-cyclic LDPC encoding on an information block bit sequence to obtain an LDPC codeword sequence, and determining a one-dimensional finite-length circular buffer size based on the LDPC codeword sequence; selecting a redundancy version value from a plurality of predetermined redundancy version values, and determining the starting position for reading the bit sequence to be transmitted from the one-dimensional finite-length circular buffer based on the selected redundancy version value and predefined parameters; wherein the predefined parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, systematic number of columns in the basic graph matrix, and length of the information block bit sequence; starting from the starting position, sequentially reading data bits of a specific length to form a bit sequence to be transmitted, and transmitting the bit sequence to be transmitted.

[0025] Optionally, determining the size of the one-dimensional finite-length circular buffer based on the LDPC codeword sequence includes: interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence, and acquiring one-dimensional finite-length circular buffer data. The one-dimensional finite-length circular buffer data is the data of the interleaved LDPC codeword sequence.

[0026] Optionally, the step of interleaving the LDPC codeword sequence to obtain the interleaved LDPC codeword sequence includes: performing block interleaving on the LDPC codeword sequence, wherein the number of rows of the interleaving matrix is ​​determined according to the quasi-cyclic LDPC coding parameters, wherein the quasi-cyclic LDPC coding parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, and systematic number of columns in the basic graph matrix. The interleaving matrix is ​​a column-in-column interleaving method, and the interleaving method includes interleaving according to different column output orders, or interleaving each column separately within the column and then outputting them in a certain column output order.

[0027] Optionally, the number of rows in the interleaving matrix is ​​equal to a positive integer factor of the quasi-cyclic LDPC boost value, or equal to a positive integer multiple of the boost value of the quasi-cyclic LDPC encoding.

[0028] Optionally, the number of rows in the interleaving matrix is ​​equal to a positive integer factor of the total number of columns in the basic graph matrix of the quasi-cyclic LDPC encoding, or equal to a positive integer multiple of the total number of columns in the basic graph matrix of the quasi-cyclic LDPC encoding.

[0029] Optionally, the interleaving method further includes: outputting the interleaved LDPC bit sequences in a predetermined column order. The column order is as follows: even numbers followed by odd numbers, odd numbers followed by even numbers, [integers with an interval of g1 between 0 and g0, integers with an interval of g1 between 1 and g0, ..., integers with an interval of g1 between g1 and g1-1]. g0 and g1 are both positive integers.

[0030] Optionally, the interleaving method further includes interleaving each column separately. In a preferred embodiment, the interleaving methods for any two columns are different.

[0031] Optionally, the starting position is determined based on the redundant version, the boost value, and the total number of columns in the basic graph matrix.

[0032] Optionally, the starting position corresponding to the redundant version RVi is calculated using the following formula:

[0033] First formula: S i =α×funtion(β×(nb / G)×RV) i +χ)×Z+δ;wherein, nb in the first formula is the total number of columns of the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive real number, χ is a non-negative real number, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer for the real number x;

[0034] Alternatively, the second formula: S i =α×(β×funtion(λ×nb / G)×RV i +χ)×Z+δ;where, in the second formula, nb is the total number of columns of the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer for the real number x;

[0035] Alternatively, the third formula: S i =α×(β×funtion(λ×nb×Z / G)×RV i +χ)+δ;

[0036] In the third formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0037] Optionally, the starting position is determined based on the redundant version, the boost value, the total number of rows in the basic graph matrix, and the length of the information block bit sequence.

[0038] Optionally, the starting position corresponding to the redundant version RVi is calculated using one of the following formulas:

[0039] S i =α×(β×funtion((K+mb×Z) / G)×RV i +χ)+δ;

[0040] S i =α×(β×funtion((K+mb×Z) / G)+χ)×RV i +δ

[0041] In the above two formulas, K is the length of the information block bit sequence, Z is the boost value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, and δ is an integer, where function(x) represents rounding up, down, or to the nearest integer on the real number x.

[0042] Optionally, interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence includes: interleaving all bits from bit S0 to bit S1 in the LDPC codeword sequence, wherein S0 and S1 are both positive integers, and S1 is greater than S0.

[0043] Optionally, interleaving all bits from bit S0 to bit S1 in the LDPC codeword sequence includes: performing block interleaving on all bits from bit S0 to bit S1 in the LDPC codeword sequence according to the interleaving matrix, wherein the number of columns of the block interleaving matrix is ​​Z0, and Z0 is determined by quasi-cyclic LDPC coding parameters, wherein the quasi-cyclic LDPC coding parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, and systematic number of columns in the basic graph matrix.

[0044] Optionally, Z0 is equal to a positive integer factor of the boost value or a positive integer multiple of the boost value.

[0045] Optionally, Z0 is equal to a positive integer factor of the total number of columns in the basic graph matrix, or a positive integer multiple of the total number of columns in the basic graph matrix.

[0046] Optionally, S1 is equal to a positive integer multiple of the boost value.

[0047] Optionally, S1 is equal to the boost value kb-2, kb-1, kb, kb+1, or kb+2 times, where kb is the number of columns in the basic graph matrix system of LDPC encoding.

[0048] Optionally, Z0 is determined by the following parameters: S0, S1, and modulation order, wherein the modulation order is the number of bits carried by each modulation symbol.

[0049] Optionally, Z0 is obtained according to the following calculation formula: Z0=function(α×(S1-S1+1) / M+δ), where M is the modulation order and M is a positive integer, α is a positive real number, δ is a non-negative integer, and function(x) represents rounding up, down, or to the nearest integer on the real number x.

[0050] Optionally, the value of S1 is determined by at least one of the following parameters: the length of the information packet bit sequence; the length of the bit sequence to be transmitted.

[0051] Optionally, the interleaving method is determined based on the modulation order.

[0052] Optionally, if the modulation order is greater than M0, the interleaving method is performed, wherein M0 is an integer greater than 1.

[0053] Optionally, the interleaving method is determined based on the code rate, wherein the code rate is equal to the ratio of the length of the information packet bit sequence to the bit sequence to be transmitted, and the code rate is a real number greater than 0 and less than 1.

[0054] Optionally, if the code rate is greater than R0, the interleaving method is performed, wherein R0 is a real number greater than 1 / 2 and less than 1.

[0055] Optionally, transmitting the bit sequence to be transmitted includes: dividing the bit sequence to be transmitted into multiple bit groups, interleaving the bits within each bit group, and then mapping each interleaved bit group to a constellation modulation symbol.

[0056] Optionally, the interleaving within the bit group is determined based on the modulation order.

[0057] Optionally, if the modulation order is greater than M1, the interleaving method is performed, wherein M1 is equal to 2, 3, 4, 5 or 6.

[0058] According to another embodiment of the present invention, a data encoding apparatus is also provided, comprising: an acquisition module for acquiring data to be transmitted; an interleaving module for performing quasi-cyclic LDPC encoding on the data to be transmitted to obtain an LDPC codeword sequence, and interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence; a selection module for performing cyclic bit selection on the interleaved LDPC codeword sequence from a starting position to obtain a rate-matched codeword sequence, wherein the starting position is determined according to predetermined parameters, wherein the predetermined parameters include at least one of the following: redundancy version, boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, system number of columns in the basic graph matrix, and length of the information packet bit sequence; and a transmission module for transmitting the rate-matched codeword sequence.

[0059] According to another embodiment of the present invention, a storage medium is also provided, the storage medium including a stored program, wherein the program, when executed, performs the method described in any of the above optional embodiments.

[0060] According to another embodiment of the present invention, a processor is also provided, the processor being used to run a program, wherein the program, when running, performs the method described in any of the above optional embodiments.

[0061] This invention obtains data to be transmitted; performs quasi-cyclic LDPC encoding on the data to be transmitted to obtain an LDPC codeword sequence; interleaves the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence; performs cyclic bit selection on the interleaved LDPC codeword sequence starting from a starting position to obtain a rate-matched codeword sequence, wherein the starting position is determined according to predetermined parameters; and transmits the rate-matched codeword sequence. This scheme solves the problem of unstable transmission after quasi-cyclic LDPC encoding of transmitted data in related technologies, and achieves stable transmission after quasi-cyclic LDPC encoding. Attached Figure Description

[0062] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0063] Figure 1 This is a flowchart of a data encoding method according to an embodiment of the present invention;

[0064] Figure 2 This is a flowchart of LDPC encoded data processing according to a preferred embodiment of the present invention. Detailed Implementation

[0065] This application provides a mobile communication network (including but not limited to a 5G mobile communication network), whose network architecture may include network-side devices (e.g., base stations) and terminals. This application also provides an information transmission method that can operate on the aforementioned network architecture. It should be noted that the operating environment of the information transmission method provided in this application is not limited to the aforementioned network architecture.

[0066] Example 1

[0067] This embodiment provides a data encoding method. Figure 1 This is a flowchart of a data encoding method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0068] Step S102: After performing quasi-cyclic LDPC encoding on the information block bit sequence, an LDPC codeword sequence is obtained, and the size of the one-dimensional finite-length circular buffer is determined based on the LDPC codeword sequence.

[0069] Step S104: Select a redundancy version value from multiple predetermined redundancy version values, and determine the starting position of reading the bit sequence to be transmitted from the one-dimensional finite-length circular buffer according to the selected redundancy version value and predefined parameters; wherein, the predefined parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, system number of columns in the basic graph matrix, and length of the information packet bit sequence;

[0070] Step S106: Starting from the starting position, sequentially read data bits of a specific length to form a bit sequence to be transmitted, and send the bit sequence to be transmitted.

[0071] Through the above steps, quasi-cyclic LDPC encoding of the information packet bit sequence yields an LDPC codeword sequence, and the size of a one-dimensional finite-length circular buffer is determined based on the LDPC codeword sequence. A redundancy version value is selected from multiple predetermined redundancy version values, and the starting position for reading the bit sequence to be transmitted from the one-dimensional finite-length circular buffer is determined based on the selected redundancy version value and predefined parameters. The predefined parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, systematic number of columns in the basic graph matrix, and length of the information packet bit sequence. Starting from the starting position, data bits of a specific length are sequentially read to form the bit sequence to be transmitted, and the bit sequence to be transmitted is then sent. This scheme solves the problem of unstable transmission after quasi-cyclic LDPC encoding of transmitted data in related technologies, achieving stable transmission after quasi-cyclic LDPC encoding.

[0072] Optionally, the entity performing the above steps may be a base station, a terminal, etc., but is not limited to these.

[0073] Optionally, the process of interleaving the LDPC codeword sequence to obtain the interleaved LDPC codeword sequence includes: performing block interleaving on the LDPC codeword sequence, wherein the number of rows of the interleaving matrix is ​​determined according to the quasi-cyclic LDPC coding parameters, wherein the quasi-cyclic LDPC coding parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, and systematic number of columns in the basic graph matrix, and the interleaving matrix is ​​column-in, column-out interleaved.

[0074] Optionally, the number of rows in the interleaving matrix is ​​equal to a positive integer factor of the quasi-cyclic LDPC boost value, or equal to a positive integer multiple of the boost value of the quasi-cyclic LDPC encoding.

[0075] Optionally, the number of rows in the interleaving matrix is ​​equal to a positive integer factor of the total number of columns in the basic graph matrix of the quasi-cyclic LDPC encoding, or equal to a positive integer multiple of the total number of columns in the basic graph matrix of the quasi-cyclic LDPC encoding.

[0076] Optionally, the interleaving method further includes: outputting the interleaved bit sequences in a predetermined column order.

[0077] Optionally, the interleaving method within the column can be determined based on the modulation order.

[0078] Optionally, if the modulation order is greater than M0, then the intra-column interleaving method is performed, where M0 is an integer greater than 1.

[0079] Optionally, the starting position is determined based on the redundant version, the boost value, and the total number of columns in the basic graph matrix.

[0080] Optionally, the starting position corresponding to the redundant version RVi is calculated using the following formula:

[0081] First formula: S i =α×funtion(β×(nb / G)×RV) i +χ)×Z+δ;

[0082] In the first formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive real number, χ is a non-negative real number, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0083] Alternatively, the second formula: S i =α×(β×funtion(λ×nb / G)×RV i+χ)×Z+δ;

[0084] In the second formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0085] Alternatively, the third formula: S i =α×(β×funtion(λ×nb×Z / G)×RV i +χ)+δ;

[0086] In the third formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0087] Optionally, the starting position is determined based on the redundant version, the boost value, the total number of rows in the basic graph matrix, and the length of the information block bit sequence.

[0088] Optionally, the starting position corresponding to the redundant version RVi is calculated using one of the following formulas:

[0089] S i =α×(β×funtion((K+mb×Z) / G)×RV i +χ)+δ;

[0090] S i =α×(β×funtion((K+mb×Z) / G)+χ)×RV i +δ

[0091] In the above two formulas, K is the length of the information block bit sequence, Z is the boost value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, and δ is an integer. Function(x) represents rounding up, down, or to the nearest integer on the real number x.

[0092] Optionally, interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence includes: interleaving all bits from bit S0 to bit S1 in the LDPC codeword sequence, wherein S0 and S1 are both positive integers, and S1 is greater than S0.

[0093] Optionally, interleaving all bits from bit S0 to bit S1 in the LDPC codeword sequence includes: performing block interleaving on all bits from bit S0 to bit S1 in the LDPC codeword sequence according to the interleaving matrix, wherein the number of columns of the block interleaving matrix is ​​Z0, which is determined by quasi-cyclic LDPC coding parameters, wherein the quasi-cyclic LDPC coding parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, and systematic number of columns in the basic graph matrix.

[0094] Optionally, Z0 is equal to a positive integer factor of the LDPC encoding boost value.

[0095] Optionally, Z0 is equal to Z, Z is the LDPC encoding boost value, S0 is equal to 2×Z, and S1 is equal to E×Z-1, where E is an integer greater than 2.

[0096] Optionally, E is equal to kb, kb+1, kb+2, kb+3, or kb+4, where kb is the number of columns in the basic graph matrix system of LDPC encoding.

[0097] Optionally, Z0 is determined by the following parameters: S0, S1, and modulation order, where the modulation order is the number of bits carried by each modulation symbol.

[0098] Alternatively, Z0 is obtained according to the following formula: Where M is the modulation order and M is a positive integer.

[0099] Optionally, the value of S1 may be determined by at least one of the following parameters: the length of the information block bit sequence obtained after segmenting the data to be transmitted into code blocks; and the length of the bit sequence to be transmitted.

[0100] Optionally, when the LDCP coding rate R is less than or equal to R0, all bits from bit S0 to bit S1 in the LDPC codeword sequence are interleaved according to the interleaving matrix, where R0 is a real number greater than or equal to 3 / 4 and less than 1, and the LDCP coding rate R is equal to the quotient of the length of the information block bit sequence and the length of the bit sequence to be transmitted.

[0101] The following detailed description is based on preferred embodiments of the present invention.

[0102] Preferred embodiment 1

[0103] This embodiment provides a quasi-cyclic LDPC coding data processing method that can be used in NR (New Radio Access Technology) communication systems. The method proposed in this optional embodiment can be used in LTE mobile communication systems, future fifth-generation (5G) mobile communication systems, or other wireless and wired communication systems. The data transmission direction is either the base station sending data to the mobile user (downlink transmission service data) or the mobile user sending data to the base station (uplink transmission service data). Mobile user includes: mobile device, access terminal, user terminal, user station, user unit, mobile station, remote station, remote terminal, user agent, user equipment, user device, or other terms. A base station includes an access point (AP), or may be referred to as a node B, radio network controller (RNC), evolved node B (eNB), base station controller (BSC), base transceiver station (BTS), base station (BS), transceiver function (TF), radio router, radio transceiver, basic service unit, extended service unit, radio base station (RBS), or some other terminology.

[0104] According to one aspect of this optional embodiment, the quasi-cyclic LDPC coded data processing method provided by this optional embodiment can be applied to enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), or massive machine-type communications (mMTC) scenarios in new radio access technology (new RAT).

[0105] Figure 2 This is a flowchart of LDPC encoded data processing according to a preferred embodiment of the present invention, such as... Figure 2 As shown, it includes the following steps:

[0106] Step S201: Obtain the length information of the source data packet to be transmitted; determine the length of the source data packet to be transmitted (also called the Transport Block Size, TBS) to be sent from the TBS table based on the control information. The control information can be obtained from downlink control information, uplink control information, or other system information.

[0107] Step S202, code block segmentation; the source data packet to be transmitted is segmented according to the longest information block length Kmax, wherein the number of information block bit sequences obtained from the segmentation is The length of the information block bit sequence obtained after code block segmentation includes: and Where K is the length of the information block bit sequence, K is a positive integer, Kmax is a positive integer, and L is the length of the CRC sequence added to each information block bit sequence.

[0108] Step S203, add a CRC sequence; after code block segmentation, obtain an L-bit CRC (Cyclic Redundancy Check) sequence for each information bit block, where L is an integer greater than 0.

[0109] Step S204, Fill bits; Fill the information bit block after adding the CRC sequence with sub-bits, where the sub-bits are only used for auxiliary encoding and are not transmitted.

[0110] Step S205, Quasi-cyclic LDPC encoding: Determine the boost value used for LDPC encoding based on the length of each information block bit sequence obtained after code block segmentation, determine and calculate the LDPC encoding parity check matrix based on the obtained boost value information, and perform quasi-cyclic LDPC encoding on each information block bit sequence corresponding to the parity check matrix and the LDPC encoding boost value to obtain the LDPC codeword sequence.

[0111] The quasi-cyclic LDPC encoding uses two types of base graph matrices: base graph 1 and base graph 2. Base graph 1 has 46 rows and 68 columns; base graph 2 has 42 rows and 52 columns. Table 1 shows the corresponding row index "i" positions in base graph 1 and base graph 2, indicating positions that can be replaced by cyclic permutation identity matrix positions. Table 2 corresponds to the lift values ​​supported by base graph 1, including 8 lift value sets; Table 4 corresponds to the lift values ​​supported by base graph 2, also including 8 lift value sets. The lift value set index i is determined based on the lift value information described above. LSAccording to the index number i of the set of promotion values LS Obtain the shift value matrix corresponding to each lift set from the base graph 1 matrix in Table 3, and alternatively, obtain the shift value matrix corresponding to each lift set from the base graph 2 matrix in Table 5 based on the lift set index number. Then, apply formula P... i,j =mod(V i,j Z c You can then obtain the corresponding boost value Z. c The base graph matrix. If the bit sequence size of the information block is less than or equal to 2560 and the code rate is less than or equal to 2 / 3, then the base graph matrix 2 is selected; otherwise, the base graph matrix 1 is selected. Note: In Table 1, the first column corresponds to the row index i indicating the base graph matrix 1 and the base graph matrix 2; the second column corresponds to the column index j indicating the base graph matrix 1; [i,j] together determine the "1" position of the base graph matrix 1; and the third column corresponds to the column index j indicating the base graph matrix 2. Tables 3 and 4 respectively illustrate the 8 shift value matrices corresponding to the base graph matrix 1 and the base graph matrix 2, where i indicates the row index and j indicates the column index. LS It is used to indicate the index number of the promoted value set.

[0112] Table 1 shows the base graph matrices 1 and 2.

[0113]

[0114] Table 2 shows the lift values ​​for base graph 1.

[0115]

[0116] The shift values ​​for base graph 1 are shown in Table 3 below.

[0117]

[0118]

[0119] Table 4 shows the lift values ​​for base graph 2.

[0120]

[0121] The shift values ​​for base graph 2 are shown in Table 5 below.

[0122]

[0123]

[0124] Step S206, Interleaving (another part of sovereignty); the interleaving is to interleave the LDPC codeword sequence to obtain the interleaved LDPC codeword sequence. The interleaving method includes: performing block interleaving on the LDPC codeword sequence, wherein the number of rows of the interleaving matrix is ​​determined according to quasi-cyclic LDPC coding parameters, wherein the quasi-cyclic LDPC coding parameters include at least one of the following: boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, and systematic number of columns in the basic graph matrix.

[0125] Preferably, in one specific embodiment, the number of rows of the interleaving matrix is ​​equal to a positive integer factor of the quasi-cyclic LDPC boost value, or equal to a positive integer multiple of the boost value of the quasi-cyclic LDPC encoding.

[0126] Preferably, in one specific embodiment, the number of rows of the interleaving matrix is ​​equal to a positive integer factor of the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding, or equal to a positive integer multiple of the total number of columns of the basic graph matrix of the quasi-cyclic LDPC encoding.

[0127] Preferably, in one embodiment, the interleaving matrix is ​​column-in-column interleaving.

[0128] Preferably, in one specific embodiment, in the interleaving method, the interleaved bit sequence is obtained by outputting according to a predetermined column order.

[0129] Preferably, in one specific embodiment, the interleaving method involves performing intra-column interleaving on each column of the interleaving matrix, wherein the intra-column interleaving method includes: cyclic shift interleaving and random sequence interleaving. Preferably, the intra-column interleaving method is determined based on the modulation order. Preferably, if the modulation order is greater than 2, the intra-column interleaving method is executed.

[0130] The interleaving method is characterized by: mapping all bits from bit S0 to bit S1 in the LDPC codeword sequence to bits S0 to S1 of the interleaved codeword sequence according to a predetermined interleaving index sequence, wherein S0 is a positive integer and S1 is an integer greater than S0.

[0131] The feature is that the predetermined interleaving index sequence is obtained according to the block interleaving method, the number of columns of the block interleaving matrix is ​​Z0, and Z0 is a positive integer.

[0132] Preferably, in a more specific embodiment, Z0 is equal to a positive integer factor of the LDPC encoding boost value.

[0133] Preferably, in a more specific embodiment, Z0 equals Z, Z is the LDPC encoding boost value, S0 equals 2×Z, and S1 equals E×Z-1, where E is an integer greater than 2. Further, E equals kb, kb+1, kb+2, kb+3, or kb+4, where kb is the number of columns in the basic graph matrix system of the LDPC encoding.

[0134] Preferably, in a more specific embodiment, S0 equals kb × Z, S1 equals E × Z - 1, where Z is the LDPC coding boost value, E equals kb + Δmb, and Δmb is an integer greater than 0, and kb is the number of systematic columns in the LDPC coding fundamental graph matrix. Further, Δmb is determined according to one of the following parameter combinations: combination 1, the number of systematic columns in the LDPC coding fundamental graph matrix and the coding rate; combination 2, the length of the information block bit sequence, the length of the bit sequence to be transmitted, and the LDPC coding boost value; combination 3, the number of LDPC code parity bits in the bit sequence to be transmitted and the LDPC coding boost value.

[0135] In a more specific embodiment, the Z0 is determined by the following parameters: S0, S1, and modulation order, wherein the modulation order is the number of bits carried by each modulation symbol. Preferably, the Z0 is obtained according to the following formula: Where M is the modulation order and M is a positive integer.

[0136] In a more specific embodiment, the specific value of S1 is determined by the following parameters: the length of the information packet bit sequence and the length of the bit sequence to be transmitted.

[0137] In a more specific embodiment, the block interleaving described above is performed when the code rate R is less than or equal to R0, wherein R0 is a real number greater than or equal to 3 / 4 and less than 1, and the code rate R is equal to the value obtained by dividing the length of the information block bit sequence by the length of the bit sequence to be transmitted.

[0138] The advantages of the interleaving method described above are: it can very effectively randomize LDPC codewords, enabling LDPC codes to achieve better performance advantages in high-order modulation (such as 64QAM and 256QAM); and it can effectively improve the performance of LDPC codes in fading channels.

[0139] Step S207, rate matching; cyclic bit selection is performed on the interleaved LDPC codeword sequence starting from the beginning position to obtain a rate-matched codeword sequence. The characteristic is that the beginning position is determined according to predetermined parameters, wherein the predetermined parameters include at least one of the following: redundancy version, boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, systematic number of columns in the basic graph matrix, and length of the information block bit sequence.

[0140] Preferably, in one specific embodiment, the starting position is determined based on the redundant version, the boost value, and the total number of columns in the basic graph matrix. Further, the starting position corresponding to the redundant version RVi is calculated using the following formula:

[0141] S i =α×funtion(β×(nb / G)×RV) i +χ)×Z+δ

[0142] In the formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive real number, χ is a non-negative real number, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0143] Furthermore, the starting position corresponding to the redundant version RVi is calculated using the following formula:

[0144] S i =α×(β×funtion(λ×nb / G)×RV i +χ)×Z+δ

[0145] In the formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0146] Furthermore, the starting position corresponding to the redundant version RVi is calculated using the following formula:

[0147] S i =α×(β×funtion(λ×nb×Z / G)×RV i +χ)+δ

[0148] In the formula, nb is the total number of columns in the basic graph matrix, Z is the lift value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, rounding down, or rounding to the nearest integer on the real number x.

[0149] Preferably, in one specific embodiment, the starting position is determined based on the redundancy version, the boost value, the total number of rows in the basic graph matrix, and the length of the information block bit sequence. Further, the starting position corresponding to the redundancy version RVi is calculated using one of the following formulas:

[0150] S i =α×(β×funtion((K+mb×Z) / G)×RV i +χ)+δ;

[0151] S i =α×(β×funtion((K+mb×Z) / G)+χ)×RV i +δ

[0152] In the formula, K is the length of the information block bit sequence, Z is the boost value, G is a real number greater than 0, α is a positive integer, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, and function(x) represents rounding up, down, or to the nearest integer on the real number x.

[0153] Cyclic bit selection is performed on the interleaved codeword sequence. The 2nd × Z bit to the last bit of the interleaved codeword sequence is stored in a cyclic buffer. N bits are sequentially obtained from the cyclic buffer according to the redundancy version to form the bit sequence to be transmitted.

[0154] Step S208, constellation modulation; the bit sequence to be transmitted is divided into multiple bit groups, the multiple bit groups are mapped onto constellation modulation symbols, and the constellation modulation symbols are transmitted. In a preferred embodiment, before mapping to the constellation modulation symbols, the bits within each bit group are interleaved, and then each interleaved bit group is mapped onto the constellation modulation symbols. The modulation order of the constellation modulation symbols is M, where the modulation order represents the number of bits carried by each constellation modulation symbol. Constellation symbol modulation includes one of the following: BPSK, QPSK, 16QAM, 64QAM, and 256QAM, and their corresponding modulation orders are 1, 2, 4, 6, and 8, respectively. Preferably, in a specific embodiment, the interleaving within the bit group is determined according to the modulation order. If the modulation order is greater than M1, the interleaving method is executed, where M1 is equal to 2, 3, 4, 5, or 6. Preferably, the interleaving within the bit group includes: cyclic shift interleaving and random index number interleaving. Preferably, the interleaving methods for any F adjacent constellation symbols in all constellation modulation symbols are different, where F is a positive integer. In another embodiment, there are G0 interleaving methods within bit blocks, and these G0 methods are not identical. The bit interleaving within each bit block selects G1 methods from the G0 interleaving methods and interleaves the bits within each bit block sequentially in a certain order. In yet another embodiment, there are multiple sets of bit-block interleaving methods, and the bit-block interleaving method is determined from these multiple sets of interleaving methods based on the modulation order.

[0155] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0156] Example 2

[0157] This embodiment also provides a data encoding device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0158] According to another embodiment of the present invention, a data encoding device is also provided, comprising:

[0159] The acquisition module is used to acquire data to be sent.

[0160] An interleaving module, connected to the acquisition module, is used to perform quasi-cyclic LDPC encoding on the data to be sent to obtain an LDPC codeword sequence, and interleave the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence.

[0161] The selection module, connected to the interleaving module, is used to perform cyclic bit selection on the interleaved LDPC codeword sequence from the starting position to obtain a rate-matched codeword sequence. The starting position is determined according to predetermined parameters, which include at least one of the following: redundancy version, boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, system number of columns in the basic graph matrix, and length of the information block bit sequence.

[0162] A sending module, connected to the selection module, is used to send the rate-matched codeword sequence.

[0163] It should be added that all the method steps in Embodiment 1 can be executed by the device in this embodiment.

[0164] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0165] Example 3

[0166] According to another embodiment of the present invention, a processor is also provided, the processor being used to run a program, wherein the program, when running, performs the method described in any of the above optional embodiments.

[0167] Example 4

[0168] According to another embodiment of the present invention, a storage medium is also provided, the storage medium including a stored program, wherein the program, when executed, performs the method described in any of the above optional embodiments.

[0169] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0170] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low density parity check (LDPC) data encoding method, characterized by, include: LDPC codeword sequence is obtained by performing LDPC encoding on the information block bit sequence; Interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence includes: mapping all bits from bit S0 to bit S1 in the LDPC codeword sequence to bits S0 to S1 in the interleaved LDPC codeword sequence according to a predetermined interleaving index sequence, where S0 is a positive integer and S1 is an integer greater than S0. The interleaved LDPC codeword sequence is subjected to cyclic bit selection starting from the beginning position to obtain a rate-matched LDPC codeword sequence; and Send the rate-matched LDPC codeword sequence; Wherein, the value of S0 is equal to 2×Z, where Z is the LDPC coding boost value; wherein, the value of S1 is determined by at least one of the following parameters: the length of the information block bit sequence, the length of the bit sequence to be transmitted.

2. The method of claim 1, wherein, The starting position is determined based on the redundancy version value, the LDPC encoding boost value, and the length of the information block bit sequence.

3. The method according to claim 1, characterized in that, The starting position Si corresponding to the redundancy version of is calculated by the following equation: First formula: ; In the first formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding lift value, α is a positive integer, G is a real number greater than 0, β is a positive real number, χ is a non-negative real number, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version. Alternatively, the second formula: ; In the second formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding lift value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version; Alternatively, the third formula: ; In the third formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding boost value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version.

4. The method according to claim 1, characterized in that, The predetermined interleaving index sequence is obtained using a block interleaving method. The number of columns in the block interleaving matrix is ​​Z0, where Z0 is determined by quasi-cyclic LDPC coding parameters. The quasi-cyclic LDPC coding parameters include at least one of the following: LDPC coding boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, system column number in the basic graph matrix, or length of the information block bit sequence.

5. The method according to claim 1, characterized in that, S1 is equal to a positive integer multiple of the LDPC encoding boost value.

6. The method according to claim 1, characterized in that, The transmission of the rate-matched LDPC codeword sequence includes: The rate-matched LDPC codeword sequence is divided into multiple bit groups, the bits within each bit group are interleaved, and each interleaved bit group is mapped to a constellation modulation symbol.

7. A low-density parity-check (LDPC) data encoding device, characterized in that, include: Interleaving module, the interleaving module is used for: LDPC codeword sequence is obtained by performing LDPC encoding on the information block bit sequence; Interleaving the LDPC codeword sequence to obtain an interleaved LDPC codeword sequence includes: mapping all bits from bit S0 to bit S1 in the LDPC codeword sequence to bits S0 to S1 in the interleaved LDPC codeword sequence according to a predetermined interleaving index sequence, where S0 is a positive integer and S1 is an integer greater than S0. A selection module, configured to perform cyclic bit selection on the interleaved LDPC codeword sequence starting from the beginning position to obtain a rate-matched LDPC codeword sequence; and The sending module is used to send the rate-matched LDPC codeword sequence; Wherein, the value of S0 is equal to 2×Z, and Z is the LDPC coding boost value; S1 is determined by at least one of the following parameters: the length of the information block bit sequence and the length of the bit sequence to be transmitted.

8. The apparatus according to claim 7, characterized in that, The starting position is determined based on the redundancy version value, the LDPC encoding boost value, and the length of the information block bit sequence.

9. The apparatus according to claim 7, characterized in that, The corresponding redundant version is The starting position S i It is calculated using the following formula: First formula: ; In the first formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding lift value, α is a positive integer, G is a real number greater than 0, β is a positive real number, χ is a non-negative real number, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version. Alternatively, the second formula: ; In the second formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding lift value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version; Alternatively, the third formula: ; In the third formula, nb is the total number of columns in the LDPC encoding basic graph matrix, Z is the LDPC encoding boost value, α is a positive integer, G is a real number greater than 0, β is a positive integer, λ is a positive real number, χ is a non-negative integer, δ is an integer, function(x) represents rounding the real number x up or down to the nearest integer, and i represents the index of the redundant version.

10. The apparatus according to claim 7, characterized in that, The predetermined interleaving index sequence is obtained using a block interleaving method. The number of columns in the block interleaving matrix is ​​Z0, where Z0 is determined by quasi-cyclic LDPC coding parameters. The quasi-cyclic LDPC coding parameters include at least one of the following: LDPC coding boost value, total number of columns in the basic graph matrix, total number of rows in the basic graph matrix, system column number in the basic graph matrix, or length of the information block bit sequence.

11. The apparatus according to claim 7, characterized in that, S1 is equal to a positive integer multiple of the LDPC encoding boost value.

12. The apparatus according to claim 7, characterized in that, The transmission of the rate-matched LDPC codeword sequence includes: The rate-matched LDPC codeword sequence is divided into multiple bit groups, the bits within each bit group are interleaved, and each interleaved bit group is mapped to a constellation modulation symbol.

13. A storage medium comprising a stored program, characterized in that, When the program is executed by a processor, the program performs the method of any one of claims 1 to 6.

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