Semiconductor memory devices and their operation methods

Abstract

This technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes: a memory cell array comprising a plurality of memory blocks; peripheral circuitry configured to perform a programming operation on a selected memory block among the plurality of memory blocks; and control logic configured to control the peripheral circuitry to perform a hold-accelerate operation, including boosting the channels of the plurality of cell strings included in the selected memory block, between a programming voltage application operation and a programming verification operation during the programming operation.

Description

Technical Field

[0001] One or more embodiments described herein relate to a semiconductor memory device and a method of operating a semiconductor memory device. Background Technology

[0002] Semiconductor memory devices are made using semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP).

[0003] Volatile semiconductor memory devices store data when power is off. Examples include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile semiconductor memory devices retain stored data even when power is off. Examples include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Examples of flash memory include NOR and NAND types. Summary of the Invention

[0004] One or more embodiments described herein provide a semiconductor memory device, for example, which may have an improved threshold voltage distribution of memory cells during programming operations.

[0005] One or more embodiments described herein provide a method for operating, for example, a semiconductor memory device that may have an improved threshold voltage distribution.

[0006] According to an embodiment of the present disclosure, a semiconductor memory device includes: a memory cell array including a plurality of memory blocks; peripheral circuitry configured to perform a programming operation on a selected memory block among the plurality of memory blocks; and control logic configured to control the peripheral circuitry to perform a retention acceleration operation, including boosting the channels of a plurality of cell strings included in the selected memory block, between a programming voltage application operation and a programming verification operation during the programming operation.

[0007] According to an embodiment of this disclosure, a semiconductor memory device includes: a memory block including memory cells programmed into a plurality of programming states; peripheral circuitry configured to perform programming operations including a plurality of programming cycles on the memory block; and control logic configured to control the peripheral circuitry to perform the plurality of programming cycles. The control logic is configured to control the peripheral circuitry to perform a hold-up acceleration operation during the current programming cycle when a programming operation is determined to be successful as a result of a programming verification operation of a previous programming cycle among the plurality of programming cycles.

[0008] According to an embodiment of the present disclosure, a method of operating a semiconductor memory device includes: performing a programming voltage application operation to apply a programming voltage to a selected word line among a plurality of word lines connected to a cell string, the cell string including a plurality of memory cells programmed into a plurality of programming states; performing a programming verification operation on the memory cells connected to the selected word line; and performing a hold-up acceleration operation by boosting the channel of the cell string when programming is determined to be successful as a result of the programming verification operation.

[0009] This technology can improve the retention degradation characteristics of semiconductor memory devices during programming operations, thereby improving the phenomenon that the threshold voltage distribution of memory cells is altered. Attached Figure Description

[0010] Figure 1 An embodiment of a semiconductor memory device is illustrated.

[0011] Figure 2 An implementation of a memory cell array is illustrated.

[0012] Figure 3 An example of how to implement a storage block is given.

[0013] Figure 4 An example of how to implement a storage block is given.

[0014] Figure 5 An example of how to implement a storage block is given.

[0015] Figure 6 An example of the programming states for a three-level unit is shown.

[0016] Figure 7 An example of how programming operations can be implemented is given.

[0017] Figure 8 and Figure 9 An example of how programming operations can be implemented is given.

[0018] Figure 10 An example of how to implement a programming loop is given.

[0019] Figure 11An example of an implementation of a memory system is given.

[0020] Figure 12 An example of an application of a memory system is shown.

[0021] Figure 13 An example of how to implement a computing system is given. Detailed Implementation

[0022] The structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein can be implemented in various forms and are not limited to those described in this specification or application.

[0023] In the following description, embodiments will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement the technical spirit of this disclosure.

[0024] Figure 1 This diagram illustrates an embodiment of a semiconductor memory device 100, which may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The peripheral circuitry can perform various operations, such as programming operations for storing data in the memory cell array 110, reading operations for outputting the stored data, and erasing operations for erasing the stored data. The control logic 130 can control the peripheral circuitry 120 and perform other operations.

[0025] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Local lines LL and bit lines BL1 to BLm (where m is a positive integer) may be connected to each of the memory blocks BLK1 to BLKz. For example, the local line LL may include a first select line, a second select line, and multiple word lines disposed between the first and second select lines. Additionally, the local line LL may include dummy lines disposed between the first select line and the word lines, and between the second select line and the word lines. The first select line may be a source select line, and the second select line may be a drain select line. For example, the local line LL may include word lines, drain select lines, and source select lines.

[0026] In one implementation, the local line LL may also include a dummy line. For example, the local line LL may also include a pipe line. The local lines LL may be connected to memory blocks BLK1 to BLKz respectively, and the bit lines BL1 to BLM may be connected together to memory blocks BLK1 to BLKz.

[0027] The memory blocks BLK1 to BLKz can have a two-dimensional or three-dimensional structure. For example, in a two-dimensional structure, the memory cells can be arranged in a direction parallel to the substrate. In a three-dimensional structure, the memory cells can be stacked on the substrate in a vertical direction.

[0028] The peripheral circuit 120 can be configured to perform programming, reading and / or erasing operations on the selected memory block under the control of the control logic 130.

[0029] In one embodiment, the peripheral circuitry 120 may include a voltage generation circuitry 121, a row decoder 122, a page buffer group 123, a column decoder 124, an input / output circuitry 125, a pass / fail determiner (pass / fail check circuitry) 126, and a source line driver 127.

[0030] The voltage generation circuit 121 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OP_CMD. Additionally, the voltage generation circuit 121 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 121 can generate programming voltage, verification voltage, and pass voltage under the control of control logic 130.

[0031] During the hold-up acceleration operation in the programming process, the voltage generation circuit 121 can generate a first setting voltage to be applied to the unselected word line and a second setting voltage to be applied to the selected word line. The second setting voltage can be a voltage with a potential different from (e.g., lower than) the first setting voltage. For example, the first setting voltage can be a positive voltage with a high potential, and the second setting voltage can be a voltage of 0V.

[0032] The row decoder 122 can transmit an operating voltage Vop to the local line LL connected to the selected memory block in response to the row decoder control signal AD_signals. For example, during programming operations, the row decoder 122 can apply a programming voltage generated by the voltage generation circuit 121 to the selected word line in the selected local line LL of the selected memory block in response to the row decoder control signal AD_signals, and can apply a pass voltage generated by the voltage generation circuit 121 to the unselected word line.

[0033] During the hold-up acceleration operation in the programming operation, the line decoder 122 can apply a first setting voltage generated by the voltage generation circuit 121 to the unselected word line of the selected memory block and a second setting voltage generated by the voltage generation circuit 121 to the selected word line. Additionally, during the hold-up acceleration operation in the programming operation, the line decoder 122 can turn off the drain select transistor and source select transistor of the selected memory block by applying a cutoff voltage to the drain select line and source select line of the selected memory block.

[0034] Page buffer group 123 may include multiple page buffers PB1 to PBm connected to bit lines BL1 to BLm. Page buffers PB1 to PBm may operate in response to the page buffer control signal PBSIGNALS. For example, page buffers PB1 to PBm may temporarily store data to be programmed during a programming operation and adjust the potential levels of bit lines BL1 to BLm based on the temporarily stored data. Additionally, page buffers PB1 to PBm may sense the voltage or current of bit lines BL1 to BLm during read operations or program verification operations.

[0035] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the page buffers PB1 to PBm via the data lines DL, or it can exchange data with the input / output circuitry 125 via the column lines CL.

[0036] The input / output circuit 125 can transmit commands (CMD) and addresses (ADD) (e.g., received from an external source) to the control logic 130, or exchange data (DATA) with the column decoder 124.

[0037] During a read operation or a programming verification operation, the pass / fail determiner 126 can generate a reference current in response to the enable bit VRY_BIT<#>, compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current, and output a pass signal PASS or a failure signal FAIL. The sensed voltage VPB can be controlled, for example, based on the number of memory cells determined to pass during the programming verification operation.

[0038] The source line driver 127 can be connected to a memory cell in the memory cell array 110 via the source line SL, and can control the voltage applied to the source line SL. The source line driver 127 can receive the source line control signal CTRL_SL from the control logic 130 and control the voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0039] In response to the command CMD and address ADD, control logic 130 can control peripheral circuitry 120 by outputting the operation signal OP_CMD, the row decoder control signal AD_signals, the page buffer control signal PBSIGNALS, and the enable bit VRY_BIT<#>. Control logic 130 can control peripheral circuitry 120 to sequentially execute multiple programming cycles during programming operations on selected pages of the selected memory block, thereby programming memory cells in the selected pages into one or more programming states.

[0040] For example, each programming cycle may include a programming voltage application operation and a programming verification operation performed sequentially. Some programming cycles may include a hold-up operation. For example, when programming is determined to be successful as a result of a programming verification operation, a hold-up operation may be included in the corresponding programming cycle, or it may be included in the next programming cycle. For example, when programming is determined to be successful as a result of a programming verification operation in the corresponding programming cycle, the hold-up operation may be performed immediately after the completion of the programming verification operation, or it may be performed before the programming voltage application operation or programming verification operation of the next programming cycle.

[0041] During the programming operation of a memory cell, charge can be trapped in the charge storage layer of the memory cell. Some of the trapped charge may be trapped in an unstable state. Within a predetermined time after the programming operation is completed, the charge trapped in the unstable state may be untrapped in the charge storage layer. This may result in a decrease in the threshold voltage of the memory cell (e.g., one or more of its transistors).

[0042] In one implementation, during the programming operation, a hold-up acceleration operation can be performed when programming is determined to be successful as a result of a programming verification operation corresponding to multiple programming states. During the hold-up acceleration operation, control logic 130 controls peripheral circuitry 120 to self-boost the channels of one or more strings in the selected memory blocks.

[0043] For example, with the source and drain selection transistors of the selected memory block off, the potential of the channel in the string within the selected memory block is increased by applying a high-potential first setting voltage to the unselected word line. At this time, charge trapped in an unstable state can be removed from the charge trapped in the memory cell connected to the selected word line. This can be achieved by applying a 0V second setting voltage to the selected word line. Therefore, the retention characteristics of the memory cell and the phenomenon of altered threshold voltage distribution can be improved.

[0044] Figure 2 This is an example Figure 1 A diagram illustrating an embodiment of the memory cell array 110.

[0045] Reference Figure 2 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure and may include multiple memory cells stacked on a substrate. The memory cells may be arranged along the +X, +Y, and +Z directions. (Refer to...) Figures 3 to 5 An example describing the structure of each storage block.

[0046] Figure 3 For example, it could be... Figure 2 A circuit diagram of an implementation of storage block BLK1, which is represented by storage block BLK1 to BLKz.

[0047] Reference Figure 3 Storage block BLK1 includes multiple cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed into a predetermined shape, such as a "U" shape or another shape. In storage block BLK1, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 3 In this diagram, two unit strings are arranged in the column direction (e.g., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0048] Each of the cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0049] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In an embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In an embodiment, pillars for providing the channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating film, a charge storage film, or a barrier insulating film.

[0050] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp. In this implementation, the source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction. The source select transistors of cell strings arranged in different rows can be connected to different source select lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0051] In one implementation, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0052] The first memory cells MC1 to nth memory cells MCn in each cell string are connected between the source selection transistor SST and the drain selection transistor DST. The first memory cells MC1 to nth memory cells MCn may include first memory cells MC1 to pth memory cells MCp and (p+1)th memory cells MCp+1 to nth memory cells MCn. The first memory cells MC1 to pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to pth memory cells MCp and the (p+1)th memory cells MCp+1 to nth memory cells MCn are connected to each other via the transistor PT. The gates of the first memory cells MC1 to nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0053] The gate of the tubular transistor PT in each unit string is connected to the pipe line PL.

[0054] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0055] A string of cells arranged in the column direction is connected to a bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0056] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, in the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 constitute one page. In the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 constitute another page. A cell string arranged in a row direction can be selected by selecting one of the drain selection lines DSL1 or DSL2. A page in the selected cell string can be selected by selecting one of the word lines WL1 to WLn.

[0057] In one implementation, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines BL1 to the m-th bit lines BLm. Additionally, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0058] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. In one implementation, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. The more dummy memory cells provided, the better the operational reliability of the memory block BLK1, but the larger the size of the memory block BLK1. Conversely, the smaller the dummy memory cells provided, the smaller the size of the memory block BLK1 can be, but the operational reliability of the memory block BLK1 may decrease.

[0059] To efficiently control at least one dummy memory cell, each dummy memory cell may have a threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLK1. When an erase operation is performed after a programming operation, the dummy memory cell may have a threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0060] Figure 4 For example, it could be... Figure 2 A circuit diagram of an implementation of storage block BLK2, which is represented by storage block BLK1 to BLKz.

[0061] Reference Figure 4 The memory block BLK2 includes multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along the +Z direction. Each of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST, all stacked on a substrate beneath the memory block BLK2.

[0062] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a single source select line.

[0063] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0064] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0065] As a result, in addition to excluding the tubular transistor PT from each cell string, Figure 4 The storage block BLK2 has the same as Figure 3 The equivalent circuit of the storage block BLK1 is similar to the equivalent circuit.

[0066] In one implementation, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings in the row-direction cell strings CS11′ to CS1m′ or CS21′ to CS2m′ can be connected to the even-numbered bit lines, and odd-numbered cell strings in the row-direction cell strings CS11′ to CS1m′ or CS21′ to CS2m′ can be connected to the odd-numbered bit lines.

[0067] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. In one implementation, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. The more dummy memory cells provided, the better the operational reliability of the memory block BLK2, but the larger the size of the memory block BLK2. Conversely, the smaller the dummy memory cells provided, the smaller the size of the memory block BLK2 can be, but the operational reliability of the memory block BLK2 may decrease.

[0068] To efficiently control at least one dummy memory cell, each dummy memory cell can have a threshold voltage. Programming operations can be performed on all or part of the dummy memory cells before or after an erase operation on memory block BLK2. When an erase operation is performed after a programming operation, the dummy memory cell can have a threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0069] Figure 5 For example, it could be... Figure 1 A circuit diagram of an implementation of a memory block BLK3, representing memory block BLK1 to BLK2 in the memory cell array 110.

[0070] Reference Figure 5 The memory block BLK3 may include multiple cell strings CS1 to CSm connected to multiple bit lines BL1 to BLm respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0071] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In an embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In an embodiment, pillars for providing the channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0072] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and memory cells MC1 to MCn. The first memory cell MC1 to the nth memory cell MCn of each cell string is connected between the source select transistor (SST) and the drain select transistor (DST). The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0073] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any one of the word lines WL1 to WLn.

[0074] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines BL1 to the m-th bit lines BLm. The even-numbered cell strings among the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0075] As mentioned above, memory cells connected to a word line can form a physical page. Figure 5 In the example, within the memory cells belonging to memory block BLK3, m memory cells connected to any one of the word lines WL1 to WLn constitute a physical page.

[0076] The memory cell array 110 of the semiconductor memory device 100 can be configured as a three-dimensional structure (e.g., as shown in the image). Figure 3 and Figure 4 (as shown) or two-dimensional structures (e.g., such as) Figure 5 (As shown).

[0077] Figure 6 This is a diagram illustrating an example of the programming states of a three-level cell (TLC). (See reference...) Figure 6 In this example, the three-level unit has threshold voltage states corresponding to an erase state E and seven programming states P1 to P7, respectively. The erase state E and the first programming states P1 to the seventh programming states P7 have corresponding bit codes; for example, different bit codes can be assigned to one of the corresponding erase state E and the first programming states P1 to the seventh programming states P7.

[0078] Each threshold voltage state can be classified based on the first read voltage R1 to the seventh read voltage R7. Furthermore, the first verification voltage VR1 to the seventh verification voltage VR7 can be used to determine whether the programming of the memory cell corresponding to each programming state is complete.

[0079] For example, a second verification voltage VR2 is applied to the word line to verify the memory cell in the selected physical page that corresponds to the second programming state P2. At this time, as... Figure 1 The page buffer PB1 shown can sense the current of bit line BL1 to distinguish whether the target memory cell connected to bit line BL1 is in an incomplete programming state or a completed programming state.

[0080] Figure 6 An example of a target programming state for a TLC is shown, but one or more different target programming states may be used in other embodiments. In one embodiment, the memory cell in the semiconductor memory device may be a multilevel cell (MLC). In one embodiment, the memory cell in the semiconductor memory device may be a quad-level cell (QLC).

[0081] Figure 7 This is a diagram illustrating an implementation of a programming operation, depicting the programming of memory cells using the TLC method as an example. See below for reference. Figure 6 and Figure 7 To describe programming operations.

[0082] Reference Figure 6 and Figure 7 This document illustrates an implementation of programming operations performed for first programming states P1 through seventh programming states P7. In the programming operations, multiple programming loops LOOP1 through LOOP9 corresponding to the first programming states P1 through seventh programming states P7 are executed sequentially. For example, programming loops LOOP1 and LOOP2 correspond to the first programming state P1, and programming loop LOOP3 corresponds to the second programming state P2. Furthermore, programming loop LOOP4 may correspond to the third programming state P3, programming loop LOOP5 may correspond to the fourth programming state P4, programming loop LOOP6 may correspond to the fifth programming state P5, programming loop LOOP7 may correspond to the sixth programming state P6, and programming loops LOOP8 and LOOP9 may correspond to the seventh programming state P7.

[0083] Each of the programming loops LOOP1 through LOOP9 may include a programming voltage application operation and at least one programming verification operation. Additionally, some programming loops may include a programming voltage application operation, at least one programming verification operation, and a hold-acceleration operation. For example, when programming is determined to be successful as a result of the programming verification operation, a hold-acceleration operation may be performed in the corresponding programming loop, or in the next programming loop.

[0084] As a result of the programming verification operation in each programming cycle, programming can be considered successful when the programming of a memory cell to be programmed to the programming state corresponding to the programming cycle is completed more than a set number of times. For example, when programming for the first programming state P1 is determined to be successful (P1-PASS) as a result of the programming verification operation of programming cycle LOOP2, a hold-up acceleration operation can be performed after the programming verification operation is completed in the corresponding programming cycle LOOP2, or a hold-up acceleration operation can be performed before the programming voltage application operation or programming verification operation in the next programming cycle LOOP3.

[0085] Figure 8 and Figure 9 It is a flowchart illustrating the implementation of programming operations, and Figure 10 Examples Figure 7 This describes the implementation of one of the programming loops within a programming loop. For example, it can be referred to as follows: Figure 1 , Figure 5 and Figures 8 to 10 This describes the implementation method of the programming operation.

[0086] As an example, it is described Figure 7 Programming loop LOOP3 is one of the programming loops LOOP1 to LOOP9. For example, the case where programming loop LOOP3 is executed after the programming verification operation for the first programming state P1 in the previous programming loop LOOP2 has been determined to be P1-PASS.

[0087] Page buffers PB1 to PBm temporarily store the data to be programmed during programming operations and adjust the potential levels of bit lines BL1 to BLm based on the temporarily stored data. For example, the bit lines to be programmed are controlled at a programming enable voltage level, while the bit lines not to be programmed are controlled at a programming disable voltage level.

[0088] In S810, control logic 130 controls peripheral circuitry 120 to apply a programming voltage to the selected page of the selected memory block. For example, voltage generation circuitry 121 generates a programming voltage VP3 and a pass voltage Vpass in response to the operation signal OP_CMD. Line decoder 122 applies the programming voltage VP3 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK3) and the pass voltage Vpass to the remaining unselected word lines (e.g., WL2 to WLn). Therefore, charge is trapped in the charge storage layer of the memory cell MC1 within the selected page, where the corresponding bit line is controlled to a programming-enabled voltage level.

[0089] In S820, control logic 130 controls peripheral circuitry 120 to perform a hold-up acceleration operation on the selected pages of the selected memory block using a channel boost operation. The implementation is described below.

[0090] In S821, during the hold-up acceleration operation, the line decoder 122 turns off the drain select transistor DST and source select transistor SST of the selected memory block BLK3 by applying a cutoff voltage to the drain select line DSL and the source select line SSL. Therefore, the channels of the cell strings CS1 to CSm in the selected memory block BLK3 are in a floating state.

[0091] In S822, the voltage generation circuit 121 generates and outputs a first setting voltage V1 to be applied to the unselected word lines WL2 to WLn and a second setting voltage V2 to be applied to the selected word lines WL1. The line decoder 122 applies the first setting voltage V1 to the unselected word lines WL2 to WLn of the selected memory block BLK3. Therefore, as a coupling phenomenon based on the high potential of the first setting voltage V1 applied to the unselected word lines WL2 to WLn, an increase in the potential level of the channels of the cell strings CS1 to CSm in the selected memory block BLK3 may occur.

[0092] The channel potential of cell strings CS1 to CSm in the selected memory block BLK3 is increased by applying a positive set voltage Vposi to the source line SL. For example, the channel potential of cell strings CS1 to CSm in the selected memory block BLK3 is increased by turning on the source selection transistor SST of the selected memory block BLK3. In one embodiment, for example, the channel potential of cell strings CS1 to CSm can be increased by applying a voltage of 0V to the gate of the source selection transistor SST of the selected memory block BLK3 using a gate-induced drain leakage (GIDL) method.

[0093] In S823, a second setting voltage V2 is applied to the selected word line WL1 corresponding to the selected page of the selected memory block BLK3. Therefore, the charge trapped in the memory cell MC1 in the selected page in an unstable state can be decapsulated by the channel potential boosted by the channel voltage and the second setting voltage V2 applied to the word line WL1.

[0094] In S830, control logic 130 controls peripheral circuitry 120 to perform a programming verification operation on the selected pages of the selected memory block. For example, voltage generation circuitry 121 generates a verification voltage VR2 and a pass voltage Vpass in response to the operation signal OP_CMD. Row decoder 122 applies the verification voltage VR2 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK3) and the pass voltage Vpass to the remaining unselected word lines (e.g., WL2 to WLn). Page buffers PB1 to PBm sense the voltage or current of bit lines BL1 to BLm to perform a verification operation corresponding to the second programming state P2.

[0095] Subsequently, voltage generation circuit 121 generates verification voltage VR3 and pass voltage Vpass in response to operation signal OP_CMD, and line decoder 122 applies verification voltage VR3 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK3) and pass voltage to the remaining unselected word lines (e.g., WL2 to WLn). Page buffers PB1 to PBm sense the voltage or current of bit lines BL1 to BLm to perform the verification operation corresponding to the third programming state P3.

[0096] Subsequently, voltage generation circuit 121 generates verification voltage VR4 and pass voltage Vpass, and line decoder 122 applies verification voltage VR4 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK3) and pass voltage Vpass to the remaining unselected word lines (e.g., WL2 to WLn). Page buffers PB1 to PBm sense the voltage or current of bit lines BL1 to BLm to perform the verification operation corresponding to the fourth programming state P4.

[0097] In the above embodiments, the following example is described: where, when it is determined to be successful based on the programming verification operation in a previous programming cycle, a hold-up acceleration operation is performed after the programming voltage application operation is performed in the current programming cycle. However, in one embodiment, the hold-up acceleration operation can be performed after the programming verification operation in a previous programming cycle is completed, before the programming voltage application operation is performed in the current programming cycle, or after the programming verification operation is performed in the current programming cycle. For example, after it is determined to be successful based on the programming verification operation in the current programming cycle, the hold-up acceleration operation can be performed immediately after the programming verification operation in the current programming cycle or in the next programming cycle.

[0098] In the programming verification operation performed after the hold-up acceleration operation, the verification voltage can be reduced and applied. Since the threshold voltage of a memory cell that has passed programming may be reduced by the hold-up acceleration operation, the threshold voltage distribution of the memory cell can be further improved by reducing the reduced threshold voltage by the verification voltage during the next programming verification operation.

[0099] The above description illustrates an example of performing a hold-and-accelerate operation when the programming verification operation for the first programming state P1 is determined to be passed. In other embodiments, when the programming verification operation for each of the second programming states P2 to the sixth programming states P6 is determined to be passed, the hold-and-accelerate operation may be performed in the current programming cycle or the next programming cycle.

[0100] Figure 11 This is a block diagram illustrating an embodiment of a memory system 1000 including a semiconductor memory device according to any embodiment of this document.

[0101] Reference Figure 11 The memory system 1000 includes a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be, for example, referenced... Figure 1 The semiconductor memory device described.

[0102] Controller 1100 is connected to a host computer and semiconductor memory device 100. Controller 1100 is configured to access semiconductor memory device 100 in response to a request from the host computer. For example, controller 1100 is configured to control read operations, write operations, erase operations, and background operations of semiconductor memory device 100. Controller 1100 is configured to serve as an interface between semiconductor memory device 100 and the host computer. Controller 1100 is configured to drive instructions (e.g., firmware) for controlling semiconductor memory device 100.

[0103] The controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: operating memory of the processing unit 1120, cache memory between the semiconductor memory device 100 and the host, and buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the controller 1100. Furthermore, the controller 1100 can temporarily store programming data provided from the host during programming operations.

[0104] Host interface 1130 includes protocols for performing data exchange between the host and controller 1100. As an exemplary implementation, controller 1100 is configured to communicate with the host via at least one of various interface protocols. Examples include Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0105] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface 1140 includes a NAND interface or a NOR interface.

[0106] Error correction block 1150 is configured to use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. Processing unit 1120 can control semiconductor memory device 100 to adjust read voltage and perform reread based on the error detection results of error correction block 1150. As an exemplary implementation, the error correction block may be a component of controller 1100.

[0107] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As an exemplary embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. Examples of memory cards include: PC cards (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash Cards (CF), Smart Media Cards (SM or SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, or Micro MMC), SD cards (SD, Mini SD, Micro SD, or SDHC), and Universal Flash Memory (UFS).

[0108] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 can be greatly improved.

[0109] In one example, the memory system 1000 is configured as one of various components of an electronic device. Examples of electronic devices include: computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, web tablets, cordless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, and digital video players; devices capable of transmitting and receiving information in a wireless environment; one of various electronic devices for configuring a home network; one of various electronic devices for configuring a computer network; one of various electronic devices for configuring a telematics network; RFID devices; and one of various components for configuring a computing system.

[0110] As an exemplary embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted as various types of packages. Examples include: PoP (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Wafer in-package, Wafer Form-on-Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Scale Fabrication Package (WFP), and Wafer-Scale Fabrication Stacked Package (WSP).

[0111] Figure 12 This is an example Figure 11 A block diagram illustrating an application example of the memory system 2000.

[0112] Reference Figure 12 The memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips that can be divided into multiple groups.

[0113] exist Figure 12 In this process, multiple groups communicate with the controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip communicates with a reference... Figure 1 The semiconductor memory device 100 described is similarly configured and operated.

[0114] Each group is configured to communicate with controller 2200 via a common channel. Controller 2200 can communicate with reference to... Figure 11The controller 1100 described is similarly configured and can be configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0115] Figure 13 Examples include, for example, being. Figure 12 Block diagram of the memory system of the computing system 3000.

[0116] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000. The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0117] exist Figure 13 In this embodiment, the semiconductor memory device 2100 is connected to the system bus 3500 via the controller 2200. However, in another embodiment, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500. In this case, the operation of the controller 2200 may be controlled or executed by the central processing unit 3100 and the RAM 3200.

[0118] exist Figure 13 In the middle, refer to Figure 12 The memory system 2000 is described. However, in one embodiment, reference 2000 may be used. Figure 11 The memory system 1000 described herein replaces the memory system 2000. In an exemplary embodiment, the computing system 3000 may be configured to include reference... Figure 11 The described memory system 1000 and reference Figure 12 The memory system described in 2000 is both.

[0119] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0120] When at least partially implemented in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, determiners, drivers, blocks, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method implementation can transform a computer processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0121] The embodiments of this disclosure disclosed in this specification and accompanying drawings are merely specific examples used to readily describe the technical content of this disclosure and to facilitate understanding of this disclosure, and do not limit the scope of protection of this disclosure. It will be apparent to those skilled in the art that other modifications based on the technical spirit of this disclosure can be implemented in addition to the embodiments disclosed herein.

[0122] Cross-reference to related applications

[0123] This application claims priority to Korean Patent Application No. 10-2020-0186196, filed with the Korean Intellectual Property Office on December 29, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array, the memory cell array comprising multiple memory blocks; Peripheral circuitry, which performs programming operations including multiple programming loops on a selected memory block among the plurality of memory blocks; as well as Control logic, the control logic being: Based on the results of the programming verification operations in the previous programming loop, determine whether to perform a preservative acceleration operation on the current programming loop, and The peripheral circuitry is controlled to perform the hold-accelerate operation, which includes boosting the channels of multiple cell strings in the selected memory block, between the programming voltage application operation and the programming verification operation of the current programming cycle.

2. The semiconductor memory device according to claim 1, wherein, The peripheral circuit includes: A voltage generation circuit generates a first setting voltage to be applied to the unselected word line of the selected memory block and a second setting voltage to be applied to the selected word line of the selected memory block during the hold-acceleration operation. A row decoder applies a first setting voltage and a second setting voltage to the unselected word line and the selected word line of the selected memory block, respectively; and Page buffer group, which controls the potential of the bit line of the selected memory block or senses the potential or current of the bit line.

3. The semiconductor memory device according to claim 2, wherein, The row decoder applies a cutoff voltage to the source select line and drain select line of the selected memory block during the hold-up acceleration operation.

4. The semiconductor memory device according to claim 3, wherein, The row decoder controls the channels of the plurality of cell strings in the selected memory block to have a floating state during the hold-acceleration operation.

5. The semiconductor memory device according to claim 4, wherein, The channels of the plurality of unit strings are boosted by the first set voltage, and The first set voltage is higher than the second set voltage.

6. The semiconductor memory device according to claim 1, wherein, The control logic controls the peripheral circuitry to perform the hold-acceleration operation immediately after the programming voltage application operation is executed.

7. The semiconductor memory device according to claim 1, wherein, The control logic: Control is used to perform the programming voltage application operation and the programming verification operation on the selected memory block during the programming operation, and The peripheral circuitry is controlled to perform the hold-acceleration operation based on the result of the programming verification operation of the previous programming cycle to ensure that the programming passes.

8. A semiconductor memory device, the semiconductor memory device comprising: A storage block, the storage block comprising memory cells programmed into multiple programming states; Peripheral circuitry that performs programming operations, including multiple programming loops, on the memory block; as well as Control logic controls the peripheral circuitry to execute the plurality of programming loops, wherein the control logic controls the peripheral circuitry to perform a hold-up acceleration operation during the current programming loop based on the result of a programming verification operation of a previous programming loop among the plurality of programming loops to ensure programming is passed.

9. The semiconductor memory device according to claim 8, wherein, Each of the plurality of programming loops includes a programming voltage application operation and a programming verification operation.

10. The semiconductor memory device according to claim 9, wherein, The peripheral circuit includes: A voltage generation circuit generates a first setting voltage to be applied to the unselected word lines of the memory block and a second setting voltage to be applied to the selected word lines of the memory block during the hold-acceleration operation. A row decoder applies a first setting voltage and a second setting voltage to the unselected word line and the selected word line of the memory block, respectively; and Page buffer group, which controls the potential of the bit lines of the memory block, or senses the potential or current of the bit lines.

11. The semiconductor memory device of claim 10, wherein, The row decoder applies a cutoff voltage to the source select line and drain select line of the memory block during the hold-up acceleration operation.

12. The semiconductor memory device according to claim 11, wherein, The row decoder controls the channels of multiple cell strings in the memory block to have a floating state during the hold-acceleration operation.

13. The semiconductor memory device according to claim 12, wherein, The channels of the plurality of unit strings are boosted by the first set voltage, and The first set voltage is higher than the second set voltage.

14. The semiconductor memory device according to claim 9, wherein, The control logic controls the peripheral circuitry to perform the hold-acceleration operation either before or immediately after the programming voltage application operation of the current programming cycle.

15. The semiconductor memory device according to claim 9, wherein, The control logic controls the peripheral circuitry to perform the programming verification operation performed after the hold-up acceleration operation using a new verification voltage that is lower than the verification voltage used in the previous programming verification operation.

16. A method of operating a semiconductor memory device, the method comprising the steps of: A programming voltage application operation is performed to apply a programming voltage to a selected word line among multiple word lines connected to a cell string, the cell string comprising multiple memory cells programmed into multiple programming states; Perform a programming verification operation on the memory cell connected to the selected word line; as well as The result of the programming verification operation is that the programming is successful, and the holding acceleration operation is performed by boosting the channel of the cell string.

17. The method of claim 16, further comprising the step of: Before performing the hold-up acceleration operation, a next programming voltage application operation is performed, which includes applying a new programming voltage to the selected word line.

18. The method according to claim 16, wherein, The steps for performing the sustained acceleration operation include the following: Turn off the source selection transistor and drain selection transistor of the cell string; The channel of the cell string is boosted by applying a first setting voltage to the unselected word lines among the plurality of word lines connected to the cell string; and A second setting voltage lower than the first setting voltage is applied to the selected word line.

19. The method according to claim 18, wherein, The second set voltage is 0V.

20. The method of claim 16, wherein the method comprises the following steps: If the programming verification operation results in a programming failure, another programming voltage application operation is performed using a new programming voltage obtained by increasing the programming voltage.

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