Stacked body, method for manufacturing the same, and semiconductor device
By using magnesium oxide and zinc oxide electrode layers in deep ultraviolet light-emitting diodes, combined with metal oxide buffer layers of Ga, Al, In and Zn, the problem of poor transmittance of ITO electrodes is solved, achieving high efficiency in ultraviolet transmission and conductivity, and improving luminous efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- IDEMITSU KOSAN CO LTD
- Filing Date
- 2020-11-02
- Publication Date
- 2026-06-12
AI Technical Summary
In existing deep ultraviolet light-emitting diodes, the ITO electrode has poor ultraviolet transmittance, making it impossible to balance ultraviolet transmittance and conductivity, resulting in poor luminous efficiency.
An electrode layer containing magnesium oxide and zinc oxide is formed by combining a buffer layer with metal oxides of Ga, Al, In and Zn, and by controlling the molar ratio and heat treatment, an electrode layer with excellent ultraviolet transmittance and conductivity is formed.
It achieves high luminous efficiency in the ultraviolet region, and the electrode layer has good ultraviolet transmittance and conductivity, making it suitable for deep ultraviolet light-emitting semiconductor devices.
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Figure CN114730819B_ABST
Abstract
Claims
1. A laminate, comprising sequentially a support, a buffer layer, and an electrode layer. The buffer layer contains one or more metals selected from Ga, Al, In, and Zn, and oxygen. The buffer layer contains zinc oxide. The molar ratio of Ga to the total of Ga and Zn in the buffer layer [Ga / (Ga+Zn)] is greater than 0.000 and less than 0.
2. The electrode layer comprises magnesium oxide and zinc oxide. In the X-ray diffraction measurement of the electrode layer, the half-width of the diffraction peak observed at 2θ = 34.8 ± 0.5 deg was less than 0.43 deg.
2. The laminated body according to claim 1, wherein, In the X-ray diffraction measurement of the electrode layer, the half-width of the diffraction peak observed at 2θ = 34.8 ± 0.5 deg was greater than 0.001 deg.
3. The laminate according to claim 1 or 2, wherein, The half-width of the diffraction peak is a value determined using an XRD evaluation device under the following conditions. X-ray diffraction measurement conditions: X-rays: Cu-Kα rays, wavelength 1.5406 Å, monochromated using a graphite monochromator. Output: 40kV-40mA 2θ-θ reflectance method, continuous scanning at 1.0 deg / min, measurement range 20 deg to 70 deg Sampling interval: 0.02deg Slit DS, SS: 2 / 3deg, RS: 0.6mm.
4. The laminate according to claim 1 or 2, wherein, The electrode layer and the buffer layer are in direct contact and stacked together.
5. The laminate according to claim 1 or 2, wherein, The conductivity of the stacked unit composed of the electrode layer and the buffer layer is greater than or equal to 0.01 S / cm and less than 10,000 S / cm.
6. The laminate according to claim 1 or 2, wherein, The conductivity of the stacked unit composed of the electrode layer and the buffer layer is 0.5 S / cm or higher.
7. The laminate according to claim 5, wherein, The conductivity of the stacked unit consisting of the electrode layer and the buffer layer is a value measured at 25°C using a resistivity / hole measurement system.
8. The laminate according to claim 1 or 2, wherein, The resistivity of the stacked unit composed of the electrode layer and the buffer layer is above 0.0317 Ωcm and below 0.381 Ωcm.
9. The laminate according to claim 8, wherein, The resistivity of the stacked unit consisting of the electrode layer and the buffer layer is a value measured at 25°C using a resistivity / hole measurement system.
10. The laminate according to claim 1 or 2, wherein, The mobility of the electrode layer is 10 cm. 2 / Vs or above and 28.2cm 2 / Vs and below.
11. The laminate according to claim 1 or 2, wherein, The carrier concentration of the electrode layer is 4.20 × 10⁻⁶. 18 cm 3 Above and 1.79×10 19 cm 3 the following.
12. The laminate according to claim 1 or 2, wherein, The mobility of the electrode layer is 10 cm. 2 / Vs or above and 28.2cm 2 Below / Vs, the carrier concentration of the electrode layer is 4.20×10 18 cm 3 Above and 1.79×10 19 cm 3 the following.
13. The laminate according to claim 10, wherein, The mobility of the electrode layer was measured at 23°C using a resistivity / hole measurement system.
14. The laminate according to claim 11, wherein, The carrier concentration of the electrode layer was measured at 23°C using a resistivity / hole measurement system.
15. The laminate according to claim 1 or 2, wherein, The molar ratio of Mg to the total of Mg and Zn in the electrode layer [Mg / (Mg+Zn)] is 0.25 or more and 0.75 or less.
16. The laminate according to claim 15, wherein, The molar ratio [Mg / (Mg+Zn)] in the electrode layer was determined by secondary ion mass spectrometry.
17. The laminate according to claim 1 or 2, wherein, In the electrode layer, the regions dominated by zinc oxide and the regions dominated by magnesium oxide each exist in a dispersed state.
18. The laminate according to claim 1 or 2, wherein, The electrode layer contains a solid solution of magnesium and zinc, MgZnOx.
19. The laminate according to claim 1 or 2, wherein, The electrode layer essentially comprises magnesium oxide and zinc oxide.
20. The laminate according to claim 1 or 2, wherein, The electrode layer is composed of more than 90% by mass of magnesium oxide and zinc oxide.
21. The laminate according to claim 1 or 2, wherein, The electrode layer consists only of magnesium oxide and zinc oxide.
22. The laminate according to claim 21, wherein, The electrode layer further contains unavoidable impurities.
23. The laminate according to claim 1 or 2, wherein, The electrode layer further comprises trivalent or tetravalent elements X, in addition to Mg and Zn.
24. The laminate according to claim 23, wherein, Element X is selected from one or more of B, Al, Ga, In, Tl, C, Si, Ge, Sn, and Pb.
25. The laminate according to claim 23, wherein, The molar ratio of element X to all metal elements in the electrode layer [element X / all metal elements] is greater than 0.0001 and less than 0.
20.
26. The laminate according to claim 25, wherein, The molar ratio [element X / total metal elements] in the electrode layer is a value determined by secondary ion mass spectrometry.
27. The laminate according to claim 23, wherein, The electrode layer essentially comprises magnesium oxide, zinc oxide, and oxides of element X.
28. The laminate according to claim 23, wherein, The electrode layer is composed of over 90% by mass of magnesium oxide, zinc oxide, and oxides of element X.
29. The laminate according to claim 23, wherein, The electrode layer consists only of magnesium oxide, zinc oxide, and oxides of element X.
30. The laminate according to claim 29, wherein, The electrode layer further contains unavoidable impurities.
31. The laminate according to claim 1 or 2, wherein, The transmittance of light with a wavelength of 260 nm in the stacked unit composed of the electrode layer and the buffer layer is greater than 4%.
32. The laminate according to claim 1 or 2, wherein, The transmittance of light with a wavelength of 260 nm in the stacked unit composed of the electrode layer and the buffer layer is less than 80%.
33. The laminate according to claim 31, wherein, The transmittance of light at a wavelength of 260 nm for the stacked unit consisting of the electrode layer and the buffer layer is a value evaluated using a spectrophotometer at 25°C.
34. The laminate according to claim 1 or 2, wherein, The c-axis orientation of the electrode layer is above 40%.
35. The laminate according to claim 1 or 2, wherein, The c-axis orientation of the electrode layer is less than 100%.
36. The laminate according to claim 34, wherein, The c-axis orientation of the electrode layer is a value calculated using XRD evaluation equipment based on the diffraction intensity measured under the following conditions, by equations (1) and (2). X-ray diffraction measurement conditions: X-rays: Cu-Kα rays, wavelength 1.5406 Å, monochromated using a graphite monochromator. Output: 40kV-40mA 2θ-θ reflectance method, continuous scanning at 1.0 deg / min, measurement range 20 deg to 70 deg Sampling interval: 0.02deg Slit DS, SS: 2 / 3deg, RS: 0.6mm; Formula for calculating c-axis orientation: c-axis orientation (%) = {(P-P0) / (1-P0)} × 100 P0=I0(0002) / ΣI0(hkil)…(1) P=I S (0002) / ΣI S (hkil) …(2) In the aforementioned equation (1), I0 (0002) represents the diffraction intensity of the peak appearing at 2θ = 34.8 ± 0.5 deg in PowderDiffraction File card number 01-075-0576 of the International Centre for Diffraction Data. I S (0002) represents the diffraction intensity of the peak appearing in the electrode layer at 2θ = 34.8 ± 0.5 deg. ΣI0 (hkil) represents the integral value of the diffraction intensity in the range of 2θ = 30deg to 60deg for PowderDiffraction File card number 01-075-0576 from the International Centre for Diffraction Data. ΣI S (hkil) represents the integral value of the diffraction intensity of the electrode layer in the range of 2θ = 30deg to 60deg.
37. The laminate according to claim 1 or 2, wherein, The electrode layer is an amorphous layer, a polycrystalline layer, or a layer in which amorphous and crystalline components coexist.
38. The laminate according to claim 37, wherein, The crystallization state of the electrode layer is determined by observing the lattice image of the cross-section in the thickness direction of the electrode layer using a transmission electron microscope.
39. The laminate according to claim 1 or 2, wherein, The electrode layer comprises hexagonal ZnO with the c-axis oriented along the thickness direction of the electrode layer.
40. The laminate according to claim 1 or 2, wherein, The electrode layer comprises hexagonal ZnO with the c-axis oriented along the thickness direction of the electrode layer, and Mg is dissolved in the ZnO.
41. The laminate according to claim 1 or 2, wherein, The thickness of the electrode layer is 1 nm to 10 μm.
42. The laminate according to claim 41, wherein, The thickness of the electrode layer is a value confirmed by scanning electron microscopy or transmission electron microscopy.
43. The laminate according to claim 1 or 2, wherein, The buffer layer further comprises gallium oxide.
44. The laminate according to claim 1 or 2, wherein, The molar ratio of Ga to the total of Ga and Zn in the buffer layer [Ga / (Ga+Zn)] is greater than 0.001 and less than 0.
2.
45. The laminate according to claim 44, wherein, The molar ratio [Ga / (Ga+Zn)] in the buffer layer is a value determined by secondary ion mass spectrometry.
46. The laminate according to claim 1 or 2, wherein, The buffer layer comprises a gallium-zinc solid solution GaZnOx.
47. The laminate according to claim 1 or 2, wherein, The buffer layer essentially contains one or more metals selected from Ga, Al, In, and Zn, and oxygen.
48. The laminate according to claim 1 or 2, wherein, The buffer layer comprises more than 90% by mass of one or more metals and oxygen selected from Ga, Al, In and Zn.
49. The laminate according to claim 1 or 2, wherein, The buffer layer consists of only one or more metals selected from Ga, Al, In and Zn and oxygen.
50. The laminate according to claim 49, wherein, The buffer layer further contains unavoidable impurities.
51. The laminate according to claim 1 or 2, wherein, The buffer layer further contains trivalent or tetravalent element Z in addition to Ga, Al, In and Zn.
52. The laminate according to claim 51, wherein, Element Z is selected from one or more of B, Tl, C, Si, Ge, Sn, and Pb.
53. The laminate according to claim 51, wherein, The molar ratio of element Z to all metal elements in the buffer layer [element Z / all metal elements] is greater than 0.0001 and less than 0.
20.
54. The laminate according to claim 53, wherein, The molar ratio [element Z / total metal elements] in the buffer layer is a value determined by secondary ion mass spectrometry.
55. The laminate according to claim 51, wherein, The buffer layer essentially contains one or more metals selected from Ga, Al, In, and Zn, oxygen, and element Z.
56. The laminate according to claim 51, wherein, The buffer layer comprises more than 90% by mass of one or more metals, oxygen, and element Z selected from Ga, Al, In, and Zn.
57. The laminate according to claim 51, wherein, The buffer layer consists of only one or more metals selected from Ga, Al, In and Zn, oxygen and element Z.
58. The laminate according to claim 57, wherein, The buffer layer further contains unavoidable impurities.
59. The laminate according to claim 1 or 2, wherein, The thickness of the buffer layer is greater than 1 nm and less than 100 nm.
60. The laminate according to claim 59, wherein, The thickness of the buffer layer is a value confirmed by scanning electron microscopy or transmission electron microscopy.
61. The laminate according to claim 1 or 2, wherein, The support includes an ultraviolet-transmitting component.
62. The laminate according to claim 61, wherein, The ultraviolet-transmitting component comprises glass, quartz, or resin.
63. The laminate according to claim 1 or 2, wherein, The support includes a semiconductor layer.
64. The laminate according to claim 63, wherein, The semiconductor layer comprises a group III-V nitride semiconductor.
65. The laminate according to claim 63, wherein, The semiconductor layer comprises one or more selected from GaN, InGaN, AlGaN, AlInGaN, AlN, InN, and BN.
66. The laminate according to claim 63, wherein, The semiconductor layer comprises AlN, GaN, InN, or a mixture thereof.
67. The laminate according to claim 63, wherein, The semiconductor layer is an n-type semiconductor.
68. The laminate according to claim 63, wherein, The semiconductor layer is a p-type semiconductor.
69. The laminate according to claim 67, wherein, The semiconductor layer contains Si as an n-type dopant.
70. The laminate according to claim 68, wherein, The semiconductor layer contains Mg as a p-type dopant.
71. The laminate according to claim 63, wherein, The semiconductor layer and the buffer layer are in direct contact and stacked together.
72. The laminate according to claim 63, wherein, The thickness of the semiconductor layer is 10 nm to 2 mm.
73. The laminate according to claim 63, wherein, The support comprises a semiconductor layer and a support substrate, the support substrate further comprising a material different from the semiconductor layer.
74. The laminate according to claim 73, wherein, The semiconductor layer is formed by epitaxial growth on the supporting substrate.
75. The laminate according to claim 73 or 74, wherein, The supporting substrate is GaN, InGaN, AlGaN, AlN, InN, SiC, Si, or sapphire.
76. The laminate according to claim 73 or 74, wherein, The support includes a semiconductor layer on the buffer layer side and the support substrate on the side opposite to the buffer layer when viewed from the semiconductor layer.
77. The laminate according to claim 63, wherein, In addition to the semiconductor layer, the support also includes an ultraviolet light-emitting layer.
78. The laminate according to claim 77, wherein, The semiconductor layer is disposed between the ultraviolet emitting layer and the buffer layer.
79. The laminate according to claim 1 or 2, further comprising a wiring layer in contact with a portion of the electrode layer.
80. The laminate according to claim 79, wherein, The laminate has a semiconductor layer. The wiring layer is formed on the surface opposite to the side of the electrode layer that is in contact with the semiconductor layer.
81. The laminate according to claim 79, wherein, The wiring layer is formed of a material having higher conductivity than the electrode layer.
82. The laminate according to claim 79, wherein, The wiring layer comprises: one or more metals or alloys thereof selected from Ni, Pd, Pt, Rh, Zn, In, Sn, Ag, Au, Mo, Ti, Cu and Al, and one or more metals selected from ITO, SnO2, ZnO, In2O3, Ga2O3, RhO2, NiO, CoO, PdO, PtO, CuAlO2, CuGaO2, TiN, TaN, SiNx and poly-Si.
83. The laminate according to claim 79, wherein, The wiring layer is a transparent conductive oxide or a transparent conductive nitride.
84. The laminate according to claim 79, wherein, The wiring layer is a stack having a Ni layer stacked on the side connected to the electrode layer and an Au layer stacked on the Ni layer.
85. The laminate according to claim 79, wherein, The wiring layer is linear or grid-like.
86. The laminate according to claim 79, wherein, The thickness of the aforementioned wiring layer is 10 nm to 10 μm.
87. A laminated body having: substrate, n-type GaN semiconductor layer stacked on the substrate A portion of the first electrode layer stacked on the n-type GaN semiconductor layer, In the region of the n-type GaN semiconductor layer, an ultraviolet emitting layer is stacked at a location other than the location where the first electrode layer is stacked and its surrounding area. p-type GaN semiconductor layer stacked on the ultraviolet light-emitting layer The buffer layer and the layer stacked on the p-type GaN semiconductor layer A second electrode layer is stacked on the buffer layer; The buffer layer contains one or more metals selected from Ga, Al, In, and Zn, and oxygen. The buffer layer contains zinc oxide. The molar ratio of Ga to the total of Ga and Zn in the buffer layer [Ga / (Ga+Zn)] is greater than 0.000 and less than 0.
2. The second electrode layer comprises magnesium oxide and zinc oxide. In the X-ray diffraction measurement of the second electrode layer, the half-width of the diffraction peak observed at 2θ = 34.8 ± 0.5 deg was less than 0.43 deg.
88. The laminate according to claim 87, wherein, A wiring layer is stacked on the second electrode layer.
89. The laminate according to claim 87 or 88, further comprising a buffer layer adjacent to the first electrode layer.
90. A laminated body having: First electrode layer The substrate stacked on the first electrode layer, n-type GaN semiconductor layer stacked on the substrate The ultraviolet-emitting layer stacked on the n-type GaN semiconductor layer, p-type GaN semiconductor layer stacked on the ultraviolet light-emitting layer The buffer layer and the layer stacked on the p-type GaN semiconductor layer A second electrode layer is stacked on the buffer layer; The buffer layer contains one or more metals selected from Ga, Al, In, and Zn, and oxygen. The buffer layer contains zinc oxide. The molar ratio of Ga to the total of Ga and Zn in the buffer layer [Ga / (Ga+Zn)] is greater than 0.000 and less than 0.
2. The second electrode layer comprises magnesium oxide and zinc oxide. In the X-ray diffraction measurement of the second electrode layer, the half-width of the diffraction peak observed at 2θ = 34.8 ± 0.5 deg was less than 0.43 deg.
91. The laminate according to claim 90, wherein, A wiring layer is stacked on the second electrode layer.
92. The laminate according to claim 90 or 91, further comprising a buffer layer adjacent to the first electrode layer.
93. A laminated body, which has: substrate, The first electrode layer stacked on the substrate, An n-type GaN semiconductor layer is stacked on the first electrode layer. The ultraviolet-emitting layer stacked on the n-type GaN semiconductor layer, p-type GaN semiconductor layer stacked on the ultraviolet light-emitting layer The buffer layer and the layer stacked on the p-type GaN semiconductor layer A second electrode layer is stacked on the buffer layer; The buffer layer contains one or more metals selected from Ga, Al, In, and Zn, and oxygen. The buffer layer contains zinc oxide. The molar ratio of Ga to the total of Ga and Zn in the buffer layer [Ga / (Ga+Zn)] is greater than 0.000 and less than 0.
2. The second electrode layer comprises magnesium oxide and zinc oxide. In the X-ray diffraction measurement of the second electrode layer, the half-width of the diffraction peak observed at 2θ = 34.8 ± 0.5 deg was less than 0.43 deg.
94. The laminate according to claim 93, wherein, A wiring layer is stacked on the second electrode layer.
95. The laminate according to claim 93 or 94, further comprising a buffer layer adjacent to the first electrode layer.
96. A semiconductor device comprising a stack according to any one of claims 1 to 95.
97. The semiconductor device of claim 96, wherein it is a semiconductor device using gallium nitride semiconductor and is a short-wavelength light-emitting diode emitting visible light and / or ultraviolet light.
98. The semiconductor device of claim 96, wherein it is a semiconductor device using gallium nitride semiconductor and is a short-wavelength light-emitting laser diode emitting visible light and / or ultraviolet light.
99. The semiconductor device according to claim 96, wherein it is a deep ultraviolet light-emitting semiconductor device that emits ultraviolet light in the wavelength region below 260 nm.
100. A method for manufacturing a laminate, comprising the method for manufacturing the laminate according to any one of claims 1 to 86, comprising: The steps of forming the buffer layer on the support, and The step of forming the electrode layer on the buffer layer.
101. The method of manufacturing a laminate according to claim 100, comprising the step of heat-treating the electrode layer formed on the buffer layer.
102. The method for manufacturing a laminate according to claim 101, wherein, The heat treatment temperature is above 750℃ and below 1200℃.
103. The method for manufacturing a laminate according to any one of claims 100 to 102, wherein, The buffer layer is formed on the support containing the semiconductor layer.
104. The method for manufacturing a laminate according to any one of claims 100 to 102, wherein, The buffer layer is formed on the support containing the ultraviolet-transmitting component.
105. The method for manufacturing a laminate according to claim 104, wherein, A semiconductor layer is further formed on the electrode layer.
106. The method for manufacturing a laminate according to any one of claims 100 to 102, wherein, The buffer layer or the electrode layer is formed by resistance wire heating evaporation, electron beam evaporation, sputtering, atomic layer deposition, thermochemical vapor deposition, parallel plate plasma CVD, magnetic field microwave plasma CVD, or inductively coupled plasma CVD, spin coating, or ion plating.
107. The method for manufacturing a laminate according to claim 106, wherein, The buffer layer and the electrode layer are formed by sputtering or ion plating using at least one of O2, Ar and N2 as the sputtering gas.