A programmable frequency divider, a frequency divider programming method and a frequency synthesizer device

Abstract

The embodiment of the application discloses a programmable frequency divider, a frequency divider programming method and a frequency synthesizer device, the programmable frequency divider comprises N CD trigger units, a carry unit corresponding to N-1 trigger units and a frequency division signal output unit; the control signal end of each trigger unit is used for accessing the corresponding control signal; the input end of the carry unit corresponding to the trigger unit of the i-th order is connected with the state signal end of each trigger unit before the i-th order; the output end of the carry unit is connected with the carry signal end of the trigger unit of the previous order; the frequency division signal output unit determines a target frequency division ratio according to a preset rule and the control signals of all the trigger units; and the frequency division signal output unit is used for outputting a target clock signal corresponding to the target frequency division ratio. Through the programmable frequency divider of the embodiment of the application, the full-range programmable continuous frequency division function can be realized, and the multiplicity is good.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits and semiconductors, and in particular to a programmable frequency divider, a frequency divider programming method, and a frequency synthesizer device. Background Technology

[0002] In frequency synthesizers based on phase-locked loops (PLLs), the frequency divider is a crucial module. It is key to the frequency synthesizer's ability to provide multiple high-precision frequency signals while simultaneously achieving high-frequency, low-power operation. During communication, the division ratio of the frequency divider needs to be changed to switch between channels, making the design and implementation of the frequency divider highly significant and valuable in practice.

[0003] Traditional programmable frequency divider structures, such as Figure 1 As shown, the structure consists of three parts: a dual-mode prescaler, a pulse counter, and a swallowing counter. The structure is relatively complex. The division ratio of the prescaler is PN+S (P>S), where N is a fixed value. The pulse count value P and the swallowing count value S are programmable. Typically, the dual-mode prescaler is a 2 / 3, 4 / 5, or 8 / 9 prescaler, and it is necessary to control P>S. Therefore, traditional programmable prescalers can only achieve programmable division within the target range. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide a programmable frequency divider, an apparatus, an electronic device, and a computer-readable storage medium, with the specific solutions as follows:

[0005] In a first aspect, embodiments of this application provide a programmable frequency divider, which includes N CD trigger units, a carry unit corresponding to N-1 CD trigger units, and a frequency division signal output unit, wherein the N CD trigger units are connected in a preset order;

[0006] The control signal terminal of each CD trigger unit is used to connect to the corresponding frequency division control signal;

[0007] The carry signal terminal of the i-th CD trigger unit is connected to the output terminal of the (i-1)-th carry unit.

[0008] The input terminal of the carry unit in the (i-1)th order is connected to the status signal terminal of each CD trigger unit before the i-th order, where 1 <i≤N;

[0009] The carry signal terminal of the first CD trigger unit is grounded;

[0010] The control terminal of the frequency division signal output unit is used to receive the frequency division control signal, the first input terminal of the frequency division signal output unit is used to receive the preset standard clock signal, and the second input terminal of the frequency division signal output unit is connected to the status signal terminal of each CD trigger unit.

[0011] The frequency division signal output unit outputs a target clock signal corresponding to the target frequency division ratio according to the frequency division control signal.

[0012] According to a specific embodiment of this application, the CD triggering unit includes a D flip-flop, a first selector, and an XNOR gate, wherein,

[0013] The clock signal terminal of the D flip-flop is used to connect to a preset standard clock signal;

[0014] The state signal terminal of the D flip-flop is connected to the first input terminal of the XOR gate, and the second input terminal of the XOR gate is used to connect the output signal of the corresponding carry unit.

[0015] The output of the XOR gate is connected to the first input of the first selector, the second input of the first selector is used to receive the corresponding frequency division control signal, and the control terminal of the first selector is used to receive the preset selection signal.

[0016] The output of the first selector is connected to the control terminal of the D flip-flop;

[0017] The first selector is used to determine whether to receive a signal through the first input terminal or the second input terminal based on the selection signal.

[0018] According to a specific embodiment of this application, when the signal received by the control terminal of the first selector is a first selection signal, the first selector receives the signal through the first input terminal.

[0019] When the signal received by the control terminal of the first selector is the second selection signal, the first selector receives the signal through the second input terminal.

[0020] According to a specific embodiment of this application, the first carry unit is an inverter, and the j-th carry unit is a NAND gate, where 1 <j≤N-1。

[0021] According to a specific embodiment of the present application, the frequency division signal output unit includes a second selector, a NOR gate, and a selection signal circuit;

[0022] The input terminal of the NOR gate is used to receive the frequency division control signal, and the output terminal of the NOR gate is connected to the control terminal of the second selector;

[0023] The first input terminal of the second selector is used to connect to a preset standard clock signal;

[0024] The input terminal of the selection signal circuit is connected to the status signal terminal of each CD trigger unit, and the output terminal of the selection signal circuit is connected to the selection signal terminal of each CD trigger unit and is connected to the second input terminal of the second selector.

[0025] The output of the second selector is used to output a clock signal corresponding to the target division ratio.

[0026] According to a specific embodiment of the present application, the selection signal circuit includes a NAND gate and a first inverter;

[0027] The input terminal of the NAND gate is connected to the status signal terminal of each CD trigger unit;

[0028] The output of the NAND gate is connected to the input of the first inverter.

[0029] The output terminal of the first inverter is connected to the second input terminal of the second selector as the output terminal of the selection signal circuit.

[0030] According to a specific embodiment of this application, the frequency division signal output unit further includes a blocking circuit, the blocking circuit including a preset number of inverters connected in sequence, and the output terminal of the selection signal circuit is connected to the second input terminal of the second selector through the blocking circuit.

[0031] According to a specific embodiment of the present application, the programmable frequency divider further includes a clock unit;

[0032] The output terminal of the clock unit is connected to the clock signal terminal of the programmable frequency divider, and the clock unit is used to output a preset standard clock signal.

[0033] Secondly, embodiments of this application provide a frequency divider programming method, applied to the programmable frequency divider described in the first aspect and any embodiment of the first aspect, the frequency divider programming method comprising:

[0034] Obtain the preset standard clock signal and frequency division control signal;

[0035] The standard clock signal is divided according to the frequency division control signal to obtain a target clock signal with a corresponding target frequency division ratio.

[0036] Thirdly, embodiments of this application provide a frequency synthesizer device, which includes the programmable frequency divider described in the first aspect and any embodiment of the first aspect.

[0037] The embodiments of the present application provide a programmable frequency divider, a method for programming the frequency divider, and a frequency synthesizer device. The programmable frequency divider includes N CD trigger units, carry units corresponding to N - 1 CD trigger units, and a frequency division signal output unit. Among them, the N CD trigger units are connected in a preset order; the control signal terminals of each CD trigger unit are used to access the corresponding frequency division control signal; the carry signal terminal of the CD trigger unit in the i-th order is correspondingly connected to the output terminal of the carry unit in the (i - 1)-th order; the input terminal of the carry unit in the (i - 1)-th order is connected to the state signal terminals of each CD trigger unit before the i-th order, where 1 < i ≤ N; the carry signal terminal of the CD trigger unit in the first order is grounded; the control terminal of the frequency division signal output unit is used to access the frequency division control signal, the first input terminal of the frequency division signal output unit is used to access a preset standard clock signal, and the second input terminal of the frequency division signal output unit is connected to the state signal terminals of each CD trigger unit; the frequency division signal output unit outputs a target clock signal corresponding to a target frequency division ratio according to the frequency division control signal. Through the programmable frequency divider of the embodiments of the present application, a full-range programmable continuous frequency division function can be achieved, and it has a high working speed and good reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the protection scope of the present invention. In each drawing, similar components are numbered similarly.

[0039] Figure 1 FIG. shows a schematic structural diagram of a frequency divider provided by an embodiment of the present application;

[0040] Figure 2 FIG. shows a schematic structural diagram of a programmable frequency divider provided by an embodiment of the present application;

[0041] Figure 3 FIG. shows a schematic structural diagram of a CD flip-flop in a programmable frequency divider provided by an embodiment of the present application;

[0042] Figure 4 FIG. shows a schematic flow chart of a method for programming a frequency divider provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0044] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0045] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0046] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0048] refer to Figure 2 This is a schematic diagram of a programmable frequency divider provided in an embodiment of this application. The programmable frequency divider provided in this embodiment of the application, such as... Figure 2 As shown, the programmable frequency divider includes N CD trigger units, a carry unit corresponding to N-1 CD trigger units, and a frequency division signal output unit, wherein the N CD trigger units are connected in a preset order;

[0049] The control signal terminal of each CD trigger unit is used to connect to the corresponding frequency division control signal;

[0050] The carry signal terminal of the i-th CD trigger unit is connected to the output terminal of the (i-1)-th carry unit.

[0051] The input terminal of the carry unit in the (i-1)th order is connected to the status signal terminal of each CD trigger unit before the i-th order, where 1 <i≤N;

[0052] The carry signal terminal of the first CD trigger unit is grounded;

[0053] The control terminal of the frequency division signal output unit is used to receive the frequency division control signal, the first input terminal of the frequency division signal output unit is used to receive the preset standard clock signal, and the second input terminal of the frequency division signal output unit is connected to the status signal terminal of each CD trigger unit.

[0054] The frequency division signal output unit outputs a target clock signal corresponding to the target frequency division ratio according to the frequency division control signal.

[0055] In a specific implementation, the programmable frequency divider consists of N CD trigger units, N-1 carry units, and a frequency division signal output unit. The N CD trigger units and N-1 carry units are connected correspondingly, and the N CD trigger units are connected in order from the first to the i-th order. <i≤N。

[0056] In this embodiment, N is a positive integer and N≥2.

[0057] For example, the number of CD trigger units can be as follows: Figure 2 The number of CD trigger units can be 2, as shown in the example of 3 or more. This embodiment does not specifically limit the number of CD trigger units.

[0058] In addition, the carry signal terminal of the CD trigger unit in the first sequence is grounded, and there is no corresponding carry unit.

[0059] In this embodiment, the control signal terminal of each CD trigger unit is connected to the signal output terminal of the host computer device to receive the frequency division control signal sent by the host computer device.

[0060] The host computer device can be any terminal device capable of programming. Users can send DIVs to the programmable frequency divider through the host computer device. <k:0>The frequency division control signal, where DIV <k:0>This indicates that the control signal includes k+1 bits, starting from bit 0 and ending at bit k. For example, DIV<2:0> indicates that the control signal includes bits 0, 1, and 2, for a total of 3 bits. Here, k is N-1.

[0061] like Figure 2 As shown, each CD trigger unit includes a carry signal terminal C, a control signal terminal D, a selection signal terminal SEL, a clock signal terminal CLK, and a status signal terminal QB.

[0062] In this configuration, the control signal terminal D of each CD trigger unit is connected to the signal output terminal of the host computer device. The control signal terminal D is used to receive the frequency division control signals DIV sent by the host computer device in the corresponding sequence. <i:0>Specifically, the CD trigger unit of the i-th order receives the (i-1)-th bit control signal DIV. <i-1>The first CD trigger unit receives the 0th bit control signal DIV. <0> .

[0063] For example, the first-order CD trigger unit receives the 0th bit control signal DIV. <0> The second trigger unit receives the first bit of the control signal DIV. <1> The third triggering unit receives the second bit control signal DIV. <2> .

[0064] The output of the (i-1)th carry unit is connected to the carry signal C of the adjacent ith CD trigger unit. In a specific embodiment, the 2nd CD trigger unit corresponds to the 1st carry unit, the 3rd CD trigger unit corresponds to the 2nd carry unit, and the ith CD trigger unit corresponds to the (i-1)th carry unit.

[0065] The carry signal terminal C of the first CD trigger unit is grounded, and the status signal terminal QB of the first CD trigger unit is connected to the carry signal terminal C of the second CD trigger unit through the carry unit corresponding to the second CD trigger unit.

[0066] Specifically, in this embodiment, the carry unit can be an inverter or a NAND gate or other electronic components.

[0067] According to a specific embodiment of this application, the first carry unit is an inverter, and the j-th carry unit is a NAND gate, where 1 <j≤N-1。

[0068] When the status signal QB0 of the first-order triggering unit changes from 0 to 1, the signal output to the carry signal terminal of the second-order triggering unit through the corresponding carry unit is 0. When the status signal QB0 of the first-order triggering unit changes from 1 to 0, the signal output to the carry signal terminal of the second-order triggering unit through the corresponding carry unit is 1.

[0069] The control terminal SE of the frequency division signal output unit is used to receive the control signal D of all CD trigger units, so as to receive the DIV sent by all host computer devices to the programmable frequency divider. <k:0>Frequency division control signal.

[0070] Specifically, after receiving the frequency division control signal corresponding to each CD trigger unit, the frequency division signal output unit generates a corresponding selection signal and outputs it to the selection signal terminal SEL of the corresponding CD trigger unit to control the output of the state signal terminal of each CD trigger unit according to the selection signal SEL.

[0071] During the switching of the output signal at the status signal terminal, each CD trigger unit implements frequency division processing of the standard clock signal through status signal jumps. When the control terminal SE of the frequency division signal output unit receives the preset frequency division control signal, the frequency division signal output unit will output a clock signal corresponding to the target frequency division ratio.

[0072] The frequency divider signal output unit can be a selector-type electronic component. The control signal terminal D of each CD trigger unit is also connected to the control terminal SE of the frequency divider signal output unit. The first input terminal CLK of the frequency divider signal output unit is used to input a preset standard clock signal. The second input terminal DIV_CLK of the frequency divider signal output unit is connected to the status signal terminal of each CD trigger unit.

[0073] The frequency division signal output unit is based on the frequency division control signal DIV input from the host computer device. <k:0>The target frequency division ratio can be determined; specifically, the target frequency division ratio is DIV. <k:0>The binary parameter value +1.

[0074] When DIV <k:0>When all bits of the frequency division control signal are 0, the frequency division signal output unit outputs an undivided standard clock signal.

[0075] like Figure 3 As shown, according to a specific embodiment of this application, the CD triggering unit includes a D flip-flop, a first selector, and an XNOR gate, wherein,

[0076] The clock signal terminal of the D flip-flop is used to connect to a preset standard clock signal;

[0077] The state signal terminal of the D flip-flop is connected to the first input terminal of the XOR gate, and the second input terminal of the XOR gate is used to connect the output signal of the corresponding carry unit.

[0078] The output of the XOR gate is connected to the first input of the first selector, the second input of the first selector is used to receive the corresponding frequency division control signal, and the control terminal of the first selector is used to receive the preset selection signal.

[0079] The output of the first selector is connected to the control terminal of the D flip-flop;

[0080] The first selector is used to determine whether to receive a signal through the first input terminal or the second input terminal based on the selection signal.

[0081] In a specific embodiment, the internal structure diagram of the CD trigger unit is as follows: Figure 3 As shown, the CD trigger unit includes a D flip-flop, a first selector, and an XNOR gate. The D flip-flop includes a clock signal terminal CLK, a status signal terminal QB, and a signal output terminal Q.

[0082] The first input terminal S of the first selector is connected to the output terminal of the XOR gate. The input terminal of the XOR gate is connected to the output terminal of the corresponding carry unit and the signal output terminal Q of the CD trigger unit, respectively, for receiving the carry signal and the current status signal, so as to calculate the output signal of the status signal terminal QB based on the carry signal and the status signal.

[0083] The second input terminal D of the first selector is used to receive the frequency division control signal sent by the host computer device, and the control terminal SEL of the first selector is used to receive the corresponding selection signal.

[0084] The clock signal terminal CLK of the D flip-flop is used to connect to a preset standard clock signal, so as to perform state signal conversion according to the standard clock signal.

[0085] In a specific embodiment, the QB0 state toggles once each time the clock is triggered, i.e., the state signal increments by 1; when the state signal QB0 is 1, the carry signal C1 is 1; when both state signals QB0 and QB1 are 1, the carry signal C2 is 1, and so on. Based on the working principle, the state equation is obtained as follows:

[0086]

[0087]

[0088] Where i is the level of the CD trigger unit, and n is the status bit.

[0089] C0 = 0

[0090] C1 = QB0

[0091] C2 = QB1·QB0

[0092]

[0093]

[0094]

[0095] To ensure consistency of basic units, the formula is used. so Then, after inverting the D flip-flop, we get... Therefore, the CD trigger unit uses an XOR gate, and the carry input uses a NAND gate.

[0096] According to a specific embodiment of this application, when the signal received by the control terminal of the first selector is a first selection signal, the first selector receives the signal through the first input terminal.

[0097] When the signal connected to the control terminal of the first selector is the second selection signal, the first selector receives the signal through the second input terminal.

[0098] In a specific embodiment, the first selection signal and the second selection signal are 0 and 1, respectively.

[0099] The control terminal of the first selector is connected to the selection signal terminal SEL, and is used to receive the selection signal SEL. When the selection signal SEL is 0, the input signal of the first input terminal S is selected as the output signal of the multiplexer. When the selection signal SEL is 1, the input signal of the second input terminal D is selected as the output signal of the multiplexer.

[0100] According to a specific embodiment of the present application, the frequency division signal output unit includes a second selector, a NOR gate, and a selection signal circuit;

[0101] The input terminal of the NOR gate is used to receive the frequency division control signal, and the output terminal of the NOR gate is connected to the control terminal of the second selector;

[0102] The first input terminal of the second selector is used to connect to a preset standard clock signal;

[0103] The input terminal of the selection signal circuit is connected to the status signal terminal of each CD trigger unit, and the output terminal of the selection signal circuit is connected to the selection signal terminal of each CD trigger unit and is connected to the second input terminal of the second selector.

[0104] The output of the second selector is used to output a clock signal corresponding to the target division ratio.

[0105] In a specific embodiment, the input / output ports of the second selector include a control terminal SE, a first input terminal CLK, a second input terminal DIV_CLK, and an output terminal DIV_OUT.

[0106] Specifically, the output of the NOR gate is connected to the control signal terminal D of each CD trigger unit to receive all the frequency division control signals DIV sent by the host computer device. <k:0>The output of the NOR gate is connected to the control terminal SE of the second selector to control the output signal DIV_OUT of the selector.

[0107] In a specific implementation, when the frequency division control signal DIV <k:0>When both are 0, the signal received by the control terminal SE of the second selector is 0. The second selector selects to output the preset standard clock signal through the first input terminal CLK. That is, the second selector outputs the preset standard clock signal through the output terminal DIV_OUT, that is, no frequency division processing is performed.

[0108] When the frequency division control signal DIV <k:0>When any control signal bit is not 0, the signal received by the control terminal SE of the second selector is 1, and the second selector selects to output the frequency division clock signal connected to the second input terminal DIV_CLK. That is, the second selector outputs the frequency division clock signal with the target frequency division ratio through the output terminal DIV_OUT.

[0109] According to a specific embodiment of the present application, the selection signal circuit includes a NAND gate and a first inverter;

[0110] The input terminal of the NAND gate is connected to the status signal terminal of each CD trigger unit;

[0111] The output of the NAND gate is connected to the input of the first inverter.

[0112] The output terminal of the first inverter is connected to the second input terminal of the second selector as the output terminal of the selection signal circuit.

[0113] In a specific embodiment, the second input terminal DIV_CLK of the selector of the frequency division signal output unit further includes a NAND gate and a first inverter, which are used to implement the predefined SEL selection signal control.

[0114] By setting the NAND gate, the digital signal output by the NAND gate is 0 if and only if QB2 = QB1 = QB0 = 1, and after being processed by the inverter, a selection signal of 1 is obtained.

[0115] Specifically, the input terminal of the inverter is connected to the output terminal of the NAND gate, and the output terminal of the inverter is connected to the blocking circuit and the selection signal terminal SEL of each CD trigger unit.

[0116] According to the input / output control of the CD trigger unit in the above embodiment, the CD trigger unit selects to access the frequency division control signal through the control signal terminal D and outputs the corresponding status signal if and only if the selection signal is 1.

[0117] According to a specific embodiment of this application, the frequency division signal output unit further includes a blocking circuit, the blocking circuit including a preset number of inverters connected in sequence, and the output terminal of the selection signal circuit is connected to the second input terminal of the second selector through the blocking circuit.

[0118] In a specific embodiment, such as Figure 2 As shown, the blocking circuit may comprise two inverters connected in sequence. The blocking circuit prevents the selection signal terminal from being directly connected to the second input terminal of the second selector. Furthermore, the inverters effectively prevent backflow of the electrical signal at the second input terminal of the second selector.

[0119] According to a specific embodiment of the present application, the programmable frequency divider further includes a clock unit;

[0120] The output terminal of the clock unit is connected to the clock signal terminal of the programmable frequency divider, and the clock unit is used to output a preset standard clock signal.

[0121] In a specific implementation, the clock unit can be an independently set crystal clock, used to output a clock signal with a preset timing sequence.

[0122] The clock unit can also be a clock generating component set in a frequency synthesizer device. This embodiment does not specifically limit the setting of the clock unit.

[0123] It should be noted that the preset standard clock signal generated by the clock unit can be used as the clock signal to be processed in this embodiment, or it can be used to realize the jump of the CD trigger unit status signal.

[0124] In a specific embodiment, the CD trigger unit changes according to the clock signal sent by the clock unit. When the clock edge in the clock signal changes or the point value in the clock signal changes, the D flip-flop in the CD trigger unit controls the state signal terminal to perform a preset state signal flipping action, so that the CD trigger unit outputs a +1 state signal QB0.

[0125] Specifically, when the value of the status signal is 1, outputting a +1 status signal will cause the corresponding status signal to perform a carry action, reset the value of the corresponding status signal to 0, and perform a +1 action at the next status signal.

[0126] For example, when the programmable frequency divider receives a frequency division control signal of DIV<2:0>, the signal received by the input terminal of the NAND gate connected to the second input terminal DIV_CLK of the frequency division signal output unit is... The process by which the selection signal circuit in the frequency division signal output unit processes the status signals of each CD trigger unit to obtain the corresponding selection signal is shown in Table 1.

[0127] Table 1

[0128] <![CDATA[QB2]]> <![CDATA[QB1]]> <![CDATA[QB0]]> SEL 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1

[0129] In a specific embodiment, as shown in Table 1, if DIV<2:0>=101 and QB<2:0>=010, the state table is 010→011→100→101→110→111, a total of 6 states. The output division ratio of the frequency divider is DIV<2:0>+1=101+1=6. Therefore, when the input frequency division control signal DIV<2:0>=101, a 6-fold division can be achieved. That is, depending on the value of the 3-bit frequency division control signal DIV<2:0> output by the host computer device, the programmable frequency divider can achieve a 1-8 division.

[0130] Adaptively, as the number of CD flip-flops in the programmable frequency divider increases, the number of bits in the frequency division control signal also increases accordingly, and the achievable frequency division ratio of the programmable frequency divider increases with the increase in the number of CD flip-flops. Of course, the target frequency division ratio also needs to be determined based on the value of the input frequency division control signal, which is the value of the frequency division control signal + 1.

[0131] For example, when the number of CD flip-flops in the programmable frequency divider is 4, the frequency division control signal is a 4-bit frequency division control signal DIV<3:0>, and the programmable frequency divider can achieve a frequency division of 1-16. When DIV<3:0> = 1011, the target frequency division ratio is 12.

[0132] The frequency division control signal of the programmable frequency divider provided in this embodiment is programmable. This signal can be decoded by a host computer device, allowing the user to input the target frequency division control signal to achieve any division ratio. The programmable frequency divider in this embodiment can achieve full-range programmable continuous frequency division without long-delay feedback loops, greatly expanding its application range.

[0133] refer to Figure 4 This is a schematic flowchart illustrating a frequency divider programming method provided in an embodiment of this application. The frequency divider programming method provided in this embodiment is applied to the programmable frequency divider in the aforementioned embodiments, such as... Figure 4 As shown, the frequency divider programming method includes:

[0134] Step S401: Obtain the preset standard clock signal and frequency division control signal;

[0135] Step S402: Perform frequency division processing on the standard clock signal according to the frequency division control signal to obtain the target clock signal with the corresponding target frequency division ratio.

[0136] Specifically, the frequency divider programming method can be implemented by an integrated software or hardware device, and this embodiment does not specifically limit it.

[0137] In a specific embodiment, the user inputs any target frequency division ratio through a host computer device. After the frequency division ratio is calculated, a frequency division control signal can be obtained. The frequency division control signal is a binary parameter signal. By inputting the frequency division control signal into the above-mentioned programmable frequency divider, the standard clock signal can be divided according to the frequency division control signal to obtain a target clock signal with the corresponding target frequency division ratio.

[0138] The specific implementation method of the frequency divider programming method can be referred to the specific implementation method of the programmable frequency divider described above, and will not be repeated here.

[0139] In addition, this application embodiment also provides a frequency synthesizer device, which includes the programmable frequency divider in the foregoing embodiments.

[0140] In summary, this application provides a programmable frequency divider, a frequency divider programming method, and a frequency synthesizer device. The novel programmable frequency divider implemented by this invention can achieve full-range programmable continuous frequency division function, and there is no long-delay feedback loop. The circuit structure is simple and easy to implement, and it can be widely used in various PLL circuits, possessing strong practical value. Furthermore, the specific implementation process of the frequency divider programming method and the frequency synthesizer device mentioned in the foregoing embodiments can be found in the specific implementation process of the above method embodiments, and will not be repeated here.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0142] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0143] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A programmable frequency divider, characterized in that, The programmable frequency divider includes N CD trigger units, N-1 carry units, and a frequency division signal output unit, wherein the N CD trigger units are connected in a preset order; The control signal terminal of each CD trigger unit is used to connect to the corresponding frequency division control signal; The carry signal terminal of the i-th CD trigger unit is connected to the output terminal of the (i-1)-th carry unit. The input terminal of the carry unit in the (i-1)th order is connected to the status signal terminal of each CD trigger unit before the i-th order, where, ; The carry signal terminal of the first CD trigger unit is grounded; The control terminal of the frequency division signal output unit is used to receive the frequency division control signal, the first input terminal of the frequency division signal output unit is used to receive the preset standard clock signal, and the second input terminal of the frequency division signal output unit is connected to the status signal terminal of each CD trigger unit. The frequency division signal output unit outputs a target clock signal corresponding to the target frequency division ratio according to the frequency division control signal.

2. The programmable frequency divider according to claim 1, characterized in that, The CD triggering unit includes a D flip-flop, a first selector, and an XOR gate, wherein... The clock signal terminal of the D flip-flop is used to connect to a preset standard clock signal; The state signal terminal of the D flip-flop is connected to the first input terminal of the XOR gate, and the second input terminal of the XOR gate is used to connect the output signal of the corresponding carry unit. The output of the XOR gate is connected to the first input of the first selector, the second input of the first selector is used to receive the corresponding frequency division control signal, and the control terminal of the first selector is used to receive the preset selection signal. The output of the first selector is connected to the control terminal of the D flip-flop; The first selector is used to determine, based on the selection signal, whether to receive a signal through a first input terminal of the first selector or a second input terminal of the first selector.

3. The programmable frequency divider according to claim 2, characterized in that, When the signal connected to the control terminal of the first selector is the first selection signal, the first selector receives the signal through the first input terminal of the first selector. When the signal received at the control terminal of the first selector is the second selection signal, the first selector receives the signal through the second input terminal of the first selector.

4. The programmable frequency divider according to claim 1, characterized in that, The carry unit of the first sequence is an inverter, and the carry unit of the j-th sequence is a NAND gate, where 1 <j≤N-1。 5. The programmable frequency divider according to claim 1, characterized in that, The frequency division signal output unit includes a second selector, an NOR gate, and a selection signal circuit; The input terminal of the NOR gate is used to receive the frequency division control signal, and the output terminal of the NOR gate is connected to the control terminal of the second selector; The first input terminal of the second selector is used to connect to a preset standard clock signal; The input terminal of the selection signal circuit is connected to the status signal terminal of each CD trigger unit, and the output terminal of the selection signal circuit is connected to the selection signal terminal of each CD trigger unit and is connected to the second input terminal of the second selector. The output of the second selector is used to output a clock signal corresponding to the target division ratio.

6. The programmable frequency divider according to claim 5, characterized in that, The selection signal circuit includes a NAND gate and a first inverter; The input terminal of the NAND gate is connected to the status signal terminal of each CD trigger unit; The output of the NAND gate is connected to the input of the first inverter. The output terminal of the first inverter is connected to the second input terminal of the second selector as the output terminal of the selection signal circuit.

7. The programmable frequency divider according to claim 5, characterized in that, The frequency division signal output unit further includes a blocking circuit, which includes a preset number of inverters connected in sequence. The output terminal of the selection signal circuit is connected to the second input terminal of the second selector through the blocking circuit.

8. The programmable frequency divider according to claim 1, characterized in that, The programmable frequency divider also includes a clock unit; The output terminal of the clock unit is connected to the clock signal terminal of the programmable frequency divider, and the clock unit is used to output a preset standard clock signal.

9. A frequency divider programming method, characterized in that, The programmable frequency divider described in any one of claims 1-8, wherein the frequency divider programming method comprises: Obtain the preset standard clock signal and frequency division control signal; The standard clock signal is divided according to the frequency division control signal to obtain a target clock signal with a corresponding target frequency division ratio.

10. A frequency synthesizer device, characterized in that, The frequency synthesizer device includes the programmable frequency divider as described in any one of claims 1 to 8.

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