Partial correlation multiple sampling single slope adc with incrementally selectable counter

Abstract

The application provides a single slope analog to digital converter (SS-ADC). The SS-ADC comprises a comparator configured to compare an analog signal with a ramp signal for analog to digital (AD) conversion of a reset level and a signal level multiple times, respectively, wherein an amplitude of the ramp signal for at least one AD conversion of the signal level other than a last AD conversion of the signal level is less than an amplitude of the ramp signal for the last AD conversion of the signal level; a counter configured to increase a count value by an increment for each clock until the amplitude of the ramp signal reaches an amplitude of the analog signal; and a controller configured to select a multiplier factor of a counter increment for each counter clock to obtain the count value corresponding to a number of the AD conversion of the signal level being the same as a number of the AD conversion of the reset level in a case that the amplitude of the ramp signal for a part of the AD conversion of the signal level does not reach the amplitude of the analog signal. The application reduces time noise without increasing conversion time.

Description

Technical Field

[0001] This invention relates to an analog-to-digital converter for image sensors. Background Technology

[0002] Image sensors, such as complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors, are classified as among the most noise-sensitive devices because most of them achieve conversion gains on the order of microvolts at their voltage output. Therefore, several noise reduction techniques have been developed, such as multisampling. Multisampling averages the results of the same N analog-to-digital (AD) conversions to reduce their time noise by a factor of 1 / (N square root). However, this technique also requires time to perform N AD conversions and limits frame rate improvements. Summary of the Invention

[0003] This invention provides a method based on multiple sampling technology to reduce the temporal noise of a single-slope analog-to-digital converter (SS-ADC) and its analog inputs (i.e., column-parallel ADCs and pixel source followers in CMOS image sensors) and to suppress the increase in its conversion time.

[0004] According to a first aspect, a single-slope analog-to-digital converter (SS-ADC) is provided, the SS-ADC comprising: a comparator for comparing an analog signal with a ramp signal for analog-to-digital (AD) conversions for a reset level and a signal level multiple times, wherein the amplitude of the ramp signal for at least one AD conversion not for the last AD conversion of the signal level is less than the amplitude of the ramp signal for the last AD conversion of the signal level; a counter for incrementing a count value by each clock cycle until the amplitude of the ramp signal reaches the amplitude of the analog signal; and a controller for selecting a multiplier factor of the counter increment for each counter clock cycle to obtain the count value if the amplitude of the ramp signal for a portion of the AD conversions for the signal level does not reach the amplitude of the analog signal, the count value corresponding to the same number of AD conversions for the signal level as the number of AD conversions for the reset level.

[0005] In a first possible implementation of the first aspect, the amplitude of the ramp signal for the non-last AD conversion of the signal level is the same as the amplitude of the ramp signal for the AD conversion of the reset level.

[0006] In a second possible implementation of the first aspect, the amplitudes of the ramp signals for the last two or more AD conversions of the signal level are the same and greater than the amplitude of the ramp signal for the first AD conversion of the signal level.

[0007] In a third possible implementation of the first aspect, the amplitude of the ramp signal for the non-last AD conversion of the signal level is greater than the amplitude of the ramp signal for the reset level of the AD conversion, but not greater than the amplitude of the ramp signal for the last AD conversion of the signal level.

[0008] In a fourth possible implementation of the first aspect, the amplitude of the ramp signal for the non-last AD conversion of the signal level includes at least two levels, but is not greater than the amplitude of the ramp signal for the last AD conversion of the signal level.

[0009] In a fifth possible implementation of the first aspect, the controller detects that the amplitude of the ramp signal for a portion of the AD conversion of the signal level does not reach the amplitude of the analog signal by detecting a lack of output from the comparator used for the AD conversion.

[0010] In a sixth possible implementation of the first aspect, the amplitude of the ramp signal for the AD conversion of the signal level is equal to or greater than the amplitude of the ramp signal for the previous AD conversion; and at least one of the amplitude sequences is less than the amplitude of the last AD conversion.

[0011] According to a second aspect, a ramp generator is provided for generating ramp signals for analog-to-digital (AD) conversions for reset level and signal level multiple times, wherein the amplitude of the ramp signal for at least one AD conversion other than the last AD conversion for the signal level is less than the amplitude of the ramp signal for the last AD conversion for the signal level.

[0012] According to a third aspect, an analog-to-digital (AD) conversion method is provided, the method comprising: comparing an analog signal multiple times with ramp signals for analog-to-digital (AD) conversions for a reset level and a signal level, wherein the amplitude of the ramp signal for at least one AD conversion (not the last AD conversion) for the signal level is less than the amplitude of the ramp signal for the last AD conversion for the signal level; incrementing a count value by each clock cycle until the amplitude of the ramp signal reaches the amplitude of the analog signal; and selecting a multiplier factor of the increment to obtain a count value when the amplitude of the ramp signal for a portion of the AD conversion for the signal level does not reach the amplitude of the analog signal, the count value corresponding to the same number of AD conversions for the signal level as the number of AD conversions for the reset level. Attached Figure Description

[0013] To more clearly describe the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings required for describing the embodiments or the prior art are briefly introduced below. Obviously, the drawings in the following description only illustrate some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0014] Figure 1 A schematic diagram of a partially correlated multiple sampling SS-ADC (PCMS SS-ADC) provided in an embodiment of the present invention is shown;

[0015] Figure 2(a) shows an example of a RAMP waveform used for correlated double sampling (CDS);

[0016] Figure 2(b) shows an example of a RAMP waveform used for correlated multiple sampling (CMS);

[0017] Figure 3(a) shows an example of a RAMP waveform used for partial multisampling;

[0018] Figure 3(b) shows an example of a small-signal comparator output;

[0019] Figure 3(c) shows an example of a large-signal comparator output;

[0020] Figure 4(a) shows an example of the RAMP waveform shown in Figure 3(a);

[0021] Figure 4(b) shows an example of the small signal CMP_OUT shown in Figure 3(b);

[0022] Figure 4(b1) shows the count value of CMP_OUT as shown in Figure 3(b);

[0023] Figure 4(b2) shows the data stored in the latch;

[0024] Figure 4(c) shows an example of the large signal CMP_OUT shown in Figure 3(c);

[0025] Figure 4(c1) shows the count value of CMP_OUT as shown in Figure 3(c);

[0026] Figure 4(c2) shows the data stored in the latch;

[0027] Figure 5 An example of an AD conversion flowchart provided by an embodiment of the present invention is shown;

[0028] Figure 6 An exemplary RAMP waveform with multiple ramps having a full-scale range is shown;

[0029] Figure 7 An exemplary RAMP waveform is shown, wherein the magnitude of the falling slope for the AD conversion of the signal level (except for the last one) is set to the midpoint between the magnitude of the falling slope for the AD conversion of the reset level and the magnitude of the full-scale range.

[0030] Figure 8 An exemplary RAMP waveform is shown, in which the magnitude of the falling slope for the AD conversion of the signal level gradually increases;

[0031] Figure 9 It shows Figure 1 A schematic diagram of an increment-selectable counter is shown;

[0032] Figure 10(a) shows an example of RAMP waveform and small signal input;

[0033] Figure 10(a1) shows an exemplary waveform of CNT_EN;

[0034] Figure 10(a2) shows an exemplary waveform of INDEX;

[0035] Figure 10(a3) shows an exemplary waveform of MSEN;

[0036] Figure 10(a4) shows an exemplary waveform of RST_CNT;

[0037] Figure 10(a5) shows an exemplary waveform of INV;

[0038] Figure 10(a6) shows an exemplary waveform of LAT;

[0039] Figure 10(a7) shows an exemplary waveform of RST_LAT;

[0040] Figure 10(b) shows an example of the small signal CMP_OUT shown in Figure 3(b);

[0041] Figure 10(b1) shows the count value of CMP_OUT as shown in Figure 3(b);

[0042] Figure 10(b2) shows the data stored in the latch;

[0043] Figure 11(a) shows an example of RAMP waveform and large signal input;

[0044] Figure 11(a1) shows an exemplary waveform of CNT_EN;

[0045] Figure 11(a2) shows an exemplary waveform of INDEX;

[0046] Figure 11(a3) shows an exemplary waveform of MSEN;

[0047] Figure 11(a4) shows an exemplary waveform of RST_CNT;

[0048] Figure 11(a5) shows an exemplary waveform of INV;

[0049] Figure 11(a6) shows an exemplary waveform of LAT;

[0050] Figure 11(a7) shows an exemplary waveform of RST_LAT;

[0051] Figure 11(c) shows an example of the large signal CMP_OUT shown in Figure 3(c);

[0052] Figure 11(c1) shows the count value of CMP_OUT as shown in Figure 3(c);

[0053] Figure 11(c2) shows the data stored in the latch. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the protection scope of the present invention.

[0055] Figure 1A schematic diagram of a Partial Correlated Multiple Sampling SS-ADC (PCMS SS-ADC) provided in an embodiment of the present invention is shown. Figure 1 The left-side pixel circuitry includes a floating diffusion (FD), a selection switch (SEL), and a current source connected in series between the power supply voltage and ground. The ADC is connected between the drain of the SEL and the current source. A pixel signal (PIXEL), as an analog signal, is input through a capacitor to the inverting input of a comparator (CMP), and a ramp signal (RAMP) generated by a RAMP generator is input through a capacitor to the non-inverting input of the CMP. The RAMP generator outputs a RAMP waveform for partial multiple sampling. The RAMP generator can be shared by SS-ADCs for pixels placed in the same column. The output of the CMP is input to an increment selectable counter, which includes a counter (CNT) and an increment selector, the increment selector being the controller of the CNT. The CNT counts a clock signal (CLK), for example, the number of cycles of the CLK, incrementing the count value for each cycle of the CLK, and storing the count value in a latch according to a control signal. Figure 1 (Not shown in the image). The increment selector can select the increment for each cycle of the CLK to obtain the count value corresponding to the AD conversion multiple times.

[0056] Before illustrating an example of the RAMP waveform provided by the present invention with reference to Figure 3(a), a typical RAMP waveform is illustrated with reference to Figures 2(a) and 2(b). Figure 2(a) shows an example of a RAMP waveform used for correlated double sampling (CDS). The solid line represents the ramp signal (RAMP), and the dashed line represents the pixel output at the reset level. The reset level and signal level are sampled as follows: a first falling slope is used for the AD conversion of the pixel output at the reset level, and a second falling slope is used for the AD conversion of the pixel output at the signal level. The CNT starts counting from the first falling slope and counts until the first falling slope intersects the dashed line. This count value corresponds to the reset level. If there is no signal from the pixel, the signal level is the same as the reset level, i.e., the level of the dashed line does not change. The CNT starts counting from the second falling slope and counts until the second falling slope intersects the dashed line. If there is a signal from the pixel, the dashed line drops to a level corresponding to the signal amplitude below the reset level, and the CNT starts counting from the second falling slope and counts until the second falling slope intersects the dashed line. This count value corresponds to the signal level. The output level is defined as the difference between the count value corresponding to the signal level and the count value corresponding to the reset level.

[0057] Figure 2(b) shows an example of a RAMP waveform used for correlated multiple sampling (CMS). To reduce time noise, the reset level is sampled three times, then the signal level is sampled three times, and the sampled values ​​of the reset level and the signal level are averaged accordingly. The output level is defined as the difference between these averages. The number of samples is not limited to three. Different numbers of samples are applicable. If the number of samples is 4, the time noise will be reduced to 1 / (square root of 4) = 1 / 2. As can be seen from Figures 2(a) and 2(b), the time required for CMS (Figure 2(b)) is increased compared to CDS (Figure 2(a)).

[0058] Figure 3(a) shows an example of a RAMP waveform used for partial multiple sampling. The solid line represents the ramp signal (RAMP). In Figure 3(a), the reset level and the signal level are sampled four times respectively, and compared to Figure 2(b), the full-scale range is applied only to the last falling slope of the AD conversion for the signal level. In other words, the falling slope of the AD conversion for the signal level (except for the last one) is equal to or greater than the falling slope of the AD conversion for the reset level, and less than the last falling slope of the AD conversion for the signal level. The duration of the latter half of the RAMP shown in Figure 3(a) is shorter than the duration of the latter half of the RAMP with four falling slopes having a full-scale range.

[0059] Regarding the dashed lines in Figure 3(a), the first half represents pixel outputs at the reset level, and the second half represents pixel outputs at the small signal level. In Figure 3(a), the small signal level is shown as being the same as the reset level. Regarding the dotted lines in Figure 3(a), the first half represents pixel outputs at the reset level, and the second half represents pixel outputs at the large signal level.

[0060] Figure 3(b) shows an example of the comparator output at reset level and small signal level (shown by the dashed line in Figure 3(a)). The pulse rises when the falling slope of the RAMP crosses the dashed line downwards; the pulse falls when the rising edge of the RAMP crosses the dashed line. As indicated by the arrow in Figure 3(b), the CNT counts from the beginning of the falling slope to the rising edge of the comparator output.

[0061] Figure 3(c) shows an example of the comparator output at the reset level and the large signal level of the pixel output, as indicated by the dotted line in Figure 3(a). The pulse rises when the falling slope of the RAMP crosses the dashed line downwards; the pulse falls when the rising edge of the RAMP crosses the dashed line. The first four pulses correspond to the reset level, and the last pulse corresponds to the large signal level. The latter half of the dotted line (where the pixel output is at the large signal level) does not cross the three smaller falling slopes in the latter half of the RAMP, but rather crosses the last falling slope. The rising edge of the comparator output is used to stop counting. For the latter half of the RAMP in Figure 3(c), the CNT counts in increments of four from the beginning of the last falling slope to the rising edge of the comparator output corresponding to the last falling slope, as described below.

[0062] refer to Figures 4(a) to 4(c2)The relationship between the comparator output, the CNT count value, and the data stored in the latch is described below. Figures 4(a), 4(b), and 4(c) are identical to Figures 3(a), 3(b), and 3(c), respectively. Figure 4(b1) shows the CMP_OUT count value shown in Figure 4(b); Figure 4(b2) shows the data stored in the latch. Initially, the count value shown in Figure 4(b1) (COUNTER) is reset to 0, and the value shown in Figure 4(b2) (DATA) is 0. The CNT starts counting when the first falling slope of the RAMP begins. The count value increases linearly. On the rising edge of the CMP_OUT (comparator output), the CNT stops counting. The CNT resumes counting when the next falling slope of the RAMP begins. The count value is accumulated over four falling slopes. The count value (positive number) is converted to a negative value and stored in the latch, and then the count value is reset to 0. For CMP_OUT corresponding to the latter half of the RAMP, the CNT operates in a similar manner. The accumulated count value is substantially the same as the accumulated count value of the first half of the RAMP. As shown in the last part of Figure 4(b2), the accumulated count value is added to the data stored in the latch. The data corresponds to the value calculated by subtracting the count value of the four AD conversions of the reset value from the count value of the four AD conversions of the signal value. The value calculated by dividing the data in the latch by 4 is equal to the difference between the average of the four AD conversions of the signal level and the average of the four AD conversions of the reset level.

[0063] Before converting the count value of the four AD conversions at the reset level to a negative value and storing it in the latch, the value can be divided by 4; similarly, before storing the count value of the four AD conversions at the signal level in the latch, the value can be divided by 4. In this case, the value finally stored in the latch is the difference between the average of the four AD conversions at the signal level and the average of the four AD conversions at the reset level.

[0064] Figure 4(c1) shows the count value of CMP_OUT as shown in Figure 4(c); Figure 4(c2) shows the data stored in the latch. In Figure 4(a), for the first half of the RAMP, the values ​​of the dashed and dotted lines are the same, and the count value in Figure 4(c1) and the data in Figure 4(c2) are the same as the count value in Figure 4(b1) and the data in Figure 4(b2), respectively.

[0065] The CNT begins counting when the first falling slope of the latter half of the RAMP begins. The count value increases linearly, as shown in Figure 4(c1). On the rising edge following the first falling slope of the latter half of the RAMP, the increment selectable counter knows that no signal level has been detected because the first falling slope of the latter half of the RAMP has not crossed the dotted line and no CMP_OUT corresponding to the first falling slope of the latter half of the RAMP has been generated. The count value is then reset. As described above, for example, the CNT counts the number of cycles of the clock signal (CLK) and increments the count value for each cycle of the CLK. The CNT triples the increment for each cycle of the CLK, i.e., this increment (hereinafter referred to as the "boost increment") is four times the increment used for the first half of the RAMP (hereinafter referred to as the "normal increment"). This means that a count value counted once using the "boost increment" corresponds to a count value counted four times using the "normal increment". The CNT is disabled at the end of the third falling slope of the latter half of the RAMP, as described below.

[0066] Even if the signal level is detected in the first falling slope of the latter half of the RAMP, it may be impossible to detect the signal level of the second or third falling slope due to noise if the signal level is close to the level at the end of the falling slope. Even in this case, the count value is reset, and the increment is tripled in the same manner as described above. However, as long as the signal level is detected, assuming the number of falling slopes for the AD conversion of the signal level is N, the detection of the signal level continues until the (N-1)th falling slope of the latter half of the RAMP ends.

[0067] The CNT begins counting when the fourth falling slope of the latter half of the RAMP begins. In Figure 4(c1), the count value increases at a rate of 4 times. The CNT stops counting at the rising edge of CMP_OUT, as shown in Figure 4(c). As shown in the final part of Figure 4(c2), the count value is added to the data stored in the latch. This data is equal to the value calculated by subtracting the count value of four AD conversions with a reset value having a "normal increment" from the count value of one AD conversion with a "boost increment" signal value. The value calculated by dividing the data in the latch by 4 is equal to the difference between the average of one AD conversion at the signal level and the average of four AD conversions at the reset level.

[0068] Before converting the accumulated value of the four AD conversions for the reset level to a negative value and storing it in the latch, the value can be divided by 4. In this case, the increment may not increase by a factor of three if no drop slope from the first to the third drop slope of the signal level is detected. The value finally stored in the latch is the difference between the one AD conversion of the signal level and the average of the four AD conversions for the reset level.

[0069] Figure 5 An example flowchart of an AD conversion provided by an embodiment of the present invention is shown. According to the Partial Correlated Multiple Sampling (PCMS) SS-ADC of the present invention, the CNT selects either CMS mode or CDS mode by detecting the presence or absence of a comparator output in the AD conversion of the signal level (excluding the last AD conversion of the signal level). The magnitude of the falling slope for the AD conversion of the signal level (excluding the last AD conversion of the signal level) is smaller than the magnitude of the last falling slope having a full-scale range. Therefore, the PCMS SS-ADC can select the following operating modes: CMS mode for small signal levels or CDS mode for large signal levels. In CDS mode, since the AD conversion of the reset level has a count value for N samples, the last AD conversion of the signal level is performed using an N-fold increment (the increment of the last signal is N times the "normal increment").

[0070] refer to Figure 5 In step S1, N AD conversions of the reset level are performed and the results are saved. In step S2, AD conversion of the signal level is performed, wherein the ramp amplitude is less than the full-scale range. In step S3, it is determined whether a comparator output exists. If yes, the process proceeds to step S5. If no, in step S4, the counter is reset, the counter increment is set to N times, and the process waits until the (N-1)th AD conversion of the signal level is completed. In step S5, it is determined whether all AD conversions of the signal level from the 1st to the (N-1)th AD conversion are completed. If yes, the process proceeds to step S6. If no, the process proceeds to step S2. In step S6, the last AD conversion of the signal level is performed, wherein the ramp amplitude is the full-scale range. In step S7, the difference between the average value of the AD conversions of the signal level and the average value of the AD conversions of the reset level is output.

[0071] In Figure 3(a), the full-scale range is applied only to the last falling slope of the AD conversion used for the signal level. The magnitude of the falling slope of the AD conversion used for the signal level (except for the last one) can vary between the magnitude of the falling slope of the AD conversion used for the reset level and the magnitude of the full-scale range. Figures 6 to 8 The modified RAMP waveform is shown. In any case, the duration of the second half of the RAMP is shorter than the duration of the second half of the RAMP with four falling slopes across the full-scale range.

[0072] Figure 6 An exemplary RAMP waveform with multiple falling slopes having a full scale range (FSR) is shown. The full scale range is applied to the last plurality of falling slopes. Assuming the number of falling slopes for the AD conversion of the signal level is N, the full scale range is applied to fewer than N falling slopes for the AD conversion of the signal level. Figure 6 In the second half of the RAMP, the magnitudes of the last two falling slopes are the full-scale range, and the magnitudes of the first two falling slopes are S0. If the magnitude of the analog input is not greater than S0, then CMS with 4 samples is applied.

[0073] If the amplitude of the analog input is greater than S0, then CMS is applied with two samples. In this case, at the first rising edge of the second half of the RAMP, the increment selectable counter knows that the signal level has not been detected because no CMP_OUT corresponding to the first falling slope of the second half of the RAMP is generated. Then, CNT resets the counter value, doubles the increment of CLK for each cycle, and is disabled at the end of the second falling slope, and then performs AD conversion of the signal level for the last two falling slopes.

[0074] Figure 7 An exemplary RAMP waveform is shown, in which the magnitude of the falling slope for the AD conversion of the signal level (except for the last one) is set to the midpoint S0' between the magnitude of the falling slope for the AD conversion of the reset level and the magnitude of the full scale range (FSR). If the amplitude of the analog input is not greater than S0', CMS is applied for N samples. If the amplitude of the analog input is greater than S0', CDS is applied. This RAMP waveform extends the amplitude of the signal level for multiple sampling.

[0075] Figure 8An exemplary RAMP waveform is shown, in which the magnitude of the falling slope for the AD conversion of the signal level gradually increases. Multiple multisampling modes can be set for several amplitude ranges of the analog input. In the case of 4 samplings, the amplitude for the AD conversion of the signal level is set to S0, S0, S1, and so on. Figure 8 The full scale range (FSR) is shown. If the analog input amplitude is no greater than S0, CMS with 4 samples is applied. If the analog input amplitude is greater than S0 but not greater than S1, CMS with 2 samples is applied. If the analog input amplitude is greater than S1, CDS is applied.

[0076] If the amplitude of the analog input is greater than S0, at the first rising edge of the latter half of the RAMP, the increment selectable counter knows that the signal level has not been detected because no CMP_OUT corresponding to the first falling slope of the latter half of the RAMP is generated. Then, the CNT resets its count value, doubles the increment of CLK for each cycle, and is disabled at the end of the second falling slope. The CNT resumes counting when the third falling slope of the RAMP begins. If the amplitude of the analog input is not greater than S1, an AD conversion of the signal level is performed for the last two falling slopes.

[0077] If the amplitude of the analog input is greater than S1, then on the third rising edge of the latter half of the RAMP, the increment selectable counter knows that the signal level has not been detected because no CMP_OUT corresponding to the third falling slope of the latter half of the RAMP is generated. The CNT then resets the count value. The CNT triples the increment of each cycle of the CLK, i.e., the increment is four times the "normal increment," and performs an AD conversion of the signal level on the last falling slope. In this case, additional signals or additional bits can be used to specify one of the "normal increment," double increment, and quadruple increment.

[0078] Figure 1 The CNT shown in Figures 4(b1) and 4(c1) is interpreted as an adder counter that increments the count value. The CNT can be implemented as both a subtractor counter and an adder counter; for the reset-level AD conversion, the subtractor counter decrements the count value by a negative value of the "normal increment" as described above; for the signal-level AD conversion, the adder counter increments the count value. In this case, when the count value used for the reset-level AD conversion is stored in a latch, it is not necessary to convert the count value to a negative value.

[0079] Figure 9 It shows Figure 1The diagram shows an increment-selectable counter. Figure 9 It shows Figure 1 The components other than the CNT and incremental selector are shown, and the control signals are illustrated in detail. Figure 9 The “CMP_OUT”, “CNT_EN”, “ADC_CLK”, and “LAT_OUT” shown correspond to Figure 1 The symbols shown are "CMP_OUT", "Monitoring Enable", "CLK", and "Digital Output".

[0080] Figures 10(a) to 10(b2) The waveform of the control signal associated with the incremental selectable counter is shown when the analog input is the small signal shown by the dashed line in Figure 4(a). Figure 10(a) shows the RAMP waveform and dashed line shown in Figure 4(a). Figures 10(b), 10(b1), and 10(b2) are the same as Figures 4(b), 4(b1), and 4(b2), respectively. The duration when CNT_EN is "high" corresponds to the falling slope of the RAMP. CMP_OUT detector ( Figure 9 Use CNT_EN and CMP_OUT to mask ADC_CLK. Figure 9 The ADC_CLK is counted from the rising edge of CNT_EN to the rising edge of CMP_OUT. Assuming the number of falling slopes for the AD conversion of the signal level is N, then INDEX is "high" from the rising edge of the first CNT_EN pulse to the falling edge of the (N-1)th CNT_EN pulse in the latter half of the RAMP. When INDEX is "high", it is possible to switch from CMS to CDS. Multiple sampling enable (MSEN) selects either CMS or CDS. For example, when MSEN is "high", CMS is selected; when MSEN is "low", CDS is selected. RST_CNT is used to reset the count value in the counter. When LAT is "high", the count value in the counter is transferred to the latch and the adder / subtractor. If INV is "high", the count value (positive number) is converted to a negative value and stored in the latch. If INV is "low", the count value is stored in the latch as is. When RST_LAT is "high", the data stored in the latch is reset to 0.

[0081] Figures 11(a) to 11(c2)The waveform of the control signal associated with the incremental selectable counter is shown when the analog input is the large signal shown by the dotted line in Figure 4(a). Figure 11(a) shows the RAMP waveform and dotted line shown in Figure 4(a). Figures 11(c), 11(c1), and 11(c2) are the same as Figures 4(c), 4(c1), and 4(c2), respectively. Figures 11(a1), 11(a2), and... Figures 11(a5) to 11(a7) Compared with Figure 10(a1), Figure 10(a2) and respectively Figures 10(a5) to 10(a7) Same. Figures 11(a3) and 11(a4) are different from Figures 10(a3) and 10(a4). When the first falling slope of the latter half of the RAMP begins, and when CNT_EN becomes "high", the counter ( Figure 9 The counting begins. The count value increases linearly. On the rising edge of RAMP, CNT_EN goes "low". Since CMP_OUT does not go "high" when CNT_EN is "high", the CMS / CDS determination circuit ( Figure 9 The CDS is selected by setting MSEN to "low". Since the counter resumes counting on the rising edge of CNT_EN (when the falling slope of the RAMP begins), RST_CNT is "high" from the falling edge of MSEN to the falling edge of the INDEX.

[0082] As shown in Figure 10, when the analog input amplitude is small, the PCMS SS-ADC operates in the same manner as the conventional CMS, outputting an AD conversion result with a noise reduction factor of 1 / (square root of N). On the other hand, when the analog input amplitude is large, the reset-level AD conversion operates in the same manner as in the case of small amplitude, and the last AD conversion of the signal level is operated using an increment of N times the counter for each counting clock cycle.

[0083] This invention can be used to reduce the noise level of CMOS image sensors. Under low illumination conditions, this invention halves the noise level by setting the number of multiple sampling repetitions to 4. If the ramp amplitude for the first 3 AD conversions used for the signal level is set to 1 / 3 of the full-scale range, the AD conversion time for multiple sampling can be reduced to 1 / 3 compared to conventional CMS.

[0084] In addition to CMOS image sensors, this invention can also be used in fingerprint sensors because it is effective for single-slope ADCs.

[0085] The effects of the above implementation method of PCMS SS-ADC are as follows:

[0086] (1) It can suppress the increase in ADC time in CMS implementation mode.

[0087] (2) A common RAMP generator can be used to achieve partial multisampling effects. This means that there is no need to consider waveform matching of multiple RAMP channels, nor is there a need to consider RAMP waveform distortion caused by changes in the connection between RAMP and comparator.

[0088] (3) Since PCMS SS-ADC only requires modification of the digital circuit blocks of traditional SS-ADC, chip area expansion for implementing additional functions can be suppressed.

[0089] (4) No new vertical control signal needs to be added through the crosstalk-sensitive comparator region.

[0090] The content disclosed above is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments, as well as equivalent modifications made according to the claims of the present invention, should fall within the scope of the present invention.

Claims

1. A single-slope analog-to-digital converter (SS-ADC), characterized in that, include: A comparator is used to compare an analog signal with ramp signals for analog-to-digital (AD) conversion for a reset level and a signal level multiple times, wherein the amplitude of the ramp signal for at least one AD conversion other than the last AD conversion for the signal level is less than the amplitude of the ramp signal for the last AD conversion for the signal level. A counter is used to increment the count value every clock cycle until the amplitude of the ramp signal reaches the amplitude of the analog signal. A controller is configured to select a multiplier factor for the counter increment of each counter clock to obtain the count value when the amplitude of the ramp signal for a portion of the AD conversion at the signal level does not reach the amplitude of the analog signal, the count value corresponding to the number of AD conversions at the signal level being the same as the number of AD conversions at the reset level.

2. The SS-ADC according to claim 1, characterized in that, The amplitude of the ramp signal for the non-last AD conversion used for the signal level is the same as the amplitude of the ramp signal for the AD conversion used for the reset level.

3. The SS-ADC according to claim 1, characterized in that, The amplitudes of the ramp signals used for the last two or more AD conversions of the signal level are the same and greater than the amplitude of the ramp signal used for the first AD conversion of the signal level.

4. The SS-ADC according to claim 1, characterized in that, The amplitude of the ramp signal for the non-last AD conversion used for the signal level is greater than the amplitude of the ramp signal for the AD conversion used for the reset level.

5. The SS-ADC according to claim 1, characterized in that, The amplitude of the ramp signal used for the non-last AD conversion of the signal level includes at least two levels.

6. The SS-ADC according to claim 1, characterized in that, The controller detects that the amplitude of the ramp signal, which is a portion of the AD conversion used for the signal level, does not reach the amplitude of the analog signal by detecting a lack of output from the comparator used for the AD conversion.

7. The SS-ADC according to claim 1, characterized in that, The amplitude of the ramp signal used for the AD conversion of the signal level is equal to or greater than the amplitude of the ramp signal used for the previous AD conversion; and at least one of the amplitude sequences is less than the amplitude of the last AD conversion.

8. A slope generator, characterized in that, Ramp signals for analog-to-digital (AD) conversion for reset level and signal level are generated multiple times, wherein the amplitude of the ramp signal for at least one AD conversion other than the last AD conversion for the signal level is less than the amplitude of the ramp signal for the last AD conversion for the signal level. The ramp signals generated multiple times are used to compare with the analog signals multiple times. The ramp signal causes the counter in the SS-ADC to increment by the count value every clock cycle until the amplitude of the ramp signal reaches the amplitude of the analog signal. If the amplitude of the ramp signal, which is a portion of the AD conversion at the signal level, does not reach the amplitude of the analog signal, the controller in the SS-ADC selects a multiplier factor for the counter increment of each counter clock to obtain the count value, which corresponds to the number of AD conversions at the signal level that is the same as the number of AD conversions at the reset level.

9. An analog-to-digital (AD) conversion method, characterized in that, include: The analog signal is compared multiple times with the ramp signal of the analog-to-digital (AD) conversion used for the reset level and the signal level, wherein the amplitude of the ramp signal of at least one AD conversion other than the last AD conversion used for the signal level is less than the amplitude of the ramp signal of the last AD conversion used for the signal level. The count value is increased incrementally with each clock cycle until the amplitude of the ramp signal reaches the amplitude of the analog signal. If the amplitude of the ramp signal, which is a portion of the AD conversion used for the signal level, does not reach the amplitude of the analog signal, a multiplier factor for the increment is selected to obtain a count value, which corresponds to the number of AD conversions for the signal level that is the same as the number of AD conversions for the reset level.

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