Time-to-digital converter, analog-to-digital converter, and electronic device

Abstract

The present invention improves performance in a TDC including a circuit for detecting edges.　This time-to-digital converter is provided with a predetermined number of phase comparators and a predetermined number of edge detection units. Each of the phase comparators compares the respective phases of a pair of input signals having different edge phases, and outputs a comparison result. Each of the edge detection units comprises a first leading edge detection unit that detects an edge of one having a leading phase out of a pair of input signals, and a first lagging edge detection unit that detects an edge of one having a lagging phase out of the pair of input signals by a circuit symmetrical to the first leading edge detection unit.

Description

Time-to-digital converter, analog-to-digital converter, and electronic device 【0001】 This technology relates to time-to-digital converters. More specifically, it relates to time-to-digital converters, analog-to-digital converters, and electronic devices that detect edges. 【0002】 Conventionally, Time-to-Digital Converters (TDCs) have been used in Analog-to-Digital Converters (ADCs) and other devices to convert time into digital signals. For example, a TDC has been proposed in which an edge detection circuit is provided at each stage to detect the earlier and later phase edges of a pair of input signals, delaying the earlier phase edge and halving the delay time of each stage compared to the previous stage (see, for example, Non-Patent Document 1). In this TDC, OR (logical disjunction) and AND (logical conjunction) circuits are arranged within the edge detection circuit. The OR circuit detects the earlier phase edge, and the AND circuit detects the later phase edge. The AND circuit is composed of, for example, a NAND (negative logical conjunction) gate and an inverter, and the OR circuit is composed of, for example, a NOR (negative logical disjunction) gate and an inverter. 【0003】 Amy Whitcombe, et al., C19-2 2022 IEEE VLSI Symposium on Technology and Circuits A 6.0mW 3.8GS / s 7b VTC / TDC-Assisted Interleaved SAR ADC with 13GHz ERBW, 2022 IEEE VLSI Symposium on Technology and Circuits. 【0004】In the conventional technology described above, the earlier-phase edge is detected and delayed at each stage, and the delay time of each stage is halved to achieve a high-speed sequential comparison TDC. However, in the above TDC, the circuit that detects the earlier-phase edge (NOR gate and inverter) and the circuit that detects the later-phase edge (NAND gate and inverter) are different. As a result, the difference in the delay of each gate fluctuates greatly depending on the phase difference of each edge of the pair of input signals, which leads to a problem in that the linearity characteristics of the TDC deteriorate and performance decreases. 【0005】 This technology was developed in light of these circumstances and aims to improve performance in TDCs that include edge detection circuits. 【0006】 This technology was developed to solve the aforementioned problems, and its first aspect is a time-digital converter comprising a predetermined number of phase comparators that compare the phases of a pair of input signals with different edge phases and output the comparison result, and a predetermined number of edge detection units, each of which has a first leading edge detection unit that detects the leading edge of the pair of input signals, and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit. This results in improved linearity characteristics. 【0007】 Furthermore, in this first aspect, the edge detection unit may further include a first output inverter that inverts and outputs the first inverted signal, and a second output inverter that inverts and outputs the second inverted signal, wherein the first leading edge detection unit generates the first inverted signal and outputs it to the first output inverter, and the first lagging edge detection unit generates the second inverted signal and outputs it to the second output inverter. This results in the inverted signal being output from the edge detection unit. 【0008】Furthermore, in this first aspect, the edges of the pair of input signals are rising edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as the first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the power node of the first leading inverter, and a third leading inverter that inverts the power supply voltage signal and supplies it to the ground node of the first leading inverter. The first lagging edge detection unit may also comprise a first lagging inverter that inverts the other signal and outputs it as the second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the ground node of the first lagging inverter, and a third lagging inverter that inverts the ground voltage signal and supplies it to the power node of the first lagging inverter. This results in a smaller difference between the delay time of the leading edge and the delay time of the lagging edge. 【0009】 Furthermore, in this first aspect, the edges of the pair of input signals are falling edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as the first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the ground node of the first leading inverter, and a third leading inverter that inverts the ground voltage signal and supplies it to the power node of the first leading inverter. The first lagging edge detection unit may also comprise a first lagging inverter that inverts the other signal and outputs it as the second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the power node of the first lagging inverter, and a third lagging inverter that inverts the power supply voltage signal and supplies it to the ground node of the first lagging inverter. This results in the edge detection unit detecting falling edges. 【0010】Furthermore, in this first aspect, the edge detection unit may further comprise a second leading edge detection unit, and the first and second leading edge detection units may be connected in parallel to the first output inverter. This results in improved linearity. 【0011】 Furthermore, in this first aspect, the edge detection unit may further comprise a second delayed edge detection unit, and the first and second delayed edge detection units may be connected in parallel to the second output inverter. This results in improved linearity by aligning the input and output loads. 【0012】 Furthermore, in this first aspect, the edge detection unit may further comprise a second leading edge detection unit, and the edge detection unit may further comprise a second lagging edge detection unit, and the first and second leading edge detection units may be connected in parallel to the first output inverter, and the first and second lagging edge detection units may be connected in parallel to the second output inverter. This results in improved linearity. 【0013】 Furthermore, in this first aspect, the first leading edge detection unit includes a first leading inverter that inverts one of the pair of input signals and outputs it as the first inverted signal, the second leading edge detection unit includes a fourth leading inverter that inverts the other of the pair of input signals and outputs it as the first inverted signal, the first lagging edge detection unit includes a first lagging inverter that inverts the other signal and outputs it as the second inverted signal, the second lagging edge detection unit includes a fourth lagging inverter that inverts one of the signals and outputs it as the second inverted signal, the ground node of the first leading inverter and the ground node of the fourth leading inverter may be short-circuited, and the power supply node of the first lagging inverter and the power supply node of the fourth lagging inverter may be short-circuited. This has the effect of reducing the difference in driving force between leading edge detection and lagging edge detection. 【0014】Furthermore, in this first aspect, the above-mentioned time-to-digital converter may be a SAR (Successive Approximation Register)-TDC. This has the effect of reducing the circuit size compared to a flash TDC. 【0015】 Furthermore, in this first aspect, the system may further include a flash TDC, and the edge detection unit may output a pair of detection signals to the flash TDC. This results in a reduction in circuit size and conversion time. 【0016】 Furthermore, the second aspect of this technology is a time-to-digital converter comprising a downstream TDC and an edge detection unit that detects the leading edge and the lagging edge of a pair of input signals with different edge phases, and outputs a pair of detection signals to the downstream TDC. This results in a reduction in circuit size and conversion time. 【0017】 Furthermore, in this second aspect, the subsequent TDC may be a flash TDC. This has the effect of reducing the circuit size and conversion time of the flash TDC compared to the case without an edge detection unit. 【0018】 Furthermore, in this second aspect, the subsequent TDC may be a vernier-type flash TDC. This results in the effect of equalizing the driving force in the delay stage on both the lag and lead sides. 【0019】 Furthermore, in this second aspect, the subsequent TDC may be a classic-type flash TDC. This results in a reduction in the number of delay elements compared to the vernier type. 【0020】 Furthermore, in this second aspect, the subsequent TDC may be a ring-type TDC. This has the effect of reducing the circuit size and conversion time of the ring-type TDC compared to the case without an edge detection unit. 【0021】Furthermore, a third aspect of this technology is an analog-to-digital converter comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output the comparison result; and a predetermined number of edge detection units, each of which is provided with a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection circuit. This results in an improvement in the linearity characteristics of the analog-to-digital converter. 【0022】 Furthermore, in this third aspect, the SARADC may be further provided, which converts the differential signal into a digital signal using a successive comparison algorithm and inputs the residual voltage to the voltage-time converter as the input voltage. This results in a wider dynamic range and improved conversion accuracy. 【0023】 Furthermore, a third aspect of this technology is an electronic device comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output bits indicating the comparison result; a predetermined number of edge detection units, each provided with a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit; and a processing unit that processes the digital signal including the bits. This results in an improvement in the linearity characteristics of the circuit within the electronic device. 【0024】This is a block diagram showing an example configuration of an electronic device in the first embodiment of this technology. This is a block diagram showing an example configuration of a TDC in the first embodiment of this technology. This is a diagram showing an example of the operation of a phase comparator in the first embodiment of this technology. This is a circuit diagram showing an example configuration of an edge detection unit in the first embodiment of this technology. This is a circuit diagram showing an example configuration of an edge detection unit with a reduced inverter in the first embodiment of this technology. This is a timing chart showing an example of the operation of a TDC in the first embodiment of this technology. This is a graph showing the lead-lag delay difference characteristics of the circuit of Non-Patent Literature 1. This is a graph showing the output code characteristics of the circuit of Non-Patent Literature 1. This is a circuit diagram showing an example configuration of an edge detection unit in the first modified example of the first embodiment of this technology. This is a graph showing the lead-lag delay difference characteristics of Non-Patent Literature 1 and the first modified example of the first embodiment, respectively. This is a graph showing the linearity characteristics of Non-Patent Literature 1 and the first modified example of the first embodiment, respectively. This is a circuit diagram showing an example configuration of an edge detection unit with a reduced lead circuit in the first modified example of the first embodiment of this technology. This is a circuit diagram showing an example configuration of an edge detection unit with a reduced delay circuit in a first modification of the first embodiment of this technology. This is a circuit diagram showing an example configuration of an edge detection unit in a second modification of the first embodiment of this technology. This is a circuit diagram showing an example configuration of an edge detection unit in a third modification of the first embodiment of this technology. This is a block diagram showing an example configuration of a hybrid ADC (Analog to Digital Converter) in a fourth modification of the first embodiment of this technology. This is a circuit diagram showing an example configuration of a SARADC in a fourth modification of the first embodiment of this technology. This is a circuit diagram showing an example configuration of a DAC (Digital to Analog Converter) in a fourth modification of the first embodiment of this technology. This is a block diagram showing an example configuration of a TDC in a second embodiment of this technology. This is a circuit diagram showing an example configuration of a delay circuit in a second embodiment of this technology. This is a block diagram showing an example configuration of a TDC in a comparative example. This is a diagram showing the results of comparing the characteristics of the comparative example and the second embodiment of this technology. This is a diagram showing specific examples of the circuit scales of the comparative example and the second embodiment of this technology.This is a circuit diagram showing an example configuration of a delay circuit in the first modification of the second embodiment of this technology. This is a block diagram showing an example configuration of a TDC in the second modification of the second embodiment of this technology. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit. 【0025】 The following describes the embodiments for implementing this technology. The description will proceed in the following order: 1. First Embodiment (Example of detecting leading and lagging edges with a symmetrical circuit) 2. Second Embodiment (Example of detecting leading and lagging edges and providing a flash TDC) 3. Application to a Mobile Device 【0026】 <1. First Embodiment> [Example of Communication System Configuration] Figure 1 is a block diagram showing an example configuration of an electronic device 100 in an embodiment of the present technology. This electronic device 100 includes CIS (CMOS Image Sensors) 111, DAC 112, transmitter 113, receiver 114, ADC 120, and processor 115. A smartphone or personal computer is envisioned as the electronic device 100. 【0027】 The CIS 111 captures image data. The CIS 111 generates a digital signal representing the captured image data and supplies it to the DAC 112. The DAC 112 converts the digital signal into an analog signal and supplies it to the transmitter 113. The transmitter 113 converts the analog signal into a PAM (Pulse-Amplitude Modulation) 4 signal and transmits it to the receiver 114. 【0028】 The receiver 114 receives the PAM4 signal, converts it into an analog differential signal, and supplies it to the ADC 120. This differential signal includes the positive side signal Vin_p and the negative side signal Vin_n. 【0029】 The ADC 120 converts the voltage difference between the positive signal Vin_p and the negative signal Vin_n into a digital signal code Dout and supplies it to the processor 115. The processor 115 processes the code Dout. 【0030】 Also, the ADC120 includes a VTC (Voltage-to-Time Converter) 121 and a TDC200. The VTC121 converts the voltage difference between the positive-side signal Vin_p and the negative-side signal Vin_n into input signals Vin_A and Vin_B representing a time corresponding to the voltage difference. These input signals Vin_A and Vin_B are signals with different edge phases from each other, and the phase difference between their edges is set to a value corresponding to the voltage difference. The edge is, for example, a rising edge. The edge of the input signal Vin_A may lead or lag the edge of the input signal Vin_B. 【0031】 The TDC200 converts the phase difference between the edges of the input signals Vin_A and Vin_B into the code Dout. 【0032】 As illustrated in the figure, by combining the TDC200 with the VTC121, an ADC corresponding corresponding high to high-speed signals such as PAM4 signals can be realized. 【0033】 Although the TDC200 is provided inside the ADC120, it is not limited to this configuration. The TDC200 can also be provided in a circuit other than the ADC, such as a digital PLL (Phase Locked Loop). 【0034】 [Configuration Example of TDC] FIG. 2 is a block diagram showing a configuration example of the TDC200 in the first embodiment of the present technology. This TDC200 includes, for example, phase comparators 211 to 214, delay circuits 221, 222, and 223, and edge detectors 301, 302, and 303. 【0035】 The figure illustrates a circuit when the code Dout is 4 bits. When the code Dout is N (N is an integer) bits, N phase comparators, N - 1 delay circuits, and N - 1 edge detectors are provided. 【0036】The phase comparator 211 and the edge detection unit 301 receive input signals Vin_A and Vin_B from the VTC 121. The phase comparator 211 compares the phases of the respective edges of the input signals Vin_A and Vin_B. The phase comparator 211 outputs a bit indicating the comparison result as CMP[3] to the processor 115. This CMP[3] corresponds to the MSB (Most Significant Bit) of the 4-bit code Dout. For example, an RS flip-flop is used as the phase comparator 211. 【0037】 The edge detection unit 301 detects the leading edge and the lagging edge of the input signals Vin_A and Vin_B, and outputs detection signals DET_E1 and DET_L1 indicating the detection results. Detection signal DET_E1 indicates the timing of the leading edge, and detection signal DET_L1 indicates the timing of the lagging edge. 【0038】 The delay circuit 221 delays the detection signal DET_E1, which is in phase lead, for a delay time of 4T, where T is a predetermined unit time. The delay circuit 221 outputs the delayed signal as the delayed signal DET_E1' to the phase comparator 212 and the edge detection unit 302. 【0039】 The phase comparator 212 compares the phases of the edges of the detection signal DET_L1 and the delay signal DET_E1'. The phase comparator 212 outputs a bit indicating the comparison result as CMP[2] to the processor 115. 【0040】 The edge detection unit 302 detects the leading edge and the lagging edge from the delayed signal DET_E1' and the detection signal DET_L1, and outputs detection signals DET_E2 and DET_L2 indicating the detection results. The detection signal DET_E2 indicates the timing of the leading edge, and the detection signal DET_L2 indicates the timing of the lagging edge. 【0041】The delay circuit 222 delays the detection signal DET_E2 over a delay time of 2T. The delay circuit 222 outputs the delayed signal as the delayed signal DET_E2' to the phase comparator 213 and the edge detection unit 303. 【0042】 The phase comparator 213 compares the phases of the edges of the detection signal DET_L2 and the delay signal DET_E2'. The phase comparator 213 outputs a bit indicating the comparison result as CMP[1] to the processor 115. 【0043】 The edge detection unit 303 detects the leading edge and the lagging edge from the delayed signal DET_E2' and the detection signal DET_L2, and outputs detection signals DET_E3 and DET_L3 indicating the detection results. The detection signal DET_E3 indicates the timing of the leading edge, and the detection signal DET_L3 indicates the timing of the lagging edge. 【0044】 The delay circuit 223 delays the detection signal DET_E3 over a delay time T. The delay circuit 223 outputs the delayed signal as the delayed signal DET_E3' to the phase comparator 214. 【0045】 The phase comparator 214 compares the phases of the edges of the detection signal DET_L3 and the delay signal DET_E3'. The phase comparator 214 outputs a bit indicating the comparison result as CMP[0] to the processor 115. 【0046】 As illustrated in the figure, the delay time for each stage is set to half the time of the previous stage. The edge detection unit detects the phase leading, the delay circuit delays the detected signal by half the delay time of the previous stage, and the phase comparator compares the phases. By repeating this process, the TDC200 can obtain an N-bit code Dout corresponding to the time difference in N binary searches. A TDC that performs this type of processing is called a SAR-TDC. 【0047】Figure 3 shows an example of the operation of the phase comparator 211 in the first embodiment of this technology. This phase comparator 211 includes a set terminal S, a reset terminal R, and an output terminal Q. A pair of input signals to be compared in phase are input to the set terminal S and the reset terminal R. The configuration of the second and subsequent phase comparators 212, 213, and 214 is the same as that of the first-stage phase comparator 211. 【0048】 If both the set terminal S and the reset terminal R have a logical value of "0", the output value from the output terminal Q will remain unchanged from the previous value. If the set terminal S has a logical value of "0" and the reset terminal R has a logical value of "1", the output value will be a logical value of "0". If the set terminal S has a logical value of "1" and the reset terminal R has a logical value of "0", the output value will be a logical value of "1". If both the set terminal S and the reset terminal R have a logical value of "1", the output value will be a logical value of "1". 【0049】 [Example of Edge Detection Unit Configuration] Figure 4 is a block diagram showing an example configuration of the edge detection unit 301 in the first embodiment of this technology. This edge detection unit 301 comprises a leading edge detection unit 310, a lagging edge detection unit 320, and inverters 350 and 360. The leading edge detection unit 310 comprises inverters 311, 312 and 313, and the lagging edge detection unit 320 comprises inverters 321, 322 and 323. The circuit configuration of the second and subsequent edge detection units 302 and 303 is the same as that of the first stage edge detection unit 301. 【0050】Inverter 360 is a CMOS (Complementary MOS) inverter. This inverter 360 includes a pMOS (p-channel Metal Oxide Semiconductor) transistor 355 and an nMOS (n-channel MOS) transistor 356. These transistors are connected in series between the power node 351 and the ground node 352, with the pMOS transistor 355 on the power supply side. Signals from the preceding stage are input to the gates of the pMOS transistor 355 and the nMOS transistor 356. Inverted signals are output from the connection nodes of the pMOS transistor 355 and the nMOS transistor 356. The circuit configuration of the inverters other than inverter 360 is the same as that of inverter 360. 【0051】 Inverter 311 inverts the input signal Vin_B and outputs the inverted signal to inverter 350. 【0052】 Inverter 312 inverts the input signal Vin_A and outputs it to the power supply node of inverter 311. 【0053】 The inverter 313 inverts the power supply voltage signal and outputs it to the ground node of the inverter 311. 【0054】 Inverters 311, 312, and 313 are examples of the first, second, and third leading inverters described in the claims. 【0055】 Inverter 321 inverts the input signal Vin_A and outputs the inverted signal to inverter 360. 【0056】 Inverter 322 inverts the input signal Vin_B and outputs it to the ground node of inverter 321. 【0057】 Inverter 323 inverts the ground voltage signal and outputs it to the power node of inverter 321. 【0058】 Inverters 321, 322, and 323 are examples of the first, second, and third lagging inverters described in the claims. 【0059】 The inverter 350 inverts the inversion signal from the inverter 311 and outputs it to the delay circuit 221 as a detection signal DET_E1. 【0060】 The inverter 360 inverts the inversion signal from the inverter 321 and outputs it as a detection signal DET_L1 to the edge detection unit 302 and the like. 【0061】 Inverters 350 and 360 are examples of the first and second output inverters described in the claims. 【0062】 The edges of input signals Vin_A and Vin_B are assumed to be rising edges. With the circuit configuration illustrated in the figure, the leading edge detection unit 310 detects the leading edge of input signals Vin_A and Vin_B. The lagging edge detection unit 320 detects the lagging edge using a circuit symmetric to that of the leading edge detection unit 310. Here, a symmetrical circuit means a circuit in which the inverters connected to the power terminals and ground terminals of inverters 311 and 321 are inverted in terms of their connection relationship. The leading edge detection unit 310 is an example of the first leading edge detection unit described in the claims, and the lagging edge detection unit 320 is an example of the first lagging edge detection unit described in the claims. 【0063】 Furthermore, the difference between the delay time of the leading edge detected by the leading edge detection unit 310 and inverter 350, and the delay time of the lagging edge detected by the lagging edge detection unit 320 and inverter 360, is referred to as the "leading-lagging delay difference". 【0064】 In parallel with the edge detection unit 301, the phase comparator 211 compares the phases of the respective edges of the input signals Vin_A and Vin_B and outputs a bit CMP [3] indicating the comparison result. 【0065】 Furthermore, as illustrated in Figure 5, inverters 313 and 323 can also be reduced. However, if inverters 313 and 323 are reduced, there is a risk that a difference in driving force may occur between the leading and lagging sides. 【0066】[Example of TDC Operation] Figure 6 is a timing chart showing an example of the operation of the TDC 200 in the first embodiment of this technology. In the figure, a shows the operation of the first-stage phase comparator 211 and edge detection unit 301. In the figure, b shows the operation of the second-stage phase comparator 212 and edge detection unit 302. 【0067】 As illustrated in figure a, if the input signal Vin_A rises first at timing t0, the edge detection unit 301 detects that edge and outputs the detection signal DET_E1, which rises immediately afterward at timing t1. 【0068】 Then, when the input signal Vin_B rises with a delay at timing t2, the edge detection unit 301 detects the edge and outputs the detection signal DET_L1, which rises immediately afterward at timing t3. 【0069】 Furthermore, the phase comparator 211 compares the phases of the input signals Vin_A and Vin_B, and raises the CMP [3] that indicates the comparison result to a high level at timing t1 immediately following timing t0. 【0070】 As illustrated in figure b, assume that the detection signal DET_E1 is delayed over 4T, resulting in its edge phase being later than that of the undelayed detection signal DET_L1. 【0071】 If the detection signal DET_L1 rises first at timing t3, the edge detection unit 301 detects that edge and outputs the detection signal DET_E2, which rises immediately afterward at timing t4. 【0072】 Then, when the delayed signal DET_E1' rises with a delay at timing t5, the edge detection unit 301 detects that edge and outputs the detection signal DET_L2, which rises immediately afterward at timing t6. 【0073】 Furthermore, the phase comparator 211 compares the phases of the delayed signal DET_E1' and the detection signal DET_L1, and keeps CMP[2] at a low level at timing t4 immediately following timing t3. 【0074】In the figure, the difference between the advancing delay time from timing t0 to t1 and the lagging delay time from timing t2 to t3 corresponds to the advancing-lagging delay difference of the first stage. Similarly, in the figure, the difference between the advancing delay time from timing t3 to t4 and the lagging delay time from timing t5 to t6 corresponds to the advancing-lagging delay difference of the second stage. 【0075】 Figure 7 is a graph showing the lead-lag delay difference characteristics of the circuit described in Non-Patent Document 1. The vertical axis in this figure represents the lead-lag delay difference, which is the difference in gate delays between the NOR gate and the NAND gate. The horizontal axis in this figure represents the input time difference, which is the phase difference between the edges of a pair of input signals. 【0076】 As mentioned above, in the circuit of Non-Patent Document 1, the circuit that detects the earlier-phase edge (NOR gate) and the circuit that detects the later-phase edge (NAND gate) are different. Therefore, the lead-to-lagging delay difference fluctuates depending on the input time difference. For example, suppose that the input time difference is positive when input signal Vin_A is leading, and negative when input signal Vin_B is leading. As illustrated in the figure, in the circuit of Non-Patent Document 1, the lead-to-lagging delay difference becomes different depending on whether input signal Vin_A or Vin_B is leading. This characteristic degrades linearity. Linearity characteristics can be evaluated using DNL (Differential Non-Linearity) or INL (Integral Non-Linearity). 【0077】 Figure 8 is a graph showing the output code characteristics of the circuit described in Non-Patent Document 1. In this figure, the vertical axis represents the lower two bits of the output code, and the horizontal axis represents the input time difference Δt. ｉｎ This shows the output code characteristics described in Non-Patent Literature 1. The thick solid line represents the output code characteristics, and the thick dotted line represents the ideal output code characteristics. 【0078】 In the circuit described in Non-Patent Document 1, the lead-lag delay difference fluctuates as described above. Therefore, if the minimum delay time T is 10 picoseconds (ps), the delay difference corresponding to the LSB (Least Significant Bit) of the code is the input time difference Δt.ｉｎ This causes it to vary in the range of -12 picoseconds to +11 picoseconds. The average value at this time is T ｍｅａｎ Therefore, in the ideal case, the input time difference Δt is as illustrated by the thick dotted line. ｉｎ ga T ｍｅａｎ The code transitions at this point. However, in the circuit of Non-Patent Document 1, as illustrated by the thick solid line, the interval in which the lower two bits of the output code are "01" is long, and the interval in which they are "10" is short. As a result, the DNL degrades, and furthermore, the INL, which is the integral of the DNL, ​​also degrades. 【0079】 In contrast, in the circuit illustrated in Figure 4, the leading edge detection unit 310 and the lagging edge detection unit 320 are symmetrical circuits, thus suppressing fluctuations in the leading-lagging delay difference. For example, when the input signal Vin_A is leading, or when the input signal Vin_B is leading, the delay difference approaches a similar value. Therefore, in the circuit of Figure 4, compared to the circuit described in Non-Patent Document 1, the output code characteristics approach ideal characteristics, and linearity characteristics such as DNL and INL can be improved. 【0080】 Thus, according to the first embodiment of this technology, the symmetrical leading edge detection unit 310 and lagging edge detection unit 320 detect the leading edge and the lagging edge, thereby suppressing fluctuations in the leading-lagging delay difference and improving linearity characteristics. 【0081】 [First Modification] In the first embodiment described above, the leading edge detection unit 310 and the lagging edge detection unit 320 were arranged within the edge detection unit 301, but it is preferable to equalize the input / output load on the leading side and the lagging side. The TDC200 in this first modification of the first embodiment differs from the first embodiment in that the input / output load is equalized. 【0082】 Figure 9 is a circuit diagram showing one example configuration of the edge detection unit 301 in a first modified example of the first embodiment of the present technology. The circuit configuration of the second and subsequent edge detection units is the same as that of the first stage edge detection unit 301. 【0083】The edge detection unit 301 in the first modification of the first embodiment differs from the first embodiment in that it further comprises a leading edge detection unit 330 and a lagging edge detection unit 340. The leading edge detection unit 330 comprises inverters 331, 332, and 332. The lagging edge detection unit 340 comprises inverters 341, 342, and 343. 【0084】 Inverter 331 inverts the input signal Vin_A and outputs the inverted signal to inverter 350. 【0085】 Inverter 332 inverts the input signal Vin_B and outputs it to the power supply node of inverter 331. 【0086】 Inverter 333 inverts the power supply voltage signal and outputs it to the ground node of inverter 331. 【0087】 Inverter 341 inverts the input signal Vin_B and outputs the inverted signal to inverter 360. 【0088】 Inverter 342 inverts the input signal Vin_A and outputs it to the ground node of inverter 341. 【0089】 Inverter 343 inverts the ground voltage signal and outputs it to the power node of inverter 341. 【0090】 As described above, the leading edge detection units 310 and 330 are connected in parallel to the inverter 350, and the lagging edge detection units 320 and 340 are connected in parallel to the inverter 360. By adding the leading edge detection units 330 and the lagging edge detection units 340, the input and output loads can be matched on the leading and lagging sides, resulting in improved linearity. 【0091】 Note that the leading edge detection units 310 and 330 are examples of the first and second leading edge detection units described in the claims. The lagging edge detection units 320 and 340 are examples of the first and second lagging edge detection units described in the claims. 【0092】Figure 10 is a graph showing the lead-lag delay difference characteristics of Non-Patent Document 1 and the first modified example of the first embodiment. In this figure, the vertical axis represents the lead-lag delay difference, and the horizontal axis represents the input time difference. The black circles represent the plot of the circuit in Non-Patent Document 1, and the white circles represent the plot of the circuit in the first modified example of the first embodiment. 【0093】 As illustrated in the figure, in the circuit of Non-Patent Document 1, the lead-to-delay difference differs depending on whether the input time difference is positive (i.e., input signal Vin_A is leading) or negative (i.e., input signal Vin_B is leading). On the other hand, in the circuit of the second modification of the first embodiment, the lead-to-delay difference is approximately the same whether input signal Vin_A is leading or input signal Vin_B is leading. 【0094】 Figure 11 is a graph showing the linearity characteristics of Non-Patent Document 1 and the first modified example of the first embodiment. In the figure, the horizontal axes of a and b show the code values ​​converted to decimal numbers, and the vertical axis shows DNL. In the figure, the horizontal axes of c and d show the code values ​​converted to decimal numbers, and the vertical axis shows INL. 【0095】 In the figure, 'a' shows the DNL characteristics of Non-Patent Document 1, and 'b' shows the DNL characteristics of the first modification of the first embodiment. As illustrated in 'a' and 'b' of the figure, the DNL of each code in the first modification of the first embodiment is smaller than that of Non-Patent Document 1. 【0096】 In the figure, c shows the INL characteristics of Non-Patent Document 1, and d shows the INL characteristics of the first modified example of the first embodiment. As illustrated in c and d of the figure, the INL values ​​of each code in the second modified example of the first embodiment are smaller than those in Non-Patent Document 1. 【0097】 As illustrated in Figure 10, in the first modified example of the first embodiment, the linearity characteristics are improved, as illustrated in Figure 11, because the variation in the lead-lag delay difference is smaller compared to Non-Patent Document 1. 【0098】Furthermore, as illustrated in Figure 12, the leading edge detection unit 310 can be reduced. 【0099】 Furthermore, as illustrated in Figure 13, the delayed edge detection unit 320 can also be reduced. 【0100】 However, it should be noted that while the circuit illustrated in Figure 12 shows improved linearity characteristics compared to the circuit described in Non-Patent Document 1, its linearity characteristics are worse compared to the circuit illustrated in Figure 9. 【0101】 Thus, according to the first modification of the first embodiment of this technology, by adding a leading edge detection unit 330 and a lagging edge detection unit 340, the input and output loads can be made equal on both the lagging and leading sides, thereby improving linearity. 【0102】 [Second Modification] In the first modification of the above-described embodiment, a leading edge detection unit 330 and a lagging edge detection unit 340 were added, but parasitic capacitance may occur at the output nodes of inverter 322 and 342. When detecting rising edges, these nodes are initially at the same voltage as the power supply voltage. Under such conditions, the detection time on the lagging edge detection side becomes longer compared to the leading edge detection side, and the leading-lagging edge time difference becomes particularly large when the input time difference is near zero. If the parasitic capacitance of the output nodes of inverter 322 and 342 is large, the leading-lagging edge time difference will increase as described above, which may worsen the linearity characteristics. The TDC 200 in this second modification of the first embodiment differs from the first modification of the first embodiment in that nodes at the same potential are short-circuited. 【0103】 Figure 14 is a circuit diagram showing one example configuration of the edge detection unit 301 in a second modification of the first embodiment of this technology. The circuit configuration of the second and subsequent edge detection units is the same as that of the first stage edge detection unit 301. 【0104】In the second modification of the first embodiment, the power supply nodes of inverters 321 and 341, i.e., the output nodes of inverters 323 and 343, are short-circuited. This increases the driving force of inverters 322 and 342, thereby reducing the difference in driving force near an input time difference of zero. However, as the driving force of inverters 322 and 342 increases, the leading-lagging edge time difference becomes larger in regions other than near an input time difference of zero. For this reason, the grounding nodes of inverters 311 and 331, i.e., the output nodes of inverters 313 and 333, are also short-circuited. This reduces the difference in driving force even when the input time difference is not near zero. As a result, deterioration of linearity characteristics caused by parasitic capacitance can be suppressed. 【0105】 Inverters 311 and 331 are examples of the first and fourth leading inverters described in the claims. Inverters 321 and 341 are examples of the first and fourth lagging inverters described in the claims. 【0106】 Thus, according to the second modification of the first embodiment of this technology, the grounding node and power supply node of the inverter are short-circuited, thereby suppressing the deterioration of linearity characteristics caused by parasitic capacitance. 【0107】 [Third Modification] In the first embodiment described above, the edge detection unit 301 detected rising edges, but it is also possible to detect falling edges instead of rising edges. The TDC200 in this third modification of the first embodiment differs from the first embodiment in that the edge detection unit 301 detects falling edges. 【0108】 Figure 15 is a circuit diagram showing one example configuration of the edge detection unit 301 in a third modified example of the first embodiment of this technology. The circuit configuration of the second and subsequent edge detection units is the same as that of the first edge detection unit 301. 【0109】 In the third modification of the first embodiment, the edges of the input signals Vin_A and Vin_B are falling edges. 【0110】 Furthermore, inverter 311 inverts the input signal Vin_A, not Vin_B, and outputs the inverted signal to inverter 350. Inverter 312 inverts the input signal Vin_B, not Vin_A, and outputs it to the ground node of inverter 311. Inverter 313 inverts the ground voltage signal, not the power supply voltage, and outputs it to the power supply node of inverter 311. 【0111】 Furthermore, inverter 321 inverts the input signal Vin_B, not the input signal Vin_A, and outputs the inverted signal to inverter 360. Inverter 322 inverts the input signal Vin_A, not the input signal Vin_B, and outputs it to the power node of inverter 321. Inverter 323 inverts the power supply voltage signal, not the ground voltage, and outputs it to the power node of inverter 321. 【0112】 As illustrated in the figure, by reversing the lag circuit and the lead circuit compared to the first embodiment, the edge detection unit 301 can detect falling edges. 【0113】 Furthermore, inverters 313 and 323 can be reduced in number. Also, in the first and second modifications of the first embodiment, the falling edge can be detected by reversing the lag circuit and the lead circuit. 【0114】 Thus, according to the third modification of the first embodiment of this technology, the lag circuit and the lead circuit are reversed, so the edge detection unit 301 can detect falling edges. 【0115】 [Fourth Modification] In the first embodiment described above, the ADC120 was realized by the VTC121 and TDC200, but in this configuration, the dynamic range of the ADC120 may be insufficient. The TDC200 in this fourth modification of the first embodiment differs from the first embodiment in that the VTC121 and TDC200 are combined with SARADC400. 【0116】Figure 16 is a block diagram showing an example configuration of a hybrid ADC 130 in a fourth modification of the first embodiment of the present technology. In the fourth modification of the first embodiment, a hybrid ADC 130 is used instead of an ADC 120 which consists only of a VTC 121 and a TDC 200. This hybrid ADC 130 comprises a SARADC 400, a VTC 121, a TDC 200, and an encoder 131. 【0117】 The SARADC400 receives a differential signal consisting of a positive signal Vin_p and a negative signal Vin_n from the receiver 114. The SARADC400 converts the differential signal into an M (where M is an integer) bit code Dout_U using a successive comparison algorithm and outputs it to the encoder 131. This code Dout_U is used as the upper bit sequence of the final code Dout. 【0118】 The SARADC400 then inputs the positive signal Vin_p' and the negative signal Vin_n', immediately after the AD conversion to M bits, to the VTC121. The voltage difference between the positive signal Vin_p' and the negative signal Vin_n' corresponds to the residual voltage remaining after the AD conversion. 【0119】 In the fourth modification of the first embodiment, the circuit configurations of VTC121 and TDC200 are the same as in the first embodiment. TDC200 supplies an N-bit digital signal as Dout_L to encoder 131. This code Dout_L is used as the lower bit sequence of the final code Dout. 【0120】 The encoder 131 generates a code Dout of (M+N) bits, with code Dout_U as the upper bit sequence and code Dout_L as the lower bit sequence, and outputs it to the processor 115. 【0121】As illustrated in the figure, the SARADC400 converts the differential signal to the higher bits, and the VTC121 and TDC200 convert the residual voltage to the lower bits. This configuration allows for a wider dynamic range compared to when only the VTC121 and TDC200 convert (M+N) bits. Furthermore, it allows for higher conversion accuracy compared to when only the SARADC400 converts the differential signal. 【0122】 Figure 17 is a circuit diagram showing one configuration example of SARADC400 in a fourth modification of the first embodiment of the present technology. This SARADC400 includes sampling switches 411 and 412, a DAC 420, a comparator 430, a SAR logic circuit 440, and output switches 451 and 452. 【0123】 Sampling switches 411 and 412 control a predetermined sampling clock CLK ＳＭＰ In sync with this, the positive signal Vin_p and the negative signal Vin_n are sampled and supplied to the DAC420. 【0124】 The DAC 420 increases or decreases the positive signal Vin_p and the negative signal Vin_n according to the positive control signal DACp and the negative control signal DACn from the SAR logic circuit 440. The DAC 420 outputs the differential signal after the increase or decrease as the positive signal Vin_p' and the negative signal Vin_n' to the comparator 430 and output switches 451 and 452. 【0125】 The comparator 430 compares the positive signal Vin_p' with the negative signal Vin_n'. The comparator 430 outputs the comparison result CMPa to the SAR logic circuit 440. 【0126】The SAR logic circuit 440 generates a positive control signal DACp and a negative control signal DACn based on the comparison result CMPa using a successive comparison algorithm and supplies them to the DAC 420. When the number of successive comparisons reaches M, the SAR logic circuit 440 outputs a signal consisting of M comparison result CMPa as code Dout_U to the encoder 131. Also, when the number of successive comparisons reaches M, the SAR logic circuit 440 controls the output switches 451 and 452 to a closed state. 【0127】 Output switches 451 and 452 open and close the path between the output terminal of the DAC 420 and the input terminal of the VTC 121, according to the control of the SAR logic circuit 440. Initially, output switches 451 and 452 are open. When output switches 451 and 452 are closed by the control of the SAR logic circuit 440, they output a positive signal Vin_p' and a negative signal Vin_n' indicating the residual voltage to the VTC 121. 【0128】 Figure 18 is a circuit diagram showing one configuration example of a DAC420 in a fourth modification of the first embodiment of the present technology. This DAC420 comprises M positive switches 421, M positive capacitors 422, M negative capacitors 423, and M negative switches 424. 【0129】 Furthermore, the positive control signal DACp is M bits, and the m-th bit (where m is an integer from 0 to M-1) from the beginning of the positive control signal DACp is input to the m-th positive switch 421. The negative control signal DACn is also M bits, and the m-th bit from the beginning of the negative control signal DACn is input to the m-th negative switch 424. 【0130】 The positive side capacitor 422 holds the positive side signal from the sampling switch 411. Each of the M positive side capacitors 422 has a different capacitance, and one end of the m-th positive side capacitor 422 is connected to the m-th positive side switch 421. The other ends of the M positive side capacitors 422 are commonly connected to the non-inverting input terminal (+) of the comparator 430. 【0131】The negative capacitor 423 holds the negative signal from the sampling switch 412. Each of the M negative capacitors 423 has a different capacitance, and one end of the m-th negative capacitor 423 is connected to the m-th negative switch 424. The other ends of the M negative capacitors 423 are commonly connected to the inverting input terminal (-) of the comparator 430. 【0132】 The positive switch 421 supplies either the reference voltage Vref or the ground voltage to the corresponding positive capacitor 422 according to the corresponding bit of the positive control signal DACp. 【0133】 The negative switch 424 supplies either the reference voltage Vref or the ground voltage to the corresponding negative capacitor 423 according to the corresponding bit of the negative control signal DACn. 【0134】 Furthermore, the first, second, and third modifications of the first embodiment can be applied to the fourth modification of the first embodiment, respectively. 【0135】 Thus, according to the fourth modification of the first embodiment of this technology, the SARADC 400 converts the differential signal to the higher bits, and the VTC 121 and TDC 200 convert the residual voltage to the lower bits. As a result, the dynamic range can be widened and the conversion accuracy can be increased compared to the case where only the VTC 121 and TDC 200 are used, or the case where only the SARADC 400 is used. 【0136】 <2. Second Embodiment> In the first embodiment, an edge detection unit was provided at each stage of the successive comparison type TDC 200, but the configuration is not limited to this. The TDC 200 in this second embodiment differs from the first embodiment in that it has only an edge detection unit 301 at the first stage, and a flash TDC is provided at the subsequent stage. 【0137】FIG. 19 is a block diagram showing a configuration example of the TDC200 in the second embodiment of the present technology. The TDC200 in this second embodiment includes a phase comparator 211, an edge detection unit 301, and a flash TDC 230. The flash TDC 230 includes delay units 231, 232, and 233, and an encoder 239. The delay unit 231 includes a phase comparator 212 and a delay circuit 240-1. The delay unit 232 includes a phase comparator 213 and a delay circuit 240-2. The delay unit 233 includes a phase comparator 214 and a delay circuit 240-3. 【0138】 Note that the flash TDC 230 is an example of the latter-stage TDC described in the claims. 【0139】 The figure illustrates a circuit when the code Dout is 3 bits. When the code Dout is N bits, 2 Ｎ－１ - 1 delay units are provided. Since a delay circuit and a phase comparator are provided for each delay unit, the number of delay circuits is 2 Ｎ－１ - 1. Furthermore, since a phase comparator is arranged at the first stage, the number of phase comparators is 2 Ｎ－１ pieces. 【0140】 The first-stage phase comparator 211 outputs a bit indicating the comparison result to the encoder 239 as CMP[3]. The first-stage edge detection unit 301 outputs detection signals DET_L1 and DET_E1 to the delay unit 231. 【0141】 The second-stage phase comparator 212 compares the phases of the detection signals DET_L1 and DET_E1, and outputs a bit indicating the comparison result to the encoder 239 as CMP[2]. 【0142】 The second-stage delay circuit 240-1 delays both the detection signals DET_L1 and DET_E1. However, the delay time of DET_E1 is longer than the delay time of DET_L1. The delay circuit 240-1 outputs the delayed signals as delayed signals DET_L1' and DET_E1' to the delay unit 232. 【0143】The third-stage phase comparator 213 compares the phases of the delayed signals DET_L1' and DET_E1', and outputs a bit indicating the comparison result as CMP[1] to the encoder 239. 【0144】 The third stage delay circuit 240-2 delays both the delay signals DET_L1' and DET_E1'. However, the delay time of DET_E1' is longer than the delay time of DET_L1'. The delay circuit 240-2 outputs the delayed signals as delayed signals DET_L2' and DET_E2' to the delay unit 233. 【0145】 The final stage phase comparator 214 compares the phases of the delayed signals DET_L2' and DET_E2', and outputs a bit indicating the comparison result as CMP[0] to the encoder 239. 【0146】 The final stage delay circuit 240-3 delays both the delay signals DET_L2' and DET_E2'. However, the delay time of DET_E2' is longer than the delay time of DET_L2'. 【0147】 The pattern of the bit sequence from CMP[2] to CMP[0] starting from the second bit is 2 ２ As a result, encoder 239 can encode the bit sequence into 2 bits. Encoder 239 adds CMP[3] as the MSB to the encoded 2 bits and outputs it as a 3-bit code Dot. 【0148】 In the circuit configuration described above, the edge detection unit 301 can detect the leading and lagging edges of each signal. Therefore, the edges of the input signal Vin_A may lead or lag behind Vin_B. The MSB, CMP[3], is used as the sign bit, and for example, its sign is positive when the input signal Vin_A leads. 【0149】It is preferable to use a circuit consisting of an inverter as illustrated in Figure 9 as the first-stage edge detection unit 301. However, the circuit is not limited to that in Figure 9, as long as it can detect both phase-advancing edges and phase-lag edges. For example, as described in Non-Patent Document 1, an edge detection circuit including a NAND gate and a NOR gate can also be provided in the first stage. 【0150】 Figure 20 is a circuit diagram showing one example configuration of the delay circuit 240-1 in the second embodiment of this technology. The circuit configuration of the third stage and subsequent delay circuits is the same as that of the second stage delay circuit 240-1. 【0151】 The delay circuit 240-1 comprises inverters 241, 242, 243, 244, 245, and 246, and a NAND (negative OR) gate 247. 【0152】 Inverters 241, 242, 243, and 244 are connected in series. These inverters delay the detection signal DET_E1 from the edge detection unit 301 and output it to the delay unit 232 as DET_E1'. Inverter 242 also outputs the delayed signal to the NAND gate 247. 【0153】 Inverters 245 and 246 are connected in series. These inverters delay the detection signal DET_L1 from the edge detection unit 301 and output it to the delay unit 232 as DET_L1'. 【0154】 The NAND gate 247 outputs the negative OR of the signal from inverter 242 and the low-level signal TIEL. In a phase comparator using a NAND latch, the leading and lagging outputs are connected to the NAND gate. By connecting the NAND gate 247 to the leading side, the load between the outputs of all delay stages can be equalized. 【0155】 As illustrated in the figure, a flash TDC that delays both the leading and lagging signals by different delay times is called a vernier-type flash TDC. 【0156】While the inverter stage, which acts as the delay element, is set to four stages on the leading side and two stages on the lagging side, this configuration is not limited to this, as long as the delay time on the leading side is longer. Furthermore, a buffer can be used instead of an inverter as the delay element. 【0157】 Here, we consider a configuration in which the edge detection unit 301 is not included and only the flash TDC 230 is used as a comparative example. 【0158】 Figure 21 is a block diagram showing one configuration example of TDC200 in a comparative example. In the comparative example, only a flash TDC230 is placed inside TDC200. This flash TDC230 includes delay units 231 to 237 and an encoder 239. Input signals Vin_A and Vin_B are input to the first stage delay unit 231. The circuit configuration of each stage delay unit is the same as in the second embodiment. 【0159】 The diagram illustrates the circuit when CodeDout is 3 bits. When CodeDout is N bits, 2 Ｎ - One delay unit is provided. Since each delay unit is provided with a delay circuit and a phase comparator, the number of delay circuits and phase comparators is 2 each. Ｎ -1 item. 【0160】 Furthermore, it is assumed that the phase of the edge of input signal Vin_A leads that of Vin_B. If the phase of the edge of input signal Vin_A lags behind that of Vin_B, the code Dout will remain a fixed value regardless of the phase difference between those edges. 【0161】As illustrated in the figure, the comparative example lacks the edge detection unit 301. Therefore, the TDC200 can only perform time-to-digital conversion when the phase of the edge of the input signal Vin_A is ahead. In contrast, in the second embodiment, since the edge detection unit 301 is placed in the first stage, the edge of the input signal Vin_A may be ahead of or behind Vin_B, and the MSB can be used as the sign bit. If the code Dot is N bits, it is sufficient to provide a delay unit for N-1 bits excluding the sign bit, thus reducing the circuit size compared to the comparative example without a sign bit. This reduction in circuit size also reduces the conversion time when converting time to a digital signal. 【0162】 Furthermore, since the circuit of the second embodiment is a circuit in which only a phase comparator 211 and an edge detection unit 301 are added to the flash TDC 230, the impact of these additional circuits on the conversion time is small. 【0163】 Furthermore, since the edge detection unit 301 of the second embodiment is composed of an inverter, it has high compatibility with the characteristics of the flash TDC 230. 【0164】 Figure 22 shows a comparison of the characteristics of the comparative example and the second embodiment of the present technology. In this figure, Code Dot is set to N bits. 【0165】 In the comparison example using only flash TDC, 2 Ｎ - One delay circuit and 2 Ｎ - One phase comparator is required. Also, the conversion time of the comparative example is somewhat longer than that of the second embodiment, and the linearity characteristics are as good as those of the second embodiment. 【0166】 In the second embodiment, a flash TDC is provided after the edge detection unit, 2 Ｎ－１ - One delay circuit is required. Also, 2 Ｎ－１ A phase comparator is required. Furthermore, the conversion time in the second embodiment is shorter than that of the comparative example, and the linearity characteristics are good. 【0167】Figure 23 shows specific examples of the circuit sizes of the comparative example and the second embodiment of the present technology. In the figure, a shows the circuit size when Code Dot is 3 bits, and b shows the circuit size when Code Dot is 4 bits. 【0168】 As illustrated in figure a, when Code Dot is 3 bits, in the comparative example, the delay circuit is 7 (= 2 ３ -1) The number of phase comparators will be 7 (=2 ３ -1) There are 3 delay circuits (=2 ３－１ -1) The number of phase comparators becomes 4 (=2 ３－１ ) There will be ) 【0169】 As illustrated in figure b, when Code Dot is 4 bits, in the comparative example, the delay circuit is 15 (= 2 ４ -1) The number of phase comparators also becomes 15 (=2 ４ -1) There are 7 delay circuits (=2 ４－１ -1) The number of phase comparators becomes 8 (=2 ４－１ ) There will be ) 【0170】 As illustrated in the figure, the second embodiment allows for a reduction in circuit size compared to the comparative example. This reduction in circuit size also allows for a reduction in conversion time. 【0171】 Furthermore, the first, second, third, and fourth modifications of the first embodiment can be applied to the second embodiment. 【0172】 Thus, according to the second embodiment of this technology, since the edge detection unit 301 is provided before the flash TDC 230, the MSB can be used as the code bit. As a result, when the number of bits in the code is kept constant, the circuit size and conversion time can be reduced compared to the comparative example. 【0173】[First Modification] In the second embodiment described above, a vernier-type flash TDC 230 was used, but the flash TDC 230 is not limited to the vernier type. The TDC 200 in this first modification of the second embodiment differs from the second embodiment in that it delays only the leading signal within the flash TDC 230. 【0174】 Figure 24 is a circuit diagram showing one example configuration of the delay circuit 240-1 in the first modification of the second embodiment of this technology. The circuit configuration of the third stage and subsequent delay circuits is the same as that of the second stage delay circuit 240-1. 【0175】 The delay circuit 240-1 in the first modification of the second embodiment differs from the second embodiment in that inverters 243 to 246 and the NAND gate 247 are omitted. With the circuit configuration illustrated in the figure, only the leading signal is delayed. Such a flash TDC is called a classic flash TDC. Note that a buffer can also be used as the delay element instead of an inverter. 【0176】 Furthermore, the first, second, third, and fourth modifications of the first embodiment can be applied to the first modification of the second embodiment. 【0177】 Thus, according to the first modification of the second embodiment of this technology, since only the leading signal is delayed within the flash TDC 230, the number of delay elements (such as inverters) can be reduced. 【0178】 [Second Modification] In the second embodiment described above, a flash TDC was placed after the edge detection unit 301, but the configuration is not limited to this. The TDC 200 in this second modification of the second embodiment differs from the second embodiment in that a ring-type TDC is placed after the edge detection unit 301. 【0179】Figure 25 is a block diagram showing an example configuration of TDC200 in a second modification of the second embodiment of the present technology. The TDC200 in this second modification of the second embodiment differs from the second embodiment in that a ring-type TDC250 is arranged instead of a flash TDC230. The ring-type TDC250 is an example of a subsequent TDC as described in the claims. 【0180】 The first-stage phase comparator 211 outputs a bit indicating the phase comparison result of the input signals Vin_A and Vin_B as Q[3] to the encoder 259. 【0181】 The ring-type TDC250 comprises a NAND gate 251, buffers 253-1 and 253-2, flip-flops 252-1, 252-2 and 252-3, and an encoder 259. The delay time of each buffer is the same. 【0182】 The diagram illustrates the circuit when CodeDout is 3 bits. When CodeDout is N bits, 2 Ｎ－１ - Two buffers are provided. The number of flip-flops is 2 Ｎ－１ -1 item. 【0183】 The first-stage phase comparator 211 outputs a bit indicating the comparison result as Q[3] to the encoder 239. The first-stage edge detection unit 301 outputs a detection signal DET_L1 from flip-flops 252-1 to 252-3 and outputs DET_E1 to the NAND gate 251. 【0184】 The NAND gate 251 outputs a signal which is the negative logical AND of the leading detection signal DET_E1 from the edge detection unit 301 and the signal from buffer 253-2 to the input terminal D of the flip-flop 252-1 and to buffer 253-1. 【0185】 Buffer 253-1 delays the signal from NAND gate 251 and outputs it to input terminal D of flip-flop 252-2 and buffer 253-2. 【0186】The flip-flop 252-1 holds the signal from the NAND gate 251 in synchronization with the delayed detection signal DET_L1 from the edge detection unit 301 and outputs it to the encoder 259 as Q[2]. 【0187】 Buffer 253-2 delays the signal from buffer 253-1 and outputs it to input terminal D of flip-flop 252-3 and NAND gate 251. 【0188】 The flip-flop 252-2 holds the signal from buffer 253-1 in synchronization with the detection signal DET_L1 and outputs it to encoder 239 as Q[1]. 【0189】 The flip-flop 252-3 holds the signal from buffer 253-2 in synchronization with the detection signal DET_L1 and outputs it as Q[0] to encoder 239. 【0190】 The pattern of the bit sequence from Q[2] to Q[0] is 2 ２ As a result, the encoder 239 can encode those bit sequences into 2 bits. The encoder 239 adds Q[3] to the encoded 2 bits and outputs it as a 3-bit code Dot. 【0191】 If the edge detection unit 301 is omitted and only the ring-type TDC250 is used, and the code is N bits, then 2 Ｎ - 2 buffers and 2 Ｎ - One flip-flop is needed. 【0192】 As illustrated in the figure, by placing the edge detection unit 301 in front of the ring-type TDC 250, the MSB (i.e., Q[3]) can be used as the code bit. This reduces the circuit size and conversion speed compared to the case without the edge detection unit 301. 【0193】 Furthermore, instead of a buffer, an even-numbered inverter can be used as the delay element. In addition, various types of TDCs other than flash TDCs and ring-type TDCs can be placed after the edge detection unit 301. 【0194】Furthermore, the first, second, third, and fourth modifications of the first embodiment can be applied to the second modification of the second embodiment. 【0195】 Thus, according to the second modification of the second embodiment of this technology, by arranging the edge detection unit 301 in front of the ring-type TDC 250, the circuit size can be reduced compared to the case without the edge detection unit 301. 【0196】 <3. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots. 【0197】 Figure 26 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied. 【0198】 The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 26, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053. 【0199】 The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle. 【0200】The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc. 【0201】 The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing. 【0202】 The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light. 【0203】 The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041. 【0204】The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. 【0205】 Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040. 【0206】 Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams. 【0207】 The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 26, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display. 【0208】 Figure 27 shows an example of the installation position of the imaging unit 12031. 【0209】In Figure 27, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105. 【0210】 The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes. 【0211】 Figure 27 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained. 【0212】 At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection. 【0213】For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed. 【0214】 For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010. 【0215】At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position. 【0216】 The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, the circuit in the electronic device 100 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, the linearity characteristics of the ADC are improved, and a clearer image can be obtained, thereby reducing driver fatigue. 【0217】 The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. 【0218】 The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur. 【0219】Furthermore, this technology can also be configured as follows: (1) A predetermined number of phase comparators that compare the phases of a pair of input signals with different edge phases and output the comparison result, and a predetermined number of edge detection units, each comprising a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit. (2) The time digital converter according to (1), wherein the edge detection unit further comprises a first output inverter that inverts and outputs a first inverted signal, and a second output inverter that inverts and outputs a second inverted signal, the first leading edge detection unit generates the first inverted signal and outputs it to the first output inverter, and the first lagging edge detection unit generates the second inverted signal and outputs it to the second output inverter. (3) The edges of the pair of input signals are rising edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the power supply node of the first leading inverter, and a third leading inverter that inverts the power supply voltage signal and supplies it to the ground node of the first leading inverter, and the first lagging edge detection unit comprises a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the ground node of the first lagging inverter, and a third lagging inverter that inverts the ground voltage signal and supplies it to the power supply node of the first lagging inverter, as described in (2).(4) The edges of the pair of input signals are falling edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the ground node of the first leading inverter, and a third leading inverter that inverts the ground voltage signal and supplies it to the power node of the first leading inverter, and the first lagging edge detection unit comprises a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the power node of the first lagging inverter, and a third lagging inverter that inverts the power supply voltage signal and supplies it to the ground node of the first lagging inverter, as described in (2). (5) The time digital converter according to (2), wherein the edge detection unit further comprises a second leading edge detection unit, and the first and second leading edge detection units are connected in parallel to the first output inverter. (6) The time digital converter according to (2), wherein the edge detection unit further comprises a second lagging edge detection unit, and the first and second lagging edge detection units are connected in parallel to the second output inverter. (7) The time digital converter according to (2), wherein the edge detection unit further comprises a second leading edge detection unit, and the edge detection unit further comprises a second lagging edge detection unit, and the first and second leading edge detection units are connected in parallel to the first output inverter, and the first and second lagging edge detection units are connected in parallel to the second output inverter.(8) The time digital converter according to (7), wherein the first leading edge detection unit includes a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, the second leading edge detection unit includes a fourth leading inverter that inverts the other of the pair of input signals and outputs it as a first inverted signal, the first lagging edge detection unit includes a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, the second lagging edge detection unit includes a fourth lagging inverter that inverts one of the signals and outputs it as a second inverted signal, the ground node of the first leading inverter and the ground node of the fourth leading inverter are short-circuited, and the power supply node of the first lagging inverter and the power supply node of the fourth lagging inverter are short-circuited. (9) The time digital converter according to any one of (1) to (8), wherein the time digital converter is SAR-TDC. (10) The time digital converter according to (1), further comprising a flash TDC, wherein the edge detection unit outputs a pair of detection signals to the flash TDC. (11) A time digital converter comprising a downstream TDC and an edge detection unit that detects the leading edge and the lagging edge of a pair of input signals with different edge phases and outputs a pair of detection signals to the downstream TDC. (12) The time digital converter according to (11), wherein the downstream TDC is a flash TDC. (13) The time digital converter according to (12), wherein the downstream TDC is a vernier-type flash TDC. (14) The time digital converter according to (12), wherein the downstream TDC is a classic-type flash TDC. (15) The time digital converter according to (11), wherein the downstream TDC is a ring-type TDC.(16) An analog-to-digital converter comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output a comparison result; a predetermined number of edge detection units, each provided with a first leading edge detection unit that detects the leading edge of the pair of input signals; and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection circuit. (17) The analog-to-digital converter according to (16), further comprising a SARADC that converts a differential signal into a digital signal using a successive comparison algorithm and inputs the residual voltage to the voltage-time converter as the input voltage. (18) An electronic device comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output bits indicating the comparison result; a predetermined number of edge detection units, each provided with a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit; and a processing unit that processes a digital signal including the bits. 【0220】100 Electronic devices 111 CIS 112, 420 DAC 113 Transmitters 114 Receivers 115 Processors 120 ADCs 121 VTCs 130 Hybrid ADCs 131, 239, 259 Encoders 200 TDCs 211-217 Phase comparators 221, 222, 223, 240-1 to 240-7 Delay circuits 230 Flash TDCs 231, 232, 233 Delay units 241-246, 311-313, 321-323, 331-333, 341-343, 350, 360 Inverters 247, 251 NAND gates 250 Ring-type TDCs 252-1 to 252-3 Flip-flops 253-1, 253-2 Buffer 301, 302, 303 Edge detection unit 310, 330 Leading edge detection unit 320, 340 Lagging edge detection unit 355 pMOS transistor 356 nMOS transistor 400 SARADC 411, 412 Sampling switch 421 Positive switch 422 Positive capacitor 423 Negative capacitor 424 Negative switch 430 Comparator 440 SAR logic circuit 451, 452 Output switch 12031 Imaging unit

Claims

1. A time-digital converter comprising a predetermined number of phase comparators that compare the phases of a pair of input signals with different edge phases and output a comparison result, and a predetermined number of edge detection units, each of which includes a first leading edge detection unit that detects the leading edge of the pair of input signals, and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit.

2. The time digital converter according to claim 1, wherein the edge detection unit further comprises a first output inverter that inverts and outputs a first inverted signal, and a second output inverter that inverts and outputs a second inverted signal, the first leading edge detection unit generates the first inverted signal and outputs it to the first output inverter, and the first lagging edge detection unit generates the second inverted signal and outputs it to the second output inverter.

3. The pair of input signals have rising edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the power node of the first leading inverter, and a third leading inverter that inverts the power supply voltage signal and supplies it to the ground node of the first leading inverter, and the first lagging edge detection unit comprises a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the ground node of the first lagging inverter, and a third lagging inverter that inverts the ground voltage signal and supplies it to the power node of the first lagging inverter, as described in claim 2.

4. The pair of input signals have falling edges, and the first leading edge detection unit comprises a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, a second leading inverter that inverts the other of the pair of input signals and outputs it to the ground node of the first leading inverter, and a third leading inverter that inverts the ground voltage signal and supplies it to the power node of the first leading inverter, and the first lagging edge detection unit comprises a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, a second lagging inverter that inverts one of the signals and outputs it to the power node of the first lagging inverter, and a third lagging inverter that inverts the power supply voltage signal and supplies it to the ground node of the first lagging inverter, as described in claim 2.

5. The time digital converter according to claim 2, wherein the edge detection unit further comprises a second leading edge detection unit, and the first and second leading edge detection units are connected in parallel to the first output inverter.

6. The time digital converter according to claim 2, wherein the edge detection unit further comprises a second delayed edge detection unit, and the first and second delayed edge detection units are connected in parallel to the second output inverter.

7. The time digital converter according to claim 2, wherein the edge detection unit further comprises a second leading edge detection unit, the edge detection unit further comprises a second lagging edge detection unit, the first and second leading edge detection units are connected in parallel to the first output inverter, and the first and second lagging edge detection units are connected in parallel to the second output inverter.

8. The time digital converter according to claim 7, wherein the first leading edge detection unit includes a first leading inverter that inverts one of the pair of input signals and outputs it as a first inverted signal, the second leading edge detection unit includes a fourth leading inverter that inverts the other of the pair of input signals and outputs it as a first inverted signal, the first lagging edge detection unit includes a first lagging inverter that inverts the other signal and outputs it as a second inverted signal, the second lagging edge detection unit includes a fourth lagging inverter that inverts one of the signals and outputs it as a second inverted signal, the ground node of the first leading inverter and the ground node of the fourth leading inverter are short-circuited, and the power supply node of the first lagging inverter and the power supply node of the fourth lagging inverter are short-circuited.

9. The time-to-digital converter according to claim 1, wherein the time-to-digital converter is a SAR (Successive Approximation Register) - TDC (Time-to-Digital Converter).

10. The time digital converter according to claim 1, further comprising a flash TDC, wherein the edge detection unit outputs a pair of detection signals to the flash TDC.

11. A time-digital converter comprising a downstream TDC and an edge detection unit that detects the leading edge and the lagging edge of a pair of input signals with different edge phases and outputs a pair of detection signals to the downstream TDC.

12. The time-digital converter according to claim 11, wherein the subsequent TDC is a flash TDC.

13. The time digital converter according to claim 12, wherein the subsequent TDC is a vernier-type flash TDC.

14. The time-digital converter according to claim 12, wherein the subsequent TDC is a classic type flash TDC.

15. The time-digital converter according to claim 11, wherein the subsequent TDC is a ring-type TDC.

16. An analog-to-digital converter comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output a comparison result; and a predetermined number of edge detection units, each provided with a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection circuit.

17. The analog-to-digital converter according to claim 16, further comprising a SARADC (Successive Approximation Register ADC) that converts a differential signal into a digital signal using a successive comparison algorithm and inputs the residual voltage as the input voltage to the voltage-time converter.

18. An electronic device comprising: a voltage-time converter that converts an input voltage into a pair of input signals with different edge phases; a predetermined number of phase comparators that compare the phases of the pair of input signals and output bits indicating the comparison result; a predetermined number of edge detection units, each provided with a first leading edge detection unit that detects the leading edge of the pair of input signals and a first lagging edge detection unit that detects the lagging edge of the pair of input signals by a circuit symmetric to the first leading edge detection unit; and a processing unit that processes a digital signal including the bits.

Images