A voltage fluctuation suppressor for microgrid optimization dispatching

Abstract

The present application relates to a voltage fluctuation suppressor for microgrid optimization and scheduling, including an input amplifier circuit, a resonance processing circuit, and a signal adjustment output circuit. A voltage fluctuation suppressor for microgrid optimization and scheduling, first, its input amplifier circuit amplifies the collected voltage fluctuation signal input, which is convenient for the subsequent circuit processing. At the same time, it can obtain instantaneous power in the time domain analysis, making the time domain analysis simple, which is conducive to the design of the controller of the power regulator of the power electronic device. Secondly, the resonance processing circuit makes the PT less likely to be magnetically saturated, can suppress the overvoltage caused by the excitation of ferromagnetic resonance, can reduce the voltage fluctuation level of the submodule, and finally realize the lightweight of the MMC. Finally, the signal adjustment output circuit can accurately determine the time when the fault occurs by accurately detecting and identifying the resonant signal of the system. FFT decomposition can identify the resonance type, output the adjustment signal, and realize voltage fluctuation suppression.

Description

Technical Field

[0001] The present application relates to the field of microgrid optimization and electronic circuits, and in particular to a voltage fluctuation suppressor for microgrid optimization scheduling. Background Art

[0002] Microgrids can effectively solve the problem of connecting a large number of distributed generation to the grid, maximize the utilization of distributed energy, ensure the reliability of load power supply and the economy of grid operation, so it is extremely important to ensure the optimized operation of microgrids. Modular Multilevel Converter (MMC) has the advantages of modularity, low switching frequency, low harmonic content and easy redundant configuration, and has a wide range of application scenarios. MMC uses small capacitors distributed in each submodule to replace the centralized large capacitor in the two-level voltage source converter. Although this decentralized arrangement is easy to manufacture, it also increases the capacitor voltage fluctuation level of the submodule. Capacitor voltage fluctuations will interact with the interphase circulating current, increase converter losses, cause deviations in the output voltage on the AC side, increase the output harmonic content, and reduce the operational reliability of the DC system. The capacitor is the largest device in the MMC submodule, and its volume and weight account for more than 50% of the submodule and about one-third of the cost. In order to ensure that the submodule voltage fluctuation level meets the power supply quality requirements, a submodule capacitor with a sufficiently large threshold is required. Therefore, suppressing the submodule capacitor voltage of MMC is expected to reduce the demand for submodule capacitance value, thereby reducing the size and cost of the converter, which is conducive to the lightweight design of the converter. Since the submodule capacitor voltage fluctuation is closely related to the MMC bridge arm power, the research is mainly conducted from two perspectives: control scheme and topology scheme. The capacitor voltage fluctuation is suppressed by changing the physical quantities such as bridge arm current and bridge arm voltage. For the submodule MMC, the paper analyzes the relationship between the submodule capacitance value and the voltage fluctuation amplitude and the MMC submodule capacitor voltage fluctuation characteristics. From the perspective of topological structure, a topology using segmented bridge arm reactance submodule is proposed, and the corresponding control strategy is designed; from the perspective of control strategy, the submodule capacitor voltage fluctuation characteristics under unbalanced grid voltage are analyzed, and a submodule capacitor voltage fluctuation suppression strategy based on third harmonic injection is proposed; it can suppress the submodule capacitor voltage fluctuation under unbalanced grid voltage; the two proposed methods are simulated and verified on the PSCAD / EMTDC platform, and the control of photovoltaic microgrid is taken as the research object. This control method improves the current tracking capability, reduces the harmonic rate of the output current, and can balance the output current when the grid voltage is unbalanced. Then, the charge and discharge control principle and SOC characteristics of the lead-acid battery are analyzed, and a lead-acid battery SOC prediction method combining the CNN-RNN neural network is proposed. The combined network simultaneously utilizes the characteristics of CNN and RNN to capture the spatial and temporal characteristics of battery data. The battery temperature, charge and discharge current, and charge and discharge voltage are used as input feature vectors, and the battery SOC is used as the output vector to train the network, and then the battery SOC is predicted. This method can effectively predict the battery SOC, improve the prediction accuracy, and has high computational efficiency.Finally, based on the previous predictions, a photovoltaic microgrid economic operation model that takes into account both energy storage and user needs was established for the operation benefits of the photovoltaic microgrid. A voltage fluctuation suppressor for microgrid optimization scheduling was designed, which can maximize the photovoltaic absorption rate of the microgrid and reduce its total operating costs, achieving the goal of self-generation and self-use of the photovoltaic microgrid system and economically stable operation.

[0003] like Figure 1 As shown, the input buffer amplifier circuit of the prior art adopts a two-stage common emitter amplifier circuit, which has a fast response and a strong driving force, but is easily interfered by power system clutter and has poor voltage stability.

[0004] like Figure 2 As shown, it is a resonant circuit of the prior art, specifically a CVT ferromagnetic resonant circuit, which adopts a two-stage damping circuit as a whole, has strong voltage stability, but low signal response sensitivity and weak regulation ability. Summary of the invention

[0005] 1. Technical issues

[0006] 1. The voltage fluctuation suppression device in the prior art is greatly affected by the resonance signal and has a poor voltage stabilization effect.

[0007] 2. The voltage suppression device in the prior art has a backward control system and low flexibility.

[0008] (II) Technical solution

[0009] In response to the above technical problems, the present application proposes a voltage fluctuation suppressor for microgrid optimization scheduling, comprising an input amplification circuit, a resonance processing circuit, and a signal conditioning output circuit connected in sequence.

[0010] The input amplifier circuit amplifies the collected voltage fluctuation signal input, and can obtain instantaneous power in time domain analysis. Through coordinate transformation, the time domain analysis becomes simple. The AC signal is added to the base of the first-stage amplifier transistor Q5 through the coupling capacitor C4, and is output from its collector after amplification. It is added to the base of the second-stage amplifier transistor Q4 through the coupling capacitor C3, and is output from its collector after amplification by the transistor Q4. The output signal is output to the base of the transistor Q3 through the coupling capacitor, and the signal is output from the emitter of the transistor Q2 after being output from the collector, and is sent to the processing circuit of the subsequent stage. One end of the resistor R9 is connected to the emitter of the transistor Q4, and the other end is connected to the emitter of the transistor Q5, forming a negative feedback loop. The larger the negative feedback amount, the smaller the gain of the amplifier, so that the input signal is stable and effective.

[0011] The resonance processing circuit reduces the magnetic saturation of the signal, making it less likely to excite ferromagnetic resonance and cause overvoltage. It has a certain inhibitory effect on the resonant overvoltage, reduces the voltage fluctuation level of the submodule, and matches the appropriate resonant signal. The signal is input to the inverting end of the amplifier U1 through the enhancement MOS transistor Q13 control, and the non-inverting end is grounded through the capacitor C9. The output signal is respectively input to the MOS transistor Q13, the enhancement MOS transistor Q16, and the depletion MOS transistor Q19 for resonant frequency matching processing. The effective output signal is input through the base of the transistor Q11 and output through the emitter. The transistor Q18 improves the signal stability and output capacity. The circuit outputs a suitable resonant signal by suppressing overvoltage.

[0012] The signal adjustment output circuit can identify the resonant signal of the system through precise detection, that is, the wavelet analysis method can accurately determine the time when the fault occurs, and the FFT decomposition can identify the resonance type, and then output the adjustment signal to achieve voltage fluctuation suppression. The signal is input to the base of the transistor Q14 through the resistor R20A, and then input to the base of the transistor Q7 after passing through the resistor R18A, and input to the enhanced MOS transistor Q10 to obtain the overvoltage amplitude, and then input into the resonant overvoltage suppressor at the time of resonance, and filtered by the capacitors C5 and C8, and finally driven by the enhanced MOS transistor Q8 and the enhanced power MOS transistor Q9 to output the overvoltage suppression signal with a smaller resistance value. The output signal can suppress the resonant overvoltage and has a strong current-carrying capacity.

[0013] The voltage fluctuation suppressor for microgrid optimization dispatching designed in this system has input amplification circuit, resonance processing circuit, and signal adjustment output circuit. When the system fails, a large current can flow to the ground through the added resistor, and will not exist in the loop for a long time, so it will not cause a high overvoltage in the loop. The resistance has a strong current carrying capacity in the process of suppressing resonant overvoltage. By setting reasonable parameters, the phase-to-phase short circuit is realized, and then the resonant overvoltage is excited, and then the resonant overvoltage suppressor is put into use to suppress the resonant overvoltage, which is beneficial to the power regulation of power electronic devices and the realization of the voltage fluctuation suppressor for microgrid optimization dispatching.

[0014] (III) Beneficial effects

[0015] A voltage fluctuation suppressor for microgrid optimization scheduling, firstly, by matching a suitable resonant signal, the resonant overvoltage is suppressed, the voltage fluctuation level of the submodule is reduced, and the voltage fluctuation suppression is achieved in a lightweight manner; secondly, the system can realize power regulation control of power electronic devices, and realize flexible control and good dynamic response. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1The invention is an input buffer amplifier circuit of the prior art.

[0017] Figure 2 FIG. 1 is a resonant circuit of the prior art.

[0018] Figure 3 This is the input amplifier circuit schematic diagram of this application.

[0019] Figure 4 This is a schematic diagram of the resonance processing circuit of this application.

[0020] Figure 5 This is the schematic diagram of the signal conditioning output circuit of this application. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the embodiments.

[0022] like Figure 3 , Figure 4 , Figure 5 As shown, the present application proposes a voltage fluctuation suppressor for microgrid optimization scheduling, including an input amplification circuit, a resonance processing circuit, and a signal adjustment output circuit connected in sequence.

[0023] The input amplifier circuit amplifies the collected voltage fluctuation signal input, and can obtain instantaneous power in time domain analysis. Through coordinate transformation, the time domain analysis becomes simple. The AC signal is added to the base of the first-stage amplifier transistor Q5 through the coupling capacitor C4, and is output from its collector after amplification. It is added to the base of the second-stage amplifier transistor Q4 through the coupling capacitor C3, and is output from its collector after amplification by the transistor Q4. The output signal is output to the base of the transistor Q3 through the coupling capacitor, and the signal is output from the emitter of the transistor Q2 after being output from the collector, and is sent to the post-processing circuit. One end of the resistor R9 is connected to the emitter of the transistor Q4, and the other end is connected to the emitter of the transistor Q5, forming a negative feedback loop. The larger the negative feedback amount, the smaller the gain of the amplifier, so that the input signal is stable and effective.

[0024] Specifically, the input amplifier circuit includes an input port IN, two transistors Q4 and Q5, seven resistors R2, R3, R4, R5, R9, R12, and R13, and four capacitors C1, C2, C4, and C6. The input port IN in the input amplifier circuit is connected to the negative electrode of the capacitor C4, the positive electrode of the capacitor C4 is respectively connected to the base of the transistor Q5 and one end of the resistor R5, and the other end of the resistor R5 is connected to the high level VCC. The collector of the transistor Q5 is respectively connected to one end of the resistor R3 and the positive electrode of the capacitor C2, and the other end of the resistor R3 is connected to the high level VCC. The negative electrode of capacitor C2 is respectively connected to one end of resistor R4 and the base of transistor Q4, the other end of resistor R4 is connected to the high level VCC, the emitter of transistor Q5 is respectively connected to one end of resistor R9 and one end of resistor R12, the other end of resistor R12 is grounded, the other end of resistor R9 is respectively connected to the emitter of transistor Q4, one end of resistor R13, and the positive electrode of capacitor C6, the negative electrode of capacitor C6 is grounded, the other end of resistor R13 is grounded, the collector of transistor Q4 is respectively connected to one end of resistor R2 and the positive electrode of capacitor C1, and the other end of resistor R2 is connected to the high level VCC. The input amplifier circuit includes an output port Va, three transistors Q1, Q2, and Q3, a diode D1, a capacitor C1, and four resistors R1, R8, R14, and R15. In the input amplifier circuit, the cathode of the capacitor C1 is respectively connected to the base of the transistor Q3 and one end of the resistor R14, the other end of the resistor R14 is grounded, the collector of the transistor Q3 is respectively connected to the cathode of the diode D1 and the base of the transistor Q2, the anode of the diode D1 is respectively connected to the high level VCC, one end of the resistor R1, and the collector of the transistor Q1, the other end of the resistor R1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is connected to the emitter of the transistor Q2, the emitter of the transistor Q3 is connected to one end of the resistor R15, the other end of the resistor R15 is grounded, the collector of the transistor Q2 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the output port Va is connected to the emitter of the transistor Q2.

[0025] The resonance processing circuit reduces the magnetic saturation of the signal, making it less likely to excite ferromagnetic resonance and cause overvoltage. It has a certain inhibitory effect on the resonant overvoltage, reduces the voltage fluctuation level of the submodule, and matches the appropriate resonant signal. The signal is input to the inverting end of the amplifier U1 through the enhancement MOS transistor Q13 control, and the non-inverting end is grounded through the capacitor C9. The output signal is respectively input to the MOS transistor Q13, the enhancement MOS transistor Q16, and the depletion MOS transistor Q19 for resonant frequency matching processing. The effective output signal is input through the base of the transistor Q11 and output through the emitter. The transistor Q18 improves the signal stability and output capacity. The circuit outputs a suitable resonant signal by suppressing overvoltage.

[0026] Specifically, the resonance processing circuit includes an input port Va, an amplifier U1, three enhancement MOS transistors Q13, Q16, and Q15, a depletion MOS transistor Q19, a resistor R26, and a capacitor C9. The input port Va in the resonance processing circuit is connected to the gate of the enhancement MOS transistor Q15, the drain of the enhancement MOS transistor Q15 is connected to the high level VCC, the source is connected to the No. 2 interface of the amplifier U1, the No. 1 interface of the amplifier U1 is connected to one end of the capacitor C9, the other end of the capacitor C9 is grounded, the No. 5 interface of the amplifier U1 is grounded, and the amplifier U Interface No. 3 of 1 is connected to the high level VCC, interface No. 4 of amplifier U1 is respectively connected to the gate of enhancement MOS transistor Q13, the gate of enhancement MOS transistor Q16, and the gate of depletion MOS transistor Q19, the drain of enhancement MOS transistor Q13 is connected to the high level VCC, the source of enhancement MOS transistor Q13 is connected to the drain of enhancement MOS transistor Q16, the source of enhancement MOS transistor Q16 is connected to one end of resistor R26, the other end of resistor R26 is grounded, the source of depletion MOS transistor Q19 is grounded, and the drain is grounded. The resonance processing circuit includes an output port Vb, an enhancement MOS transistor Q13, three transistors Q11, Q17, Q18, and two resistors R23 and R24. The source end of the enhancement MOS transistor Q13 in the resonance processing circuit is respectively connected to one end of the resistor R24 ​​and the base of the transistor Q11, the other end of the resistor R24 ​​is connected to the emitter of the transistor Q17, the base of the transistor Q17 is grounded, the collector is grounded, the collector of the transistor Q11 is connected to the high level VCC, the emitter of the transistor Q11 is respectively connected to the output port Vb and one end of the resistor R23, the other end of the resistor R23 is connected to the emitter of the transistor Q18, the base of the transistor Q18 is grounded, and the collector is grounded.

[0027] The signal adjustment output circuit can identify the resonant signal of the system through precise detection, that is, the wavelet analysis method can accurately determine the time when the fault occurs, and the FFT decomposition can identify the resonance type, and then output the adjustment signal to achieve voltage fluctuation suppression. The signal is input to the base of the transistor Q14 through the resistor R20A, and then input to the base of the transistor Q7 after passing through the resistor R18A, and input to the enhanced MOS transistor Q10 to obtain the overvoltage amplitude, and then input into the resonant overvoltage suppressor at the time of resonance, and filtered by the capacitors C5 and C8, and finally driven by the enhanced MOS transistor Q8 and the enhanced power MOS transistor Q9 to output the overvoltage suppression signal with a smaller resistance value. The output signal can suppress the resonant overvoltage and has a strong current-carrying capacity.

[0028] Specifically, the signal conditioning output circuit includes an input port Vb, an enhancement MOS transistor Q10, three transistors Q6, Q7, Q14, nine resistors R6, R7, R11, R10A, R17, R18A, R22, R20A, R25, four capacitors C3, C5, C7, C8, three diodes D2, D3, D6, The input port Vb in the signal conditioning output circuit is respectively connected to one end of a resistor R20A and one end of a resistor R25, the other end of the resistor R20A is connected to the base of a transistor Q14, the other end of the resistor R25 is connected to the anode of a diode D6, the cathode of the diode D6 is grounded, the emitter of the transistor Q14 is grounded, the collector of the transistor Q14 is respectively connected to one end of a resistor R17, one end of a resistor R18A, one end of a capacitor C7, the anode of a diode D3, and the gate of an enhancement MOS transistor Q10, the other end of the resistor R17 is connected to the emitter of the transistor Q6, the other end of the capacitor C7 is respectively connected to the base of the transistor Q6 and the emitter of the transistor Q7, the other end of the resistor R18A is connected to the base of the transistor Q7, and the gate of the transistor Q7 is connected to the collector of the transistor Q14. The cathode of the transistor D3 is respectively connected to the collector of the transistor Q6 and one end of the resistor R7, the other end of the resistor R7 is connected to the anode of the diode D2, the cathode of the diode D2 is respectively connected to the anode of the capacitor C3 and one end of the resistor R6, the cathode of the capacitor C3 is grounded, the other end of the resistor R6 is connected to the high level VCC, the collector of the transistor Q7 is connected to one end of the resistor R10A, the other end of the resistor R10A is respectively connected to one end of the capacitor C5, one end of the resistor R11, one end of the capacitor C8, and the drain end of the enhancement MOS transistor Q10, the other end of the capacitor C5 is connected to the high level VCC, the other end of the capacitor C8 is grounded, the source end of the enhancement MOS transistor Q10 is connected to one end of the resistor R22, and the other end of the resistor R22 is grounded.The signal conditioning output circuit includes an output port OUT, an enhancement MOS transistor Q8, two Schottky diodes D4 and D5, two enhancement power MOS transistors Q9 and Q12, and four resistors R11, R16, R19, and R21. The signal conditioning output circuit includes: the other end of the resistor R11 is connected to the gate of the enhancement MOS transistor Q8, the drain end of the enhancement MOS transistor Q8 is connected to the high level VCC, the source end of the enhancement MOS transistor Q8 is respectively connected to one end of the resistor R19, the positive electrode of the Schottky diode D4, one end of the resistor R16, and the power enhancement MOS transistor Q9. The gate of the transistor Q9 is connected, the other end of the resistor R19 is grounded, the cathode of the Schottky diode D4 is connected to the cathode of the Schottky diode D5, the other end of the resistor R16 is respectively connected to the source end of the power enhancement MOS transistor Q9, the output port OUT, and the source end of the power enhancement MOS transistor Q12, the drain end of the power enhancement MOS transistor Q9 is connected to the high level VCC, the gate of the power enhancement MOS transistor Q12 is respectively connected to the anode of the Schottky diode D5 and one end of the resistor R21, the other end of the resistor R21 is grounded, and the drain end of the power enhancement MOS transistor Q12 is grounded.

[0029] The voltage fluctuation suppressor for microgrid optimization dispatching designed in this system has input amplification circuit, resonance processing circuit, and signal adjustment output circuit. When the system fails, a large current can flow to the ground through the added resistor, and will not exist in the loop for a long time, so it will not cause a high overvoltage in the loop. The resistance has a strong current carrying capacity in the process of suppressing resonant overvoltage. By setting reasonable parameters, the phase-to-phase short circuit is realized, and then the resonant overvoltage is excited, and then the resonant overvoltage suppressor is put into use to suppress the resonant overvoltage, which is beneficial to the power regulation of power electronic devices and the realization of the voltage fluctuation suppressor for microgrid optimization dispatching.

[0030] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A voltage fluctuation suppressor for microgrid optimization scheduling, comprising an input amplifier circuit, a resonance processing circuit, and a signal conditioning output circuit connected in sequence, characterized in that: The input amplifier circuit includes an input port IN, two transistors Q4 and Q5, seven resistors R2, R3, R4, R5, R9, R12, and R13, and four capacitors C1, C2, C4, and C6. In the input amplifier circuit, the input port IN is connected to the negative electrode of the capacitor C4, the positive electrode of the capacitor C4 is respectively connected to the base of the transistor Q5 and one end of the resistor R5, the other end of the resistor R5 is connected to the high level VCC, the collector of the transistor Q5 is respectively connected to one end of the resistor R3 and the positive electrode of the capacitor C2, the other end of the resistor R3 is connected to the high level VCC, and the capacitor C2 is connected to the positive electrode of the capacitor C4. The negative electrode of transistor Q5 is respectively connected to one end of resistor R4 and the base of transistor Q4, the other end of resistor R4 is connected to the high level VCC, the emitter of transistor Q5 is respectively connected to one end of resistor R9 and one end of resistor R12, the other end of resistor R12 is grounded, the other end of resistor R9 is respectively connected to the emitter of transistor Q4, one end of resistor R13 and the positive electrode of capacitor C6, the negative electrode of capacitor C6 is grounded, the other end of resistor R13 is grounded, the collector of transistor Q4 is respectively connected to one end of resistor R2 and the positive electrode of capacitor C1, the other end of resistor R2 is connected to the high level VCC; The input amplifier circuit comprises an output port Va, three transistors Q1, Q2, Q3, a diode D1, a capacitor C1, and four resistors R1, R8, R14, and R15. The cathode of the capacitor C1 in the input amplifier circuit is respectively connected to the base of the transistor Q3 and one end of the resistor R14, the other end of the resistor R14 is grounded, the collector of the transistor Q3 is respectively connected to the cathode of the diode D1 and the base of the transistor Q2, the anode of the diode D1 is respectively connected to the high level VCC, one end of the resistor R1, and the collector of the transistor Q1, the other end of the resistor R1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is connected to the emitter of the transistor Q2, the emitter of the transistor Q3 is connected to one end of the resistor R15, the other end of the resistor R15 is grounded, the collector of the transistor Q2 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the output port Va is connected to the emitter of the transistor Q2; The resonance processing circuit includes an input port Va, an amplifier U1, three enhancement MOS transistors Q13, Q16, and Q15, a depletion MOS transistor Q19, a resistor R26, and a capacitor C9. In the resonance processing circuit, the input port Va is connected to the gate of the enhancement MOS transistor Q15, the drain of the enhancement MOS transistor Q15 is connected to the high level VCC, the source is connected to the No. 2 interface of the amplifier U1, the No. 1 interface of the amplifier U1 is connected to one end of the capacitor C9, the other end of the capacitor C9 is grounded, the No. 5 interface of the amplifier U1 is grounded, and the No. 3 interface of the amplifier U1 is connected to the ground. The No. interface is connected to the high level VCC, the No. 4 interface of the amplifier U1 is respectively connected to the gate of the enhancement MOS transistor Q13, the gate of the enhancement MOS transistor Q16, and the gate of the depletion MOS transistor Q19, the drain of the enhancement MOS transistor Q13 is connected to the high level VCC, the source of the enhancement MOS transistor Q13 is connected to the drain of the enhancement MOS transistor Q16, the source of the enhancement MOS transistor Q16 is connected to one end of the resistor R26, the other end of the resistor R26 is grounded, the source of the depletion MOS transistor Q19 is grounded, and the drain is grounded; The resonance processing circuit includes an output port Vb, an enhancement MOS transistor Q13, three transistors Q11, Q17, Q18, and two resistors R23 and R24. The source end of the enhancement MOS transistor Q13 in the resonance processing circuit is respectively connected to one end of the resistor R24 ​​and the base of the transistor Q11, the other end of the resistor R24 ​​is connected to the emitter of the transistor Q17, the base of the transistor Q17 is grounded, the collector is grounded, the collector of the transistor Q11 is connected to the high level VCC, the emitter of the transistor Q11 is respectively connected to the output port Vb and one end of the resistor R23, the other end of the resistor R23 is connected to the emitter of the transistor Q18, the base of the transistor Q18 is grounded, and the collector is grounded; The signal conditioning output circuit includes an input port Vb, an enhancement MOS transistor Q10, three transistors Q6, Q7, Q14, nine resistors R6, R7, R11, R10A, R17, R18A, R22, R20A, R25, four capacitors C3, C5, C7, C8, three diodes D2, D3, D6, The input port Vb in the signal conditioning output circuit is respectively connected to one end of a resistor R20A and one end of a resistor R25, the other end of the resistor R20A is connected to the base of a transistor Q14, the other end of the resistor R25 is connected to the anode of a diode D6, the cathode of the diode D6 is grounded, the emitter of the transistor Q14 is grounded, the collector of the transistor Q14 is respectively connected to one end of a resistor R17, one end of a resistor R18A, one end of a capacitor C7, the anode of a diode D3, and the gate of an enhancement MOS transistor Q10, the other end of the resistor R17 is connected to the emitter of the transistor Q6, the other end of the capacitor C7 is respectively connected to the base of the transistor Q6 and the emitter of the transistor Q7, the other end of the resistor R18A is connected to the base of the transistor Q7, and the gate of the transistor Q7 is connected to the collector of the transistor Q14. The cathode of the transistor D3 is respectively connected to the collector of the transistor Q6 and one end of the resistor R7, the other end of the resistor R7 is connected to the anode of the diode D2, the cathode of the diode D2 is respectively connected to the anode of the capacitor C3 and one end of the resistor R6, the cathode of the capacitor C3 is grounded, the other end of the resistor R6 is connected to the high level VCC, the collector of the transistor Q7 is connected to one end of the resistor R10A, the other end of the resistor R10A is respectively connected to one end of the capacitor C5, one end of the resistor R11, one end of the capacitor C8, and the drain end of the enhancement MOS transistor Q10, the other end of the capacitor C5 is connected to the high level VCC, the other end of the capacitor C8 is grounded, the source end of the enhancement MOS transistor Q10 is connected to one end of the resistor R22, and the other end of the resistor R22 is grounded.

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