LDMOS structure based on in-vivo curvature expansion and method of manufacture

Abstract

The application provides a kind of LDMOS structure and manufacturing method based on in-vivo curvature extension, comprising: first conductive type semiconductor substrate, second conductive type drift region, first conductive type well region, first conductive type buried layer and second conductive type buried layer formed by ion implantation after grooving and high-temperature push joint, polysilicon gate electrode located on the surface of the device, first dielectric oxide layer, second dielectric oxide layer, third dielectric oxide layer, first conductive type buried layer and second conductive type buried layer are located in the substrate, and the grooving is filled with dielectric; the first conductive type buried layer and the second conductive type buried layer are introduced into the substrate, a larger curvature is formed in the body of the device, the electric field distribution in the body of the device is optimized, the distance of the drift region can be shortened, and the lateral withstand voltage problem of the device is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and relates to a high-voltage LDMOS power semiconductor device and its manufacturing method. Background Technology

[0002] LDMOS devices have their source, drain, and gate all located on the chip surface, making them easy to integrate and widely used in high-voltage integrated circuits and high-voltage power circuits. Due to their high input impedance, low loss, fast switching speed, wide safe operating area, and ease of integration, they are applied in consumer electronics, automotive electronics, LED displays, and many other fields. In high-voltage LDMOS devices, to reduce the device area, a small radius of curvature is typically created on the surface. This small radius of curvature at the source and drain junctions causes electric field concentration in this region, leading to premature avalanche breakdown. Summary of the Invention

[0003] To address the shortcomings of the prior art, this invention proposes an LDMOS structure based on bulk curvature extension technology. By introducing a first conductivity type buried layer and a second conductivity type buried layer into the substrate through trenching and high-temperature push-junction, the small curvature radius of the highly doped source and drain curvature junction is transformed into a large curvature radius of the low-doped junction. This effectively reduces the peak electric field at the curvature junction, preventing premature avalanche breakdown at that location. Consequently, the drift region distance can be shortened under certain voltage withstand conditions, thus solving the lateral voltage withstand problem of the device.

[0004] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0005] An LDMOS structure based on in-body curvature extension includes:

[0006] A first conductivity type semiconductor substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12, a first conductivity type semiconductor contact region A13, a second conductivity type semiconductor contact region A22 and a second conductivity type semiconductor contact region B23, a first conductivity type buried layer A14, a second conductivity type buried layer A24, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, and a polysilicon gate electrode 41;

[0007] In this design, a first conductivity type buried layer A14 is located on the left side of a first conductivity type substrate 11, a second conductivity type buried layer 24 is located on the right side of a first conductivity type substrate 11, a second conductivity type drift region 21 is located above a first conductivity type semiconductor substrate 11, and a first conductivity type well region 12 is located on the left side of the second conductivity type drift region 21; a heavily doped second conductivity type semiconductor contact region B23 is located on the right side of the second conductivity type drift region 21, and a heavily doped first conductivity type semiconductor contact region A13 and a second conductivity type semiconductor contact region A22 are located in the first conductivity type well region 12; a first dielectric oxide layer 31 is located above the first conductivity type well region 12 and partially above the second conductivity type drift region 21, and a second dielectric oxide layer 32 is located above the second conductivity type drift region 21; a third dielectric oxide layer 33 is formed by filling a dielectric layer after grooving; the third dielectric oxide layer 33 on the left side is located within the second conductivity type drift region 21 and its bottom extends into the first conductivity type buried layer A14 in the first conductivity type substrate 11, and it is located within the first conductivity type drift region 11. The right side of a portion within the type well region 12 is connected to the left side of the first conductivity type semiconductor contact region A13; the right side of the third dielectric oxide layer 33 is located within the second conductivity type drift region 21 and extends into the second conductivity type buried layer A24 in the first conductivity type substrate 11, and is situated between the second conductivity type semiconductor contact regions B23 within the second conductivity type drift region 21; the polysilicon gate electrode 41 covers the upper surface of the first dielectric oxide layer 31 and partially extends to the upper surface of the second dielectric oxide layer 32; the direction from the source to the drain is X, the direction from the surface to the bulk of the device is Y, and the Z direction is perpendicular to the XOY plane; the heavily doped doping concentration is greater than 1E19cm. -3 .

[0008] In a preferred embodiment, the second conductivity type buried layer A24 is connected to the second conductivity type drift region 21.

[0009] As a preferred embodiment, the grooves of the third dielectric oxide layer 33 are rectangular or elliptical in shape and are arranged discretely in the Z direction.

[0010] As a preferred embodiment, a second conductivity type well region 25 is introduced into the second conductivity type drift region 21 by ion implantation; the second conductivity type well region 25 is located within the second conductivity type drift region 21 and surrounds the second conductivity type semiconductor contact region B23.

[0011] As a preferred embodiment, a plurality of third dielectric oxide layers 33 are provided in parallel along the X direction near the drain end in the second conductivity type drift region 21.

[0012] As a preferred embodiment, a first conductivity type buried layer B15 is introduced into the second conductivity type drift region 21 via ion implantation. The first conductivity type buried layer B15 is located inside the second conductivity type drift region 21 and its upper surface is in close contact with the second dielectric oxide layer 32 or there is a gap between it and the second dielectric oxide layer 32, forming a RESURF structure. This structure can increase the concentration of the second conductivity type drift region 21 and reduce the specific on-resistance of the device.

[0013] Alternatively, a first conductivity type buried layer B15 and a second conductivity type buried layer B26 can be introduced into the second conductivity type drift region 21 via ion implantation. The first conductivity type buried layer B15 and the second conductivity type buried layer B26 are located inside the second conductivity type drift region 21, with the second conductivity type buried layer B26 positioned above the first conductivity type buried layer B15. A gap is provided between the second conductivity type buried layer B26 and the second dielectric oxide layer 32, forming a RESURF deformable structure. This structure can increase the concentration of the second conductivity type drift region 21 and reduce the specific on-resistance of the device.

[0014] As a preferred embodiment, the second conductivity type semiconductor contact region B23 is replaced with the first conductivity type semiconductor contact region B16 to form an IGBT structure;

[0015] As a preferred embodiment, the second conductivity type drift region 21 is formed by epitaxial growth;

[0016] The present invention also provides a method for manufacturing an LDMOS structure based on in-body curvature extension, comprising the following steps:

[0017] Step 1: Select a semiconductor substrate 11 of the first conductivity type;

[0018] Step 2: Deposit a hard mask and form trenches through photolithography and etching;

[0019] Step 3: Introduce a second type of conductivity impurity at the bottom of the tank by ion implantation, deposit a third dielectric oxide layer to fill the tank and etch it to the silicon plane;

[0020] Step 4: Deposit a hard mask and form trenches through photolithography and etching;

[0021] Step 5: Introduce impurities of the first conductivity type at the bottom of the trench by ion implantation, deposit a third dielectric oxide layer to fill the deep trench and etch it to the silicon plane;

[0022] Step 6: Implant a second type of impurity onto the first type of conductivity semiconductor substrate 11;

[0023] Step 7: High-temperature bonding at temperatures above 1000 degrees Celsius forms a second conductivity type drift region 21, a first conductivity type buried layer A14, and a second conductivity type buried layer A24;

[0024] Step 8: Thermal oxidation growth of the second dielectric oxide layer 32;

[0025] Step 9: Form a first conductivity type well region 12 by ion implantation of a second conductivity type impurity and push-junction;

[0026] Step 10: Deposit and etch the control gate polysilicon electrode 41;

[0027] Step 11: Injection activation to form a first conductivity type semiconductor contact region A13, a second conductivity type semiconductor contact region A22, and a second conductivity type semiconductor contact region B23.

[0028] As a preferred embodiment, the medium filled in the groove of the third dielectric oxide layer 33 is one of polycrystalline silicon, low-K dielectric, or high-K dielectric.

[0029] The beneficial effects of the present invention are as follows: by introducing a first type of buried layer and a second type of buried layer in the substrate through groove injection and high-temperature push junction, the small curvature radius of the highly doped source side and drain side curvature junction is transformed into a low-doped large curvature radius, which effectively reduces the electric field peak at the curvature junction, avoids the device from premature avalanche breakdown at this location, and thus shortens the drift region distance and solves the lateral breakdown voltage problem of the device. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology in Example 1;

[0031] Figure 2 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology in Example 2;

[0032] Figure 3 This is a schematic diagram of an LDMOS structure with a rectangular slot shape based on bulk curvature extension technology, as shown in Example 3.

[0033] Figure 4 This is a schematic diagram of an LDMOS structure with an elliptical groove shape based on in-body curvature extension technology, as described in Example 3.

[0034] Figure 5 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology in Example 4;

[0035] Figure 6 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology in Example 5;

[0036] Figure 7 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology, as shown in Example 6.

[0037] Figure 8This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology, as shown in Example 6.

[0038] Figure 9 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology, as shown in Example 6.

[0039] Figure 10 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology, as shown in Example 7.

[0040] Figure 11 This is a schematic diagram of an LDMOS structure based on in-body curvature extension technology, as shown in Example 8.

[0041] Figures 12(a)-12(k) This is a schematic diagram of the process flow of the device described in Example 1;

[0042] 11 is a semiconductor substrate of the first conductivity type, 12 is a well region of the first conductivity type, 13 is a semiconductor contact region A of the first conductivity type, 14 is a buried layer A of the first conductivity type, 15 is a buried layer B of the first conductivity type, 16 is a semiconductor contact region B of the first conductivity type, 21 is a drift region of the second conductivity type, 22 is a semiconductor contact region A of the second conductivity type, 23 is a semiconductor contact region B of the second conductivity type, 24 is a buried layer A of the second conductivity type, 25 is a well region of the second conductivity type, 26 is a buried layer B of the second conductivity type, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, and 41 is a polysilicon gate electrode. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Example 1

[0045] Example 1 describes an LDMOS device based on bulk curvature extension technology, such as... Figure 1 As shown, it specifically includes:

[0046] A first conductivity type semiconductor substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12, a first conductivity type semiconductor contact region A13, a second conductivity type semiconductor contact region A22 and a second conductivity type semiconductor contact region B23, a first conductivity type buried layer A14, a second conductivity type buried layer A24, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, and a polysilicon gate electrode 41;

[0047] In this design, a first conductivity type buried layer A14 is located on the left side of a first conductivity type substrate 11, a second conductivity type buried layer 24 is located on the right side of a first conductivity type substrate 11, a second conductivity type drift region 21 is located above a first conductivity type semiconductor substrate 11, and a first conductivity type well region 12 is located on the left side of the second conductivity type drift region 21; a heavily doped second conductivity type semiconductor contact region B23 is located on the right side of the second conductivity type drift region 21, and a heavily doped first conductivity type semiconductor contact region A13 and a second conductivity type semiconductor contact region A22 are located in the first conductivity type well region 12; a first dielectric oxide layer 31 is located above the first conductivity type well region 12 and partially above the second conductivity type drift region 21, and a second dielectric oxide layer 32 is located above the second conductivity type drift region 21; a third dielectric oxide layer 33 is formed by filling a dielectric layer after grooving; the third dielectric oxide layer 33 on the left side is located within the second conductivity type drift region 21 and its bottom extends into the first conductivity type buried layer A14 in the first conductivity type substrate 11, and it is located within the first conductivity type drift region 11. The right side of a portion within the type well region 12 is connected to the left side of the first conductivity type semiconductor contact region A13; the right side of the third dielectric oxide layer 33 is located within the second conductivity type drift region 21 and extends into the second conductivity type buried layer A24 in the first conductivity type substrate 11, and is situated between the second conductivity type semiconductor contact regions B23 within the second conductivity type drift region 21; the polysilicon gate electrode 41 covers the upper surface of the first dielectric oxide layer 31 and partially extends to the upper surface of the second dielectric oxide layer 32; the direction from the source to the drain is X, the direction from the surface to the bulk of the device is Y, and the Z direction is perpendicular to the XOY plane; the heavily doped doping concentration is greater than 1E19cm. -3 .

[0048] The first conductivity type buried layer 14A and the second conductivity type buried layer A24 were ion implanted through grooving, with an implantation dose of 1e13cm. -2 The injection dose of the first type of conductive buried layer is higher than that of the second type of conductive buried layer.

[0049] After ion implantation, the first conductivity type buried layer, the second conductivity type buried layer, and the second conductivity type drift region are synchronously pushed together to form.

[0050] Its basic working principle is as follows: taking the first conductivity type semiconductor material as P-type as an example, in the off-state condition where the gate voltage is zero, the PN junction formed by the second conductivity type drift region 21 and the first conductivity type well region 12, and the second conductivity type drift region 21 and the second conductivity type buried layer A24, is reverse biased by V. dUnder the influence of the gate bias, the PN junction formed by the first conductivity type semiconductor substrate 11, the second conductivity type drift region 21, and the first conductivity type semiconductor substrate 11 and the second conductivity type buried layer A24 also begins to deplete under the influence of the reverse bias. Due to the presence of the second conductivity type buried layer A24 and the first conductivity type buried layer A14, the small radius of curvature of the heavily doped source-drain curvature junction can be transformed into a large radius of curvature of the lightly doped junction, reducing the peak electric field of the curvature junction and preventing premature breakdown at the source and drain ends. This allows for a shorter drift region distance and solves the lateral breakdown voltage problem of the device. When the gate bias V... g When the voltage exceeds the threshold voltage, an inversion layer appears on the surface of the first conductivity type well region 12 near the first dielectric oxide layer 31, causing the device source and drain to conduct.

[0051] like Figures 12(a)-12(k) The diagram shown is a schematic representation of the process flow of Embodiment 1 of the present invention, which specifically includes the following steps:

[0052] Step 1: Select a semiconductor substrate 11 of the first conductivity type;

[0053] Step 2: Deposit a hard mask and form trenches through photolithography and etching;

[0054] Step 3: Introduce a second type of conductivity impurity at the bottom of the tank by ion implantation, deposit a third dielectric oxide layer to fill the tank and etch it to the silicon plane;

[0055] Step 4: Deposit a hard mask and form trenches through photolithography and etching;

[0056] Step 5: Introduce impurities of the first conductivity type at the bottom of the trench by ion implantation, deposit a third dielectric oxide layer to fill the deep trench and etch it to the silicon plane;

[0057] Step 6: Implant a second type of impurity onto the first type of conductivity semiconductor substrate 11;

[0058] Step 7: High-temperature bonding at temperatures above 1000 degrees Celsius forms a second conductivity type drift region 21, a first conductivity type buried layer A14, and a second conductivity type buried layer A24;

[0059] Step 8: Thermal oxidation growth of the second dielectric oxide layer 32;

[0060] Step 9: Form a first conductivity type well region 12 by ion implantation of a second conductivity type impurity and push-junction;

[0061] Step 10: Deposit and etch the control gate polysilicon electrode 41;

[0062] Step 11: Injection activation to form a first conductivity type semiconductor contact region A13, a second conductivity type semiconductor contact region A22, and a second conductivity type semiconductor contact region B23.

[0063] Example 2

[0064] like Figure 2 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Example 2. The difference between this example and Example 1 is that the second conductivity type buried layer A24 is connected to the second conductivity type drift region 21. The high concentration of the second conductivity type buried layer A24 is beneficial to reduce the concentration of the second conductivity type drift region 21, thereby reducing the specific on-resistance of the device. Its working principle is basically the same as that of Example 1.

[0065] Example 3

[0066] like Figure 3 and Figure 4 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Embodiment 3. The difference between this example and Embodiment 1 is that the trenches of the third dielectric oxide layer 33 are arranged discretely in the Z direction, and the trenches of the third dielectric oxide layer 33 are rectangular. Figure 3 As shown; or the groove shape is elliptical, such as Figure 4 As shown, its working principle is basically the same as that of Example 1.

[0067] Example 4

[0068] like Figure 5 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Example 4. The difference between this example and Example 1 is that a second conductivity type well region 25 is introduced into the second conductivity type drift region 21 via ion implantation. The second conductivity type well region 25 is located within the second conductivity type drift region 21 and surrounds the second conductivity type semiconductor contact region B23. Its working principle is basically the same as in Example 1.

[0069] Example 5

[0070] like Figure 6 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Example 5. The difference between this example and Example 1 is that multiple third dielectric oxide layers 33 arranged parallel to each other along the X direction are provided near the drain end in the second conductivity type drift region 21. Its working principle is basically the same as in Example 1.

[0071] Example 6

[0072] like Figure 7 , Figure 8 and Figure 9 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Example 6. The difference between this example and Example 1 is that...

[0073] A first conductivity type buried layer B15 is introduced into the second conductivity type drift region 21 via ion implantation. The first conductivity type buried layer B15 is located inside the second conductivity type drift region 21 and its upper surface is in close contact with the second dielectric oxide layer 32. Figure 7 As shown; or a gap is provided between it and the second dielectric oxide layer 32 to form a RESURF structure, such as Figure 8 As shown;

[0074] Alternatively, a first conductivity type buried layer B15 and a second conductivity type buried layer B26 can be introduced into the second conductivity type drift region 21 via ion implantation. The first conductivity type buried layer B15 and the second conductivity type buried layer B26 are located inside the second conductivity type drift region 21, with the second conductivity type buried layer B26 positioned above the first conductivity type buried layer B15. A gap is provided between the second conductivity type buried layer B26 and the second dielectric oxide layer 32, forming a RESURF deformable structure, such as... Figure 9 As shown;

[0075] This structure can increase the doping concentration of the drift region of the second conductivity type to reduce the specific on-resistance of the device, and its working principle is basically the same as that of Example 1.

[0076] Example 7

[0077] like Figure 10 The diagram shown is a schematic of an LDMOS structure based on in-body curvature extension technology in Example 7. The difference between this example and Example 1 is that the second conductivity type semiconductor contact area B23 is replaced with the first conductivity type semiconductor contact area B16 to form an IGBT structure.

[0078] Example 8

[0079] like Figure 11 The diagram shown is a schematic of an LDMOS structure based on in vivo curvature extension technology in Example 8. The difference between this example and Example 1 is that the second conductivity type drift region is formed by epitaxial growth, and its working principle is basically the same as that of Example 1.

Claims

1. An LDMOS structure based on bulk curvature extension, characterized in that... include: First conductivity type semiconductor substrate (11), second conductivity type drift region (21), first conductivity type well region (12), first conductivity type semiconductor contact region A (13), second conductivity type semiconductor contact region A (22) and second conductivity type semiconductor contact region B (23), first conductivity type buried layer A (14), second conductivity type buried layer A (24), first dielectric oxide layer (31), second dielectric oxide layer (32), third dielectric oxide layer (33), polysilicon gate electrode (41); Among them, the first conductivity type buried layer A (14) is located on the left side of the first conductivity type semiconductor substrate (11), the second conductivity type buried layer A (24) is located on the right side of the first conductivity type semiconductor substrate (11), the second conductivity type drift region (21) is located above the first conductivity type semiconductor substrate (11), and the first conductivity type well region (12) is located on the left side of the second conductivity type drift region (21); the heavily doped second conductivity type semiconductor contact region B (23) is located on the right side of the second conductivity type drift region (21), and the heavily doped first conductivity type semiconductor contact region A (13) and the second conductivity type semiconductor contact region A (22) are located in the first conductivity type well region (12); The first dielectric oxide layer (31) is located above the first conductivity type well region (12) and partially above the second conductivity type drift region (21), and the second dielectric oxide layer (32) is located above the second conductivity type drift region (21); the third dielectric oxide layer (33) is formed by filling the dielectric after grooving; the third dielectric oxide layer (33) on the left is located in the second conductivity type drift region (21) and its bottom extends into the first conductivity type buried layer A (14) in the first conductivity type semiconductor substrate (11), and the right side of the part of it located in the first conductivity type well region (12) is connected to the left side of the first conductivity type semiconductor contact region A (13). The third dielectric oxide layer (33) on the right is located within the second conductivity type drift region (21) and extends into the second conductivity type buried layer A (24) in the first conductivity type semiconductor substrate (11), and is located on the left side within the second conductivity type semiconductor contact region B (23) in the second conductivity type drift region (21); the polysilicon gate electrode (41) covers the upper surface of the first dielectric oxide layer (31) and partially extends to the upper surface of the second dielectric oxide layer (32); the direction from the source to the drain is X, the direction from the surface to the bulk of the device is Y, and the Z direction is perpendicular to the XOY plane; the doping concentration of the heavily doped layer is greater than 1E19cm. -3 .

2. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: The second conductivity type buried layer A (24) is connected to the second conductivity type drift region (21).

3. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: The grooves of the third dielectric oxide layer (33) are rectangular or elliptical and are arranged separately in the Z direction.

4. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: A second conductivity type well region (25) is introduced into the second conductivity type drift region (21) by ion implantation; the second conductivity type well region (25) is located in the second conductivity type drift region (21) and surrounds the second conductivity type semiconductor contact region B (23).

5. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: Multiple third dielectric oxide layers (33) are arranged in parallel along the X direction near the drain end in the second conductivity type drift region (21).

6. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: A first conductive type buried layer B (15) is introduced into the second conductive type drift region (21) by ion implantation. The first conductive type buried layer B (15) is located inside the second conductive type drift region (21) and its upper surface is in close contact with the second dielectric oxide layer (32) or there is a gap between it and the second dielectric oxide layer (32) to form a RESURF structure. Alternatively, a first conductive type buried layer B (15) and a second conductive type buried layer B (26) can be introduced into the second conductive type drift region (21) by ion implantation. The first conductive type buried layer B (15) and the second conductive type buried layer B (26) are located inside the second conductive type drift region (21), and the second conductive type buried layer B (26) is located above the first conductive type buried layer B (15). There is a gap between the second conductive type buried layer B (26) and the second dielectric oxide layer (32) to form a RESURF deformable structure.

7. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: The second type of semiconductor contact region B (23) is replaced with the first type of semiconductor contact region B (16) to form an IGBT structure.

8. The LDMOS structure based on bulk curvature extension according to claim 1, characterized in that: The second type of conductivity drift region (21) is formed by epitaxial growth.

9. A method for manufacturing an LDMOS structure based on bulk curvature extension as described in any one of claims 1 to 8, characterized in that... Includes the following steps: Step 1: Select a semiconductor substrate of the first conductivity type (11), and define the upper surface as a silicon plane; Step 2: Deposit a hard mask and form trenches through photolithography and etching; Step 3: Introduce a second type of conductivity impurity at the bottom of the tank by ion implantation, deposit a third dielectric oxide layer to fill the tank and etch it to the silicon plane; Step 4: Deposit a hard mask and form trenches through photolithography and etching; Step 5: Introduce impurities of the first conductivity type at the bottom of the trench by ion implantation, deposit a third dielectric oxide layer to fill the deep trench and etch it to the silicon plane; Step 6: Implant a second type of impurity over the first type of conductivity semiconductor substrate (11); Step 7: High temperature above 1000 degrees Celsius is used to push the formation of a second conductivity type drift region (21), a first conductivity type buried layer A (14), and a second conductivity type buried layer A (24); Step 8: Thermal oxidation growth of the second dielectric oxide layer (32); Step 9: Form a first conductivity type well region (12) by ion implantation of a second conductivity type impurity and push junction. Step 10: Deposit and etch the control gate polysilicon gate electrode (41); Step 11: Injection activation to form a first conductivity type semiconductor contact region A (13), a second conductivity type semiconductor contact region A (22), and a second conductivity type semiconductor contact region B (23).

10. A method for manufacturing an LDMOS structure based on bulk curvature extension according to claim 9, characterized in that: The medium filled in the trench of the third dielectric oxide layer (33) is one of polysilicon, low-K dielectric, or high-K dielectric.

Images