Semiconductor device including LDMOS transistor and method for manufacturing the same

Abstract

The present invention provides a semiconductor device including an LDMOS transistor and a manufacturing method thereof, comprising: providing a substrate, etching a portion of the thickness of the substrate to form a trench; performing an oxidation process to form a LOCOS in the trench; forming a shallow trench isolation, forming the shallow trench isolation in the substrate on both sides of the LOCOS; forming a drift region with a first conductivity type, the drift region extending from the inside of the substrate to the upper surface of the substrate, the drift region surrounding the LOCOS located in the trench; forming a gate oxide layer and a gate located on the substrate in sequence; the gate covering the gate oxide layer and part of the LOCOS. The LOCOS of the present invention is formed before shallow trench isolation (STI), avoiding the problem of the peripheral ring of the shallow trench isolation being locally corroded to form a groove caused by the LOCOS process.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device including an LDMOS transistor and a manufacturing method thereof. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a process for manufacturing bipolar transistor (BJT) devices, complementary metal oxide semiconductor (CMOS) devices and double diffused metal oxide semiconductor (DMOS) devices on the same chip (Die).

[0003] LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device with double diffusion structure. Compared with ordinary MOS transistor, LDMOS transistor has a low-doped drift region. The drift region has a buffering effect on the electric field between the drain region and the gate, reduces the parasitic capacitance between the drain and source electrodes, and weakens the short channel effect. Part of the voltage will fall on the drift region, which increases the breakdown voltage (Breakdown Voltage, BV). LDMOS transistors are widely used in medium and high voltage and high voltage fields due to their excellent characteristics. For LDMOS transistors, on-resistance (On-resistance, Ron) and breakdown voltage are the two most important parameters. The smaller the on-resistance, the stronger the driving capability of LDMOS; the larger the breakdown voltage, the higher the reliability of LDMOS. Therefore, it is usually hoped that LDMOS has a smaller on-resistance and a larger breakdown voltage.

[0004] For semiconductor devices including LDMOS transistors, the design of the drift region is key. By setting a field oxide layer and a field plate on the drift region, the depletion electric field in the drift region under the blocking state can be weakened, which is beneficial to improving the breakdown voltage. At present, the drift region field oxygen commonly used to be set below the field plate is silicon oxide formed by using the silicon local oxidation isolation (LOCOS) process, high temperature oxide (HTO) film isolation or shallow trench isolation (STI) process. However, in the process using STI as the drift region field oxygen, the LDMOS transistor has a long conduction path and a small conduction cross-section, resulting in a large on-resistance (Ron). In the process using HTO as the drift region field oxygen, the high temperature oxide (HTO) film layer is deposited by the LPCVD process at a high temperature and a slow speed. The HTO thickness is usually thin, and the HTO thickness is limited. It has little effect on improving the depletion electric field concentration on the substrate surface, and has no obvious effect on improving the breakdown voltage. In the process using LOCOS as the drift region field oxygen, there is a problem of poor compatibility between the LOCOS process and the advanced CMOS process. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device including an LDMOS transistor and a manufacturing method thereof, which avoids the problem of local corrosion of the periphery of the shallow trench isolation caused by the LOCOS process to form a groove, and makes the LOCOS process and the CMOS process more compatible.

[0006] The present invention provides a method for manufacturing a semiconductor device including an LDMOS transistor, comprising:

[0007] Providing a substrate, and etching a portion of the thickness of the substrate to form a groove;

[0008] performing an oxidation process to form LOCOS in the trench;

[0009] Forming shallow trench isolation, wherein the shallow trench isolation is formed in the substrate on both sides of the LOCOS;

[0010] forming a drift region of a first conductivity type, the drift region extending from within the substrate to an upper surface of the substrate, the drift region surrounding the LOCOS located in the trench;

[0011] A gate oxide layer and a gate electrode are sequentially formed on the substrate; the gate electrode covers the gate oxide layer and a portion of the LOCOS.

[0012] Furthermore, in the same photolithography process of etching a portion of the thickness of the substrate to form the groove, the substrate is also etched to form an alignment mark groove.

[0013] Furthermore, by controlling the etching depth of the trench and the oxidation growth thickness of the LOCOS, the upper surface of the LOCOS finally formed is made close to the upper surface of the substrate.

[0014] Furthermore, the height difference between the upper surface of the LOCOS and the upper surface of the substrate formed finally is less than or equal to 200 angstroms.

[0015] Furthermore, the manufacturing method further comprises:

[0016] Providing a substrate, and sequentially forming an oxide layer 1 and a nitride layer 1 on the substrate; etching the nitride layer 1, the oxide layer 1 and a portion of the depth of the substrate to form the trench and the alignment mark groove;

[0017] After forming the LOCOS, removing the first nitride layer and the first oxide layer, and regrowing the second oxide layer on the substrate;

[0018] Before forming the shallow trench isolation, a second nitride layer is formed, and the second nitride layer covers the LOCOS and the second oxide layer.

[0019] Further, forming shallow trench isolation includes:

[0020] Etching the second nitride layer, the second oxide layer and a partial thickness of the substrate to form an STI trench; filling the oxide layer in the STI trench to form the shallow trench isolation;

[0021] The second nitride layer is removed.

[0022] Further, after forming the LOCOS and before forming the shallow trench isolation, the method further includes:

[0023] Dopants of the first conductivity type are implanted into the substrate to form a deep well; the deep well extends from the inside of the substrate to the upper surface of the substrate, and the deep well surrounds the drift region.

[0024] Furthermore, after forming the shallow trench isolation and before forming the gate oxide layer and the gate, the method further includes:

[0025] A well region having a second conductivity type is formed, wherein the second conductivity type is opposite to the first conductivity type, the well region extends from within the substrate to an upper surface of the substrate, and the deep well surrounds the well region.

[0026] Furthermore, after forming the gate oxide layer and the gate, the method further includes:

[0027] forming a source region and a drain region; the source region and the drain region are disposed on both sides of the gate and are both of the first conductivity type; the doping concentration of the drain region is greater than that of the drift region;

[0028] The source region is located at the top of the substrate and surrounded by the well region, the drain region is located at the top of the substrate and surrounded by the drift region, and the drain region is spaced a distance from the LOCOS.

[0029] The present invention also provides a semiconductor device including an LDMOS transistor, comprising:

[0030] a substrate having a groove formed therein;

[0031] A LOCOS is formed in the groove;

[0032] Shallow trench isolation, wherein the shallow trench isolation is formed in the substrate on both sides of the LOCOS;

[0033] A drift region, the drift region is of a first conductivity type, the drift region extends from inside the substrate to an upper surface of the substrate, and the drift region surrounds the LOCOS located in the trench;

[0034] A gate oxide layer and a gate are sequentially located on the substrate; the gate covers the gate oxide layer and a portion of the LOCOS.

[0035] Furthermore, a height difference between an upper surface of the LOCOS and an upper surface of the substrate is less than or equal to 200 angstroms.

[0036] Furthermore, it also includes:

[0037] a well region, the well region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the well region extending from within the substrate to an upper surface of the substrate;

[0038] A source region and a drain region; the source region and the drain region are arranged on both sides of the gate and are both of the first conductivity type; the doping concentration of the drain region is greater than that of the drift region; the source region is located at the top of the substrate and surrounded by the well region, the drain region is located at the top of the substrate and surrounded by the drift region, and the drain region is spaced a distance from the LOCOS.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention provides a semiconductor device including an LDMOS transistor and a manufacturing method thereof, comprising: providing a substrate, etching a portion of the thickness of the substrate to form a trench; performing an oxidation process to form a LOCOS in the trench; forming a shallow trench isolation, forming the shallow trench isolation in the substrate on both sides of the LOCOS; forming a drift region with a first conductivity type, the drift region extending from the inside of the substrate to the upper surface of the substrate, the drift region surrounding the LOCOS located in the trench; forming a gate oxide layer and a gate located on the substrate in sequence; the gate covering the gate oxide layer and part of the LOCOS. The LOCOS of the present invention is formed before shallow trench isolation (STI), avoiding the problem of the peripheral ring of the shallow trench isolation being locally corroded to form a groove caused by the LOCOS process.

[0041] Furthermore, in the same photolithography process of etching a portion of the thickness of the substrate to form a groove, the substrate is also etched to form an alignment mark groove. The groove and the alignment mark groove are performed in the same exposure and etching process, thereby saving one exposure and etching step.

[0042] Furthermore, by controlling the etching depth of the groove and the oxidation growth thickness of the LOCOS, the upper surface of the LOCOS is made close to the upper surface of the substrate, which can basically eliminate the LOCOS protrusion (the part of the upper surface of the LOCOS that is higher than the substrate is a protrusion), avoid the LOCOS protrusion affecting the ion implantation of the well region and the drift region, and avoid the LOCOS protrusion affecting the subsequent gate exposure and etching process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figures 1 to 11 A schematic diagram of the steps of a method for manufacturing LDMOS.

[0044] Fig.12 The present invention is a schematic flow chart of a method for manufacturing a semiconductor device including an LDMOS transistor according to an embodiment of the present invention.

[0045] Figures 13 to 22 The figure is a schematic diagram of each step of a method for manufacturing a semiconductor device including an LDMOS transistor according to an embodiment of the present invention.

[0046] The reference numerals are as follows:

[0047] 10-substrate; 101-oxide layer; 102-alignment mark groove; 103-first nitride layer; 104-second nitride layer; 105-opening; 110-LOCOS; 111-gate oxide layer; 120-DNW; 130-shallow trench isolation; 140-well region; 150-drift region; 161-gate;

[0048] 20-substrate; 201-oxide layer 1; 202-nitride layer 1; 203-groove; 204-alignment mark groove; 205-oxidation structure; 210-LOCOS; 211-oxide layer 2; 212-nitride layer 2; 206-STI groove; 220-DNW; 222-gate oxide layer; 230-shallow trench isolation; 240-well region; 250-drift region; 261-gate; 270-sidewall; 280-source region; 290-drain region. DETAILED DESCRIPTION

[0049] As described in the background art, in a semiconductor device including an LDMOS transistor, local oxidation isolation of silicon (LOCOS) is used as a drift region field oxygen manufacturing method, but the compatibility between the LOCOS process and the advanced CMOS process is relatively poor.

[0050] Specifically, Figure 1 As shown, an oxide layer 101 is formed on the substrate 10 .

[0051] like Figure 2 As shown, a first exposure and etching process is performed to etch the oxide layer 101 and a partial thickness of the substrate 10 to form an alignment mark groove 102 .

[0052] like Figure 3 As shown, a deep N-type well (DNW) process is performed to implant N-type ions into the substrate 10 to form a DNW 120 , which extends from a deeper position in the substrate 10 to the upper surface of the substrate 10 (the surface close to the oxide layer 101 ).

[0053] like Figure 4 As shown, a shallow trench isolation (STI) 130 is formed. Specifically, in the active area, a first nitride layer 103 is formed on the surface of the oxide layer 101. The first nitride layer 103, the oxide layer 101 and a portion of the thickness of the substrate 10 are etched to form an STI trench, and the oxide layer is filled in the STI trench to form a shallow trench isolation (STI) 130, and a chemical mechanical polishing process (CMP) is performed to make the upper surface of the first nitride layer 103 and the shallow trench isolation (STI) 130 flat.

[0054] like Figure 4 and Figure 5 As shown, an opening 105 corresponding to LOCOS is formed. Specifically, the performance (e.g., compactness) of the first nitride layer 103 is reduced after etching and CMP process, so the first nitride layer 103 is removed and regrown to form the second nitride layer 104. A second exposure and etching process is performed to form an opening 105 corresponding to LOCOS in the second nitride layer 104.

[0055] like Figure 6 and Figure 7 As shown, an oxidation process is performed to oxidize the opening 105 to form LOCOS 110. The second nitride layer 104 is removed, and the oxide layer 101 is wet cleaned. Figure 8 As shown, ion implantation processes are performed to form the well region 140 and the drift region 150. Fig. 9 As shown, a gate oxide layer 111 and a gate 161 are formed.

[0056] Fig.10 for Figure 6 A partial enlarged schematic diagram of point a in the middle; Fig.11 for Figure 7The schematic diagram of the local enlargement at b in the middle. The LOCOS process will cause a layer of thermally grown nitrogen oxide to form at a on the upper surface of the substrate 10 below the edge of the second nitride layer 104 (e.g., Si3N4) near the opening 105, which will hinder the subsequent silicon oxidation reaction, resulting in a thin gate oxide layer at a, and a white band optically, which is called the white band effect. The solution to the white band effect includes: after removing the second nitride 104, a first sacrificial oxide layer is formed by oxidation, and the first wet cleaning is performed; then, a second sacrificial oxide layer is formed by oxidation, and the second wet cleaning is performed; the nitrogen (N) element at the Si / SIO2 interface can be removed, thereby ensuring that the overall thickness of the gate oxide layer formed subsequently is uniform. However, the solution to the white band effect has led to new problems. The main problem is that during the two wet cleanings, excessive HF cleaning liquid will cause the peripheral area b of the shallow trench isolation (STI) 130 to be locally corroded to form a groove, affecting the performance of the narrow channel device of the LDMOS; and polysilicon residual defects are easily generated during the subsequent gate etching. In addition, the height of the LOCOS protrusion produced by the above process flow is relatively high on the substrate surface, and the subsequent ion implantation process of the well region and the drift region will be affected by the LOCOS protrusion (the upper surface portion of the LOCOS that is higher than the substrate is a protrusion). If the LOCOS formation step is placed after the ion implantation process of the well region and the drift region, the heat in the LOCOS formation step will affect the distribution of ions in the well region and the drift region; in addition, the LOCOS protrusion affects the subsequent gate exposure and etching process windows.

[0057] Based on the above research, an embodiment of the present invention provides a semiconductor device including an LDMOS transistor and a method for manufacturing the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0058] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0060] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] The embodiment of the present invention provides a method for manufacturing a semiconductor device including an LDMOS transistor, such as Fig.12 As shown, including:

[0063] Step S1, providing a substrate, and etching a portion of the thickness of the substrate to form a groove;

[0064] Step S2, performing an oxidation process to form LOCOS in the trench;

[0065] Step S3, forming shallow trench isolation, forming the shallow trench isolation in the substrate on both sides of the LOCOS;

[0066] Step S4, forming a drift region of the first conductivity type, wherein the drift region extends from the inside of the substrate to the upper surface of the substrate, and the drift region surrounds the LOCOS located in the trench;

[0067] Step S5, forming a gate oxide layer and a gate sequentially located on the substrate; the gate covers the gate oxide layer and a portion of the LOCOS.

[0068] Embodiments of the present invention relate to a semiconductor device including an LDMOS transistor and a method for manufacturing the same. The semiconductor device may include at least one LDMOS transistor. The LDMOS transistor has a basic transistor structure including a source region, a gate region, and a drain region, wherein the source region and the drain region may be symmetrically or asymmetrically arranged around the gate. The following embodiments mainly introduce the structure and manufacturing method of a single LDMOS transistor. However, it can be understood that in some embodiments, the semiconductor device includes more than two LDMOS transistors, and the more than two LDMOS transistors can be manufactured at the same time, and the more than two LDMOS transistors can be symmetrically arranged along a center line on the semiconductor device, and may have common components (such as a drain region and a drift region).

[0069] In the following description of a semiconductor device containing an LDMOS transistor, the case of an n-channel LDMOS transistor is mainly used for explanation. In this case, the first conductivity type in the following is n-type, and the second conductivity type opposite to the first conductivity type is p-type. The n-type dopants include phosphorus, arsenic, etc., and the p-type dopants include boron, indium, etc. However, the LDMOS transistor contained in the semiconductor device is not limited to the n-channel, but can also be a p-channel. In the latter case, it is only necessary to reverse the conductivity type (that is, the first conductivity type is p-type, and the second conductivity type opposite to the first conductivity type is n-type) and combine it with appropriate modification of the gate bias state.

[0070] Combine the following Figures 13 to 22 Each step of a method for manufacturing a semiconductor device including an LDMOS transistor according to an embodiment of the present invention is described in detail.

[0071] like Fig.13As shown, a substrate 20 is provided, on which an oxide layer 201 and a nitride layer 202 are sequentially formed. The substrate 20 is used to form a semiconductor device including an LDMOS transistor. The material of the substrate 20 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, etc., or silicon on insulator (SOI) or germanium on insulator (GOI), or other materials, such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP, etc., or a combination of the above materials. The substrate 20 may include a doped epitaxial layer, a gradient semiconductor layer, and a semiconductor layer located on other semiconductor layers of different types (such as a silicon layer on a germanium silicon layer). Here, the substrate 20 is, for example, a silicon substrate. The substrate 20 may be a doped substrate, for example, with a second conductivity type (such as p-) doping.

[0072] like Fig.14 As shown, exposure and etching processes are performed to form a groove 203 and an alignment mark groove 204 corresponding to LOCOS. Specifically, a patterned mask (e.g., a photoresist layer) can be formed on the surface of the nitride layer 1 202 first, and the groove 203 region and the alignment mark groove 204 can be defined by using the mask opening, and then the nitride layer 1 202, the oxide layer 1 201, and a portion of the depth of the substrate 10 exposed by the mask opening are etched to form a groove 203 and an alignment mark groove 204 corresponding to LOCOS. The groove 203 and the alignment mark groove 204 are performed in the same exposure and etching process, which can save one exposure and etching process.

[0073] like Fig.15 As shown, LOCOS 210 is formed; a furnace tube oxidation process is performed to form LOCOS 210 in the groove 203, and an oxidation structure 205 is formed in the alignment mark groove 204. The furnace tube oxidation process consumes the substrate 20, and the substrate 20 is, for example, a silicon substrate. The substrate 20 serves as a silicon source for forming LOCOS 210. The substrate 20 at the bottom and side of the groove 203 undergoes an oxidation reaction to generate an approximately elliptical LOCOS 210. After the furnace tube oxidation is completed, the height difference between the highest point on the upper surface of LOCOS 210 and the upper surface of the substrate 20 is less than or equal to 1000 angstroms. The solution of this embodiment is better than the prior art (the aforementioned Figures 1 to 10) is more conducive to controlling the height of LOCOS 210. The height of LOCOS 210 can be adjusted by controlling the opening depth of the groove 203 and the oxidation depth of LOCOS 210. In this embodiment, the lower part of the groove 203 is located in the substrate 20. During the formation of LOCOS 210, the substrate 20 serves as a silicon source for forming LOCOS 210. The lower part of the formed LOCOS 210 is located in the groove 203. The part of the groove 203 located in the substrate 20 accommodates a part of the thickness of LOCOS 210. In this way, the height difference between the highest point of the upper surface of LOCOS 210 and the upper surface of the substrate 20 can be reduced, which is more conducive to controlling the height of LOCOS 210.

[0074] The aforementioned Figures 1 to 10 In the production method described, Figure 5 and Figure 6 As shown, the opening 105 is only etched through the second nitride layer 104, and the opening 105 is not formed in the substrate 10. The furnace tube oxidation process consumes the oxide layer 101 and the substrate 10, and the substrate 10 is used as a silicon source for forming the LOCOS 110. Most of the thickness of the LOCOS 110 formed in this way is higher than the upper surface of the substrate 10, and a small part of the thickness of the LOCOS 110 formed is lower than the upper surface of the substrate 10 due to the consumption of the substrate 10. Finally, the height difference between the highest point of the upper surface of the LOCOS 110 and the upper surface of the substrate 10 is large, which is undesirable.

[0075] like Fig.15 and Fig.16 As shown, a deep N-type well (DNW) 220 is formed. Specifically, the performance (e.g., compactness) of the nitride layer 1 202 and the oxide layer 1 201 is reduced after the previous process, and in order to avoid the white band effect causing the overall thickness of the gate oxide layer formed subsequently to be uneven, the nitride layer 1 202 and the oxide layer 1 201 are removed. In the process of removing the nitride layer 1 202 and the oxide layer 1 201, both are removed by wet cleaning. In the process of wet cleaning, the nitrogen (N) element at the Si / SIO2 interface is removed as much as possible to avoid the white band effect; thereafter, the oxide layer 211 is regrown to form.

[0076] A deep N-type well (DNW) process is performed. N-type ions are injected into the substrate 20 to form a DNW220, which extends from a deeper position in the substrate 20 to the upper surface of the substrate 20 (the surface close to the side of the oxide layer 211). The deep well process is generally indispensable in the BCD process, and can be used for isolation or to form a triode. The DNW can be part of the LDMOS transistor or have other uses independent of the LDMOS transistor. Because the DNW is deep and needs to receive a lot of heat and diffuse, the deep well process is placed before the STI process. The DNW can be used together with the alignment mark groove 204 for mask alignment in subsequent process steps.

[0077] like Fig.17 and Fig.18 As shown, a shallow trench isolation (STI) 230 is formed. Specifically, the second nitride layer 212 is formed first, and an exposure and etching process is performed to form an STI trench 206. The second nitride layer 212, the second oxide layer 211 and a portion of the thickness of the substrate 20 are etched to form an STI trench 206, and the oxide layer is filled in the STI trench 206 to form a shallow trench isolation (STI) 230. The shallow trench isolation (STI) 230 is used to isolate the components to be manufactured on the substrate 20 so that they are insulated from each other. The second nitride layer 212 is removed. In the process of removing the second nitride layer 212, a small amount of the upper surface of the LOCOS 210 is lost. In the process of removing the nitride layer 202 and the oxide layer 201 and forming the oxide layer 211 and the nitride layer 212, there will also be a small amount of loss on the upper surface of LOCOS210. By controlling and adjusting the amount of loss on the upper surface of LOCOS210 in each process step, the height difference between the upper surface of LOCOS210 and the upper surface of the substrate 20 is made less than or equal to 200 angstroms.

[0078] like Fig.19 As shown, a well region 240 and a drift region 250 are formed; the substrate 20 includes a drift region 250 formed by an implantation process, the drift region 250 has a first conductivity type, and the drift region 250 extends from the substrate 20 to the upper surface of the substrate 20. When the drift region 250 is made by an implantation process, a patterned mask (for example, a photoresist layer) can be first formed on the surface of the substrate 20, and the implantation region is defined by the mask opening. The first conductivity type is, for example, n-type, and in the implantation process for forming the drift region 250, n-type dopants (such as phosphorus or arsenic) are implanted into the implantation region of the substrate 20. The implantation process can be a combination of a shallow region implantation with low implantation energy and a deep region implantation with high implantation energy. The implantation density and implantation depth of the n-type dopant can be set according to the size and characteristics of the LDMOS transistor. After the n-type dopant is implanted, the mask is removed.

[0079] In the embodiment of the present invention, after the first conductivity type implantation for forming the drift region 250 is completed, the implantation process is continued to form a well region 240 having a second conductivity type in the substrate 20, and the well region 240 extends from the inside of the substrate 20 to the upper surface of the substrate 20. Compared with the drift region 250, the well region 240 has a different implantation area and an implanted dopant. The second conductivity type is, for example, p-type, that is, a p-type well region is formed by implanting boron or boron difluoride (BF2). The implantation density and implantation depth of the p-type dopant can be set according to the size and characteristics of the LDMOS transistor. After the implantation of the p-type dopant is completed, the mask is removed.

[0080] After the implantation process for forming the drift region 250 and the well region 240 is completed, an ion diffusion process may be performed using a thermal annealing process to diffuse and stabilize the implanted dopants, thereby forming the drift region 250 and the well region 240. The specific thermal treatment time and temperature may be set according to the size and characteristics of the LDMOS transistor.

[0081] like Fig. 20 As shown, a gate oxide layer 222 and a gate 261 are formed. Specifically, the second oxide layer 211 is removed, an oxide layer and a gate material layer are regrown, and the oxide layer and the gate material layer are patterned to form the gate oxide layer 222 and the gate 261 . Fig. 22 Schematic diagram of a semiconductor device including an LDMOS transistor. Figures 13 to 21 For the corresponding Fig. 22 Schematic diagram of the cross-section of each step of BB'. Fig.21 and Fig. 22 As shown, a sidewall 270, a source region 280 and a drain region 290 are formed. The sidewall 270 is located on both sides of the gate 261. In this embodiment, the gate 261 extends from above the gate oxide layer 222 along the drift region 250 to the preset drain region 290, and covers the upper surface of the LOCOS 210, and part of the surface of the LOCOS 210 is exposed. The material of the gate oxide layer 222 is, for example, silicon oxide and / or silicon oxynitride, etc. In this embodiment, the positive projection of the gate 261 and the drift region 250 on the upper surface of the substrate 20 is partially overlapped, a part of the gate oxide layer 222 is arranged on the well region 240, and another part of the gate oxide layer 222 is arranged on the drift region 250, and the drift region 250 is connected to the conductive channel of the LDMOS transistor. The material of the gate 261 is, for example, doped polysilicon, with a thickness of about 100nm to 200nm. In this embodiment, the gate 261 is used to construct the field plate of the LDMOS transistor. LDMOS transistors have a large breakdown voltage and a small on-resistance (Ron). LDMOS transistors are widely used in switching regulators due to their balanced performance between on-resistance and breakdown voltage.

[0082] exist Fig. 20 Based on the structure shown in FIG. 1 , an implantation process can be used to implant n-type dopants into the substrate 20 at corresponding positions on both sides of the gate 261 to form the following structures: Fig.21 The source region 280 and the drain region 290 are shown. The source region 280 is located on the top of the substrate 20 and surrounded by the well region 240 , the drain region 290 is located on the top of the substrate 10 and surrounded by the drift region 250 , and the drain region 290 is spaced a distance from the LOCOS 210 .

[0083] The manufacturing method of the semiconductor device including the LDMOS transistor provided by the present invention forms LOCOS210 on the substrate. The LOCOS210 field oxygen structure can avoid the breakdown caused by the local concentration of the depletion electric field in the drift region below, which helps to improve the breakdown voltage, and does not affect the conduction interface between the drain region and the source region in the conduction mode, which helps to obtain a smaller on-resistance. In addition, the manufacturing method makes the LOCOS process more compatible with the CMOS process.

[0084] The LOCOS of the present invention is formed before shallow trench isolation (STI), which avoids the problem of local corrosion of the circumference of the shallow trench isolation caused by the LOCOS process to form a groove. In the same photolithography process of etching a portion of the thickness of the substrate to form a groove, the substrate is also etched to form an alignment mark groove. The groove and the alignment mark groove are carried out in the same exposure and etching process, which can save one exposure and etching. By controlling the etching depth of the groove and the oxidation growth thickness of the LOCOS, the upper surface of the LOCOS is made close to the upper surface of the substrate, and the LOCOS protrusion (the part of the upper surface of the LOCOS that is higher than the substrate is a protrusion) can be basically eliminated, avoiding the LOCOS protrusion from affecting the ion implantation of the well region and the drift region, and avoiding the LOCOS protrusion from affecting the subsequent gate exposure and etching process window.

[0085] The present invention also provides a semiconductor device comprising an LDMOS transistor, such as Fig.21 and Fig. 22 As shown, including:

[0086] A substrate 20 having a groove formed therein;

[0087] A LOCOS 210 is formed in the groove;

[0088] Shallow trench isolation 230, wherein the shallow trench isolation 230 is formed in the substrate on both sides of the LOCOS;

[0089] A drift region 250 , wherein the drift region 250 is of a first conductivity type, the drift region 250 extends from the inside of the substrate 20 to the upper surface of the substrate, and the drift region 250 surrounds the LOCOS 210 located in the trench;

[0090] A gate oxide layer 222 and a gate 261 are sequentially located on the substrate 20 ; the gate 261 covers the gate oxide layer 222 and a portion of the LOCOS 210 .

[0091] The height difference between the upper surface of the LOCOS 210 and the upper surface of the substrate 20 is less than or equal to 200 angstroms.

[0092] The drift region 250 of the LDMOS transistor is disposed in the substrate 20. The drift region 250 is used to drift carriers by forming a depletion electric field when the LDMOS transistor is working. The drift region 250 has a first conductivity type (e.g., n-) doping, which is opposite to the doping type of the substrate 20. The first conductivity type doping concentration of the drift region 250 is, for example, 5×10 16 / cm 3 Up to 5×10 18 / cm 3 the following.

[0093] The LDMOS transistor further includes a source region 280 and a drain region 290 disposed on the top of the substrate 20 (near the substrate surface). In this embodiment, the drift region 250 is located deeper than the source region 280 and the drain region 290 and surrounds the drain region 290. As an example, the source region 280 and the drain region 290 of the LDMOS transistor are asymmetrically disposed on both sides of the gate 261, the drain region 290 is disposed at a certain distance from the gate 261, and the drift region 250 is disposed at one end of the gate 261 facing the drain region 290. When the LDMOS transistor of this structure is blocked, a high voltage is applied to the drain region 290. However, in another embodiment, the source region 280 and the drain region 290 can also be symmetrically disposed on both sides of the gate 261, and a high voltage can also be applied to the source region 280 when blocked.

[0094] Specifically, the source region 280 and the drain region 290 of the LDMOS transistor have a first conductivity type, and the first conductivity type doping concentration of the source region 280 and the drain region 290 is greater than that of the drift region 250 (the doping of the source region and the drain region is, for example, represented as n+), and the drain region 290 is arranged at the top of the substrate 20 and surrounded by the drift region 250. A well region 240 of a second conductivity type is also arranged in the substrate 20 (the doping of the well region is, for example, represented as p), and the well region 240 extends from the substrate 20 to the upper surface of the substrate 10 at a position different from the drift region 250 (that is, it does not overlap with the drift region 250), and the source region 280 is located at the top of the substrate 20 and surrounded by the well region 240. Compared with the source region 280 and the drain region 290, the drift region 250 and the well region 240 are located at a deeper position in the substrate 20.

[0095] The gate oxide layer 222 and the gate 261 of the LDMOS transistor are sequentially stacked on the upper surface of the substrate 10. The source region 280 and the drain region 290 are respectively arranged on both sides of the gate 261. In this embodiment, the drift region 250 and the gate oxide layer 222 partially overlap in the positive projection on the upper surface of the substrate 20, that is, part of the gate oxide layer 222 covers the surface of the substrate 20 of the drift region 250. In addition, at a position different from the drift region 250, the well region 240 and the gate oxide layer 222 partially overlap in the positive projection on the upper surface of the substrate 20, that is, part of the gate oxide layer 222 covers the surface of the substrate 20 of the well region 240. The drift region 250 of the LDMOS transistor can be regarded as extending from the gate 261 to the direction of the drain region 290 within the range of the substrate 20 deeper than the drain region 290, and wrapping the drain region 290. When the gate 261 of the LDMOS transistor is properly biased, a conductive channel (eg, n-type) is formed between the source region 280 and the drain region 290 , specifically extending from the source region 280 to the drift region 250 .

[0096] In order to alleviate the depletion electric field concentration formed in the drift region 250 (especially the upper surface area of ​​the substrate 10 near the gate 261) in the blocking state (for example, the drain region is high voltage, and the gate and source region voltages are 0V), in the semiconductor device of the embodiment of the present invention, the LDMOS transistor is provided with LOCOS210 as a field oxide film above the substrate 20 of the drift region 250, LOCOS210 is used as a dielectric of the capacitor, and the gate 261 portion located directly above the LOCOS210 is used as a field plate, and a field plate structure is formed between the field plate and the substrate 20. When the thickness of LOCOS210 increases, the breakdown voltage increases. A furnace tube oxidation process can be used to form LOCOS210 between the field plate and the substrate as a dielectric of the capacitor. The field plate structure is arranged in the upper area of ​​the substrate 20 between the gate 261 and the drain region 290, and the drain region 290 is spaced a set distance from LOCOS210. The set distance can be specifically adjusted according to the structure and characteristics of the LDMOS transistor.

[0097] According to the need of the field plate structure to alleviate the depletion electric field concentration in the drift region below, the size of the field oxide film LOCOS210 can be adjusted. The material of the sidewall 270 is, for example, silicon oxide. The present invention is not limited to this, and the shape of the field oxide film LOCOS210 can be adjusted according to the need to alleviate the depletion electric field concentration in the drift region 250. By controlling the etching depth of the trench and the oxidation growth thickness of the LOCOS, the upper surface of the LOCOS is made close to the upper surface of the substrate, and the LOCOS protrusion (the part of the LOCOS that is higher than the upper surface of the substrate is a protrusion) can be basically eliminated, avoiding the LOCOS protrusion from affecting the ion implantation of the well region and the drift region, and avoiding the LOCOS protrusion from affecting the subsequent gate exposure and etching process window.

[0098] In the semiconductor device including the LDMOS transistor of the embodiment of the present invention, the LDMOS transistor has a field plate structure, which includes a field plate located above the drift region 250 of the substrate 20 and a field oxide film LOCOS210 located between the field plate and the substrate 20. In the blocking state, a field plate electric field is formed in the LOCOS210 region. The LOCOS210, as a dielectric, can avoid local concentration of the electric field in the depletion region in the drift region 250 below and cause breakdown, which helps to increase the breakdown voltage.

[0099] In summary, the present invention provides a semiconductor device including an LDMOS transistor and a manufacturing method thereof, comprising: providing a substrate, etching a portion of the thickness of the substrate to form a trench; performing an oxidation process to form a LOCOS in the trench; forming a shallow trench isolation, forming the shallow trench isolation in the substrate on both sides of the LOCOS; forming a drift region with a first conductivity type, the drift region extending from the inside of the substrate to the upper surface of the substrate, the drift region surrounding the LOCOS located in the trench; forming a gate oxide layer and a gate located on the substrate in sequence; the gate covering the gate oxide layer and a portion of the LOCOS. The LOCOS of the present invention is formed before shallow trench isolation (STI), avoiding the problem of local corrosion of the periphery of the shallow trench isolation caused by the LOCOS process to form a groove.

[0100] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0101] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device comprising an LDMOS transistor, characterized in that: include: Providing a substrate, and sequentially forming an oxide layer 1 and a nitride layer 1 on the surface of the substrate, and etching the nitride layer 1, the oxide layer 1 and a portion of the thickness of the substrate to form a groove; Performing an oxidation process to form LOCOS in the trench, then removing the nitride layer 1 and the oxide layer 1 and cleaning the interface between the oxide layer 1 and the substrate; After cleaning the interface between the oxide layer 1 and the substrate, shallow trench isolation is formed, and the shallow trench isolation is formed in the substrate on both sides of the LOCOS; forming a drift region of a first conductivity type, the drift region extending from within the substrate to an upper surface of the substrate, the drift region surrounding the LOCOS located in the trench; forming a gate oxide layer and a gate sequentially located on the substrate; The gate covers the gate oxide layer and a portion of the LOCOS.

2. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 1, wherein: In the same photolithography process of etching a portion of the thickness of the substrate to form a groove, the substrate is also etched to form an alignment mark recess.

3. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 1, wherein: By controlling the etching depth of the trench and the oxidation growth thickness of the LOCOS, the upper surface of the LOCOS finally formed is made close to the upper surface of the substrate.

4. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 3, wherein: The height difference between the upper surface of the LOCOS and the upper surface of the substrate formed finally is less than or equal to 200 angstroms.

5. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 2, wherein: Also includes: Etching the first nitride layer, the first oxide layer and a portion of the substrate to form the trench and the alignment mark groove; After forming the LOCOS, removing the first nitride layer and the first oxide layer, and regrowing the second oxide layer on the substrate; Before forming the shallow trench isolation, a second nitride layer is formed, and the second nitride layer covers the LOCOS and the second oxide layer.

6. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 5, wherein: Forming shallow trench isolation includes: Etching the second nitride layer, the second oxide layer and a partial thickness of the substrate to form an STI trench; filling the oxide layer in the STI trench to form the shallow trench isolation; The second nitride layer is removed.

7. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 1, wherein: After forming the LOCOS and before forming the shallow trench isolation, the method further includes: Dopants of the first conductivity type are implanted into the substrate to form a deep well; the deep well extends from the inside of the substrate to the upper surface of the substrate, and the deep well surrounds the drift region.

8. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 7, wherein: After forming the shallow trench isolation and before forming the gate oxide layer and the gate, the method further includes: A well region having a second conductivity type is formed, wherein the second conductivity type is opposite to the first conductivity type, the well region extends from within the substrate to an upper surface of the substrate, and the deep well surrounds the well region.

9. The method for manufacturing a semiconductor device comprising an LDMOS transistor according to claim 8, wherein: After forming the gate oxide layer and the gate, the method further comprises: forming a source region and a drain region; the source region and the drain region are disposed on both sides of the gate and are both of the first conductivity type; the doping concentration of the drain region is greater than that of the drift region; The source region is located at the top of the substrate and surrounded by the well region, the drain region is located at the top of the substrate and surrounded by the drift region, and the drain region is spaced a distance from the LOCOS.

10. A semiconductor device comprising an LDMOS transistor, characterized in that: The semiconductor device is formed by the manufacturing method according to any one of claims 1 to 9, comprising: a substrate having a groove formed therein; A LOCOS is formed in the groove; Shallow trench isolation, wherein the shallow trench isolation is formed in the substrate on both sides of the LOCOS; A drift region, the drift region is of a first conductivity type, the drift region extends from inside the substrate to an upper surface of the substrate, and the drift region surrounds the LOCOS located in the trench; A gate oxide layer and a gate are sequentially located on the substrate; the gate covers the gate oxide layer and a portion of the LOCOS.

11. The semiconductor device comprising an LDMOS transistor according to claim 10, wherein: A height difference between the upper surface of the LOCOS and the upper surface of the substrate is less than or equal to 200 angstroms.

12. The semiconductor device comprising an LDMOS transistor according to claim 10, wherein: Also includes: a well region, the well region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the well region extending from within the substrate to an upper surface of the substrate; a source region and a drain region; the source region and the drain region are arranged on both sides of the gate and are both of the first conductivity type; the doping concentration of the drain region is greater than that of the drift region; The source region is located at the top of the substrate and surrounded by the well region, the drain region is located at the top of the substrate and surrounded by the drift region, and the drain region is spaced a distance from the LOCOS.

Images