A subtraction circuit
By designing a subtraction circuit that includes a transmission gate and a clamping circuit, the problems of large area and power consumption in traditional ADC sampling calculations are solved, and the efficiency and accuracy of in-memory calculations are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2022-08-02
- Publication Date
- 2026-06-16
AI Technical Summary
When convolutional neural networks perform in-memory computation, traditional ADC sampling computation suffers from problems such as large area occupation and high power consumption, which limits hardware energy efficiency and acceleration speed.
A subtraction circuit including a first transmission gate, a second transmission gate, a computational capacitor, and a clamping circuit is designed. Voltage subtraction is achieved by acquiring and generating the level difference, and the computational power consumption is reduced by using the clamping circuit.
It enables voltage subtraction with a smaller area overhead, improving the efficiency and accuracy of in-memory computing and reducing power consumption.
Smart Images
Figure CN115167812B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic component technology, and in particular to a subtraction circuit applied to in-memory calculation. Background Technology
[0002] Convolutional Neural Networks (CNNs) have achieved unprecedented accuracy improvements in large-scale recognition tasks. However, algorithm complexity and memory access limitations restrict the energy efficiency and speedup of CNN hardware. Furthermore, when using in-memory computation, traditional ADC sampling computation often suffers from problems such as large footprint and high power consumption. Summary of the Invention
[0003] To address the aforementioned problems in the existing technology, this invention provides a subtraction circuit for in-memory computation.
[0004] To achieve the above objectives, the present invention provides the following solution:
[0005] A subtraction circuit includes: a first transmission gate, a second transmission gate, a calculation capacitor, and a clamping circuit;
[0006] Both the first transmission gate and the second transmission gate are connected to the computational capacitor; the computational capacitor is connected to the clamping circuit.
[0007] The first transmission gate is used to acquire a first level; the second transmission gate is used to acquire a second level; the clamping circuit is used to generate a clamping level; and the calculation capacitor is used to obtain a level difference based on the first level, the second level, and the clamping level.
[0008] Preferably, the clamping circuit includes: a control terminal, a first NMOS transistor, and an inverter;
[0009] The control terminal is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the other end of the computational capacitor; the source of the first NMOS transistor is connected to the first terminal of the inverter; the second terminal of the inverter is connected to the connection point between the drain of the first NMOS transistor and the other end of the computational capacitor; and the third terminal of the inverter is grounded.
[0010] Preferably, the inverter includes a PMOS transistor, a second NMOS transistor, and a power supply;
[0011] The gates of the PMOS transistor and the second NMOS transistor are both connected to the second terminal of the inverter; the drains of the PMOS transistor and the second NMOS transistor are both connected to the first terminal of the inverter; the source of the PMOS transistor is connected to the power supply; and the source of the second NMOS transistor is grounded to the third terminal of the inverter.
[0012] Preferably, the input terminal of the first transmission gate is used to acquire the first level; the output terminal of the first transmission gate is connected to one end of the computational capacitor; and the control terminal of the first transmission gate is used to acquire the first control level.
[0013] Preferably, the input terminal of the second transmission gate is used to acquire the second level; the output terminal of the second transmission gate is connected to one end of the computational capacitor; and the control terminal of the second transmission gate is used to acquire the second control level.
[0014] Preferably, when the first control level and the input level of the control terminal in the clamping circuit are both high, and the second control level is low, the potential at one end of the capacitor is the first level, and the potential at the other end of the capacitor is the clamping level.
[0015] Preferably, when the first control level and the input level of the control terminal are both low, and the second control level is high, the potential at one end of the calculation capacitor jumps from the first level to the second level, and the potential at the other end of the calculation capacitor changes with the potential at one end of the calculation capacitor.
[0016] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0017] The subtraction circuit provided by this invention includes: a first transmission gate, a second transmission gate, a computation capacitor, and a clamping circuit; both the first and second transmission gates are connected to the computation capacitor; the computation capacitor is connected to the clamping circuit. Based on this structure, this invention can obtain the level difference based on the first level, the second level, and the clamping level, achieving the purpose of subtracting two voltages with a small area overhead. It has the characteristics of simple structure and can reduce computational power consumption, thereby improving in-memory computation efficiency. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the subtraction circuit provided by the present invention;
[0020] Figure 2 A schematic diagram of the structure of the first transmission gate or the second transmission gate provided by the present invention;
[0021] Figure 3 The timing diagram provided for embodiments of the present invention. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] The purpose of this invention is to provide a subtraction circuit for in-memory computation that can solve the problems of large area occupation and high power consumption in traditional ADC sampling computation, while also improving in-memory computation efficiency.
[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] The subtraction circuit provided by this invention is based on the principle of a comparator, such as... Figure 1 As shown, the subtraction circuit includes: a first transmission gate T1, a second transmission gate T2, a calculation capacitor Cm, and a clamping circuit.
[0026] Both the first transmission gate T1 and the second transmission gate T2 are connected to the computational capacitor Cm. The computational capacitor Cm is connected to the clamping circuit.
[0027] The first transmission gate T1 is used to acquire the first level V1. The second transmission gate T2 is used to acquire the second level V2. The clamping circuit is used to generate the clamping level Vx. The calculation capacitor Cm is used to obtain the level difference based on the first level V1, the second level V2, and the clamping level Vx.
[0028] Specifically, based on Figure 2 The transmission gate structure shown has an input terminal of the first transmission gate T1 used to acquire a first level V1. The output terminal of the first transmission gate T1 is connected to one end of the calculation capacitor Cm. The control terminal RST0 of the first transmission gate T1 is used to acquire a first control level.
[0029] The input terminal of the second transmission gate T2 is used to obtain the second level V2. The output terminal of the second transmission gate T2 is connected to one end of the calculation capacitor Cm. The control terminal RST1 of the second transmission gate T2 is used to obtain the second control level.
[0030] Furthermore, in order to improve computational efficiency and accuracy, such as Figure 1 As shown, the clamping circuit includes: a control terminal RSTB, a first NMOS transistor NM1, and an inverter.
[0031] The control terminal RSTB is connected to the gate of the first NMOS transistor NM1. The drain of the first NMOS transistor NM1 is connected to the other end of the calculation capacitor Cm. The source of the first NMOS transistor NM1 is connected to the first terminal of the inverter. The second terminal of the inverter is connected to the junction point (i.e., the clamping level Vx point) between the drain of the first NMOS transistor NM1 and the other end of the calculation capacitor Cm. The third terminal of the inverter is grounded.
[0032] The inverter consists of a PMOS transistor PM1, a second NMOS transistor NM2, and a power supply VDD.
[0033] The gates of PMOS transistor PM1 and the second NMOS transistor NM2 are both connected to the second terminal of the inverter. The drains of PMOS transistor PM1 and the second NMOS transistor NM2 are both connected to the first terminal of the inverter. The source of PMOS transistor PM1 is connected to the power supply. The source of the second NMOS transistor NM2 is connected to the third terminal of the inverter, meaning the source of the second NMOS transistor NM2 is grounded. Figure 1 In this diagram, G represents the gate, D represents the drain, and S represents the source.
[0034] Based on such Figure 3 The timing diagram shown illustrates the specific working principle of the circuit structure provided by the present invention.
[0035] The operation is divided into two phases: In the first phase, when the control terminals RST0 and RSTB are at level 1 and the control terminal RST1 is at level 0, the first NMOS transistor NM1 is turned on. At this time, the input and output of the inverter are formed by the PMOS transistor PM1 and the second NMOS transistor NM2, creating a feedback loop that generates a clamping level Vx. The potential of the clamping level Vx is clamped at an intermediate level of approximately 1 / 2 VDD. Simultaneously, the potential at one end of the calculation capacitor Cm is at the first level V1. In the second phase, the control terminals RST0 and RSTB are both at level 0, and the control terminal RST1 is at level 1. At this time, the first NMOS transistor NM1 is turned off, there is no feedback path, and the clamping level Vx is no longer clamped. At this time, the second transmission gate T2 is turned on, and the potential at one end of the calculation capacitor Cm jumps from the first level V1 to the second level V2. Based on the inherent properties of the capacitor, the potential at the other end of the capacitor is calculated as the clamping level Vx. After the clamping level Vx is released, it will change with the change at one end of the capacitor, resulting in a change equivalent to V1-V2. This change is the deviation value relative to the intermediate level clamped in the first stage. In other words, the deviation of Vx relative to 1 / 2VDD is the value of V1-V2.
[0036] Based on the above description, the advantages of the circuit provided by the present invention are: it achieves the subtraction of two voltages with a small area overhead, has a simple structure, can be applied multiple times in in-memory computing arrays, and solves the problem of large area and power consumption overhead caused by the implementation of this function in traditional ADCs when subtracting two voltages.
[0037] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0038] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A subtraction circuit, characterized in that, include: First transmission gate, second transmission gate, calculated capacitance and clamping circuit; Both the first transmission gate and the second transmission gate are connected to the computational capacitor; The calculation capacitor is connected to the clamping circuit; The first transmission gate is used to acquire the first level; The second transmission gate is used to obtain the second level; The clamping circuit is used to generate a clamping level; The calculation capacitor is used to obtain the level difference based on the first level, the second level, and the clamping level; The clamping circuit includes: a control terminal, a first NMOS transistor, and an inverter; The control terminal is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the other end of the computational capacitor; the source of the first NMOS transistor is connected to the first terminal of the inverter; the second terminal of the inverter is connected to the connection point between the drain of the first NMOS transistor and the other end of the computational capacitor; the third terminal of the inverter is grounded. The input terminal of the first transmission gate is used to acquire the first level; the output terminal of the first transmission gate is connected to one end of the computational capacitor; the control terminal of the first transmission gate is used to acquire the first control level. The input terminal of the second transmission gate is used to obtain the second level; the output terminal of the second transmission gate is connected to one end of the calculation capacitor; the control terminal of the second transmission gate is used to obtain the second control level.
2. The subtraction circuit according to claim 1, characterized in that, The inverter includes a PMOS transistor, a second NMOS transistor, and a power supply; The gates of the PMOS transistor and the second NMOS transistor are both connected to the second terminal of the inverter; the drains of the PMOS transistor and the second NMOS transistor are both connected to the first terminal of the inverter; the source of the PMOS transistor is connected to the power supply; and the source of the second NMOS transistor is grounded to the third terminal of the inverter.
3. The subtraction circuit according to claim 1, characterized in that, When the first control level and the input level of the control terminal in the clamping circuit are both high, and the second control level is low, the potential at one end of the capacitor is calculated to be the first level, and the potential at the other end of the capacitor is calculated to be the clamping level.
4. The subtraction circuit according to claim 3, characterized in that, When both the first control level and the input level of the control terminal are low, and the second control level is high, the potential at one end of the calculation capacitor jumps from the first level to the second level, and the potential at the other end of the calculation capacitor changes with the potential at one end of the calculation capacitor.