arithmetic device

Abstract

According to an embodiment, an arithmetic device includes an arithmetic element section and a control section. The arithmetic element section includes a first element and a second element. The first element includes a first conductive member and a first laminate. The first conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first laminate includes a first magnetic layer. The second element includes a second conductive member and a second laminate. The second conductive member includes a fourth portion, a fifth portion, and a sixth portion between the fourth portion and the fifth portion. The second laminate includes a second magnetic layer. The second portion and the fourth portion are electrically connected. The control section is capable of performing an XNOR operation of a first input and a second input. The first input corresponds to a resistance of the first laminate and the second laminate. The second input corresponds to a potential of the first magnetic layer and the second magnetic layer. An arithmetic device having a simple structure is provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to computing devices. Background Technology

[0002] There are computing devices that use magnetic components. In such computing devices, a simpler structure is desired.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 6545853 Summary of the Invention

[0006] Embodiments of the present invention provide a computing device with a simple structure.

[0007] According to an embodiment of the present invention, the computing device includes a computing element section and a control section. The computing element section includes a first element and a second element. The first element includes a first conductive member and a first laminate. The first conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first laminate includes a first magnetic layer and a first opposing magnetic layer disposed between the third portion and the first magnetic layer. The second element includes a second conductive member and a second laminate. The second conductive member includes a fourth portion, a fifth portion, and a sixth portion between the fourth portion and the fifth portion. The second laminate includes a second magnetic layer and a second opposing magnetic layer disposed between the sixth portion and the second magnetic layer. The second portion is electrically connected to the fourth portion. The control section is capable of performing XNOR operations on a first input and a second input. The first input corresponds to a first resistance of the first laminate and a second resistance of the second laminate. The second input corresponds to the potential of the first magnetic layer and the potential of the second magnetic layer. Attached Figure Description

[0008] Figure 1 This is a schematic perspective view illustrating the computing device of the first embodiment.

[0009] Figure 2 This is a flowchart illustrating the operation of the computing device according to the first embodiment.

[0010] Figure 3 of Figure 3 (a) and Figure 3 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0011] Figure 4 of Figure 4 (a) and Figure 4 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0012] Figure 5 of Figure 5 (a) and Figure 5 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0013] Figure 6 of Figure 6 (a) and Figure 6 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0014] Figure 7 of Figure 7 (a) and Figure 7 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0015] Figure 8 of Figure 8 (a) and Figure 8 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0016] Figure 9 of Figure 9 (a) and Figure 9 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0017] Figure 10 of Figure 10 (a) and Figure 10 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0018] Figure 11 This is a schematic diagram illustrating the operation of the computing device according to the first embodiment.

[0019] Figure 12 This is a schematic diagram illustrating the operation of the computing device according to the first embodiment.

[0020] Figure 13 of Figure 13 (a) and Figure 13 (b) is a schematic perspective view illustrating the computing device of the first embodiment.

[0021] Figure 14 This is a schematic perspective view illustrating the computing device of the second embodiment.

[0022] Figure 15 of Figure 15 (a) and Figure 15(b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0023] Figure 16 of Figure 16 (a) and Figure 16 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0024] Figure 17 of Figure 17 (a) and Figure 17 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0025] Figure 18 of Figure 18 (a) and Figure 18 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0026] Figure 19 of Figure 19 (a) and Figure 19 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0027] Figure 20 of Figure 20 (a) and Figure 20 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0028] Figure 21 of Figure 21 (a) and Figure 21 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0029] Figure 22 of Figure 22 (a) and Figure 22 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0030] Figure 23 This is a schematic diagram illustrating the operation of the computing device according to the second embodiment.

[0031] Figure 24 This is a schematic diagram illustrating the operation of the computing device according to the second embodiment.

[0032] Figure 25 of Figure 25 (a) and Figure 25 (b) is a schematic perspective view illustrating the computing device of the second embodiment.

[0033] Figure 26This is a schematic diagram illustrating the computing device of the third embodiment.

[0034] Figure 27 This is a schematic diagram illustrating the computing device of the third embodiment.

[0035] Figure 28 This is a schematic diagram illustrating the computing device of the third embodiment.

[0036] Figure 29 of Figure 29 (a) and Figure 29 (b) is a schematic diagram illustrating the computing device of an illustrative embodiment.

[0037] Figure 30 of Figure 30 (a)~ Figure 30 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0038] Figure 31 of Figure 31 (a)~ Figure 31 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0039] Figure 32 of Figure 32 (a)~ Figure 32 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0040] Figure 33 of Figure 33 (a)~ Figure 33 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0041] Figure 34 of Figure 34 (a)~ Figure 34 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0042] Figure 35 of Figure 35 (a)~ Figure 35 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0043] Figure 36 of Figure 36 (a)~ Figure 36 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0044] Figure 37 of Figure 37 (a)~ Figure 37 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0045] Figure 38 of Figure 38 (a)~ Figure 38 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0046] Figure 39 of Figure 39 (a)~ Figure 39 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0047] Figure 40 of Figure 40 (a)~ Figure 40 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0048] Figure 41 of Figure 41 (a)~ Figure 41 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0049] Figure 42 of Figure 42 (a)~ Figure 42 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0050] Figure 43 of Figure 43 (a)~ Figure 43 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0051] Figure 44 of Figure 44 (a)~ Figure 44 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0052] Figure 45 of Figure 45 (a)~ Figure 45 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0053] Symbol Explanation

[0054] 11, 12: First and second magnetic layers; 11E, 12E: First and second elements; 11m, 12m: Magnetized; 11n, 12n: First and second non-magnetic layers; 11o, 12o: First and second opposing magnetic layers; 11om, 12om: Magnetized; 11z, 12z: Magnetic layers; 21, 22: First and second conductive members; 21a~21c: First to third parts; 22d~22f: Fourth to sixth parts; 25M, 26M: First and second memory conductive members; 50: Arithmetic element section; 51: Memory element section; 70: Control section. 78a~78f: Conductive parts; 110~112, 114~116, 110a, 114a~116a, 120~122, 124~126, 120a, 124a~126a, 130~132: Computing devices; AR0: Array area; BLc1~BLc3, BLv1, BLv2: Wiring; CC: Control circuit; CN: Connection point; DAT1, DAT2: Data; DF0: Definition; E1~E4: Potentials 1 to 4; F1: Function; I12, I21, I45, I54: Orientation; IL: Input Layer; In1, In2: 1st and 2nd inputs; _In2: negation; LGR: Logic gate region; MAR: Memory array region; MG1: Magnetization structure; ML: Intermediate layer; MPR: Peripheral region for memory read circuits; MPW: Peripheral region for memory write circuits; OL: Output layer; P1: Partial; PR0: Peripheral region; PRR: Peripheral region for logic read circuits; PRW: Peripheral region for logic write circuits; Rs1, Rs2: Result; S1, S2: 1st and 2nd layer stack; SA1: Sensing amplifier; SA2: Memory read amplifier Amplifier; SEL1, SEL2: Selectors; SM1, SM2: Memory stack 1 and 2; Sg1, Sg2: Signals; T1~T5: Terminals 1~5; Tr1~Tr5: Transistors 1~5; V1, V2: Potentials; VD: Value; WD1: Write driver; WD2: Write driver for memory; WL1, WL2: Wiring; WS1: Product operation; a1~a3, b1~b3, c1~c3, d1~d3: Status; ic1~ic4: Currents 1~4; w1~w4: Weights; x1~x4: Inputs. Detailed Implementation

[0055] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0056] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as the actual situation. Even when representing the same part, the dimensions and ratios of each other may sometimes be represented differently due to different accompanying drawings.

[0057] In this application specification and the figures, the same symbols are used for the same elements as those mentioned above with respect to the figures already shown, and detailed descriptions are appropriately omitted.

[0058] (First Embodiment)

[0059] Figure 1 This is a schematic perspective view illustrating the computing device of the first embodiment.

[0060] like Figure 1 As shown, the computing device 110 of the embodiment includes a computing element unit 50 and a control unit 70. The computing element unit 50 includes a first element 11E and a second element 12E.

[0061] The first element 11E includes a first conductive member 21 and a first laminate S1. The first conductive member 21 includes a first portion 21a, a second portion 21b, and a third portion 21c. The third portion 21c is located between the first portion 21a and the second portion 21b.

[0062] The first layer stack S1 includes a first magnetic layer 11 and a first opposing magnetic layer 11o. The first opposing magnetic layer 11o is located between the third part 21c and the first magnetic layer 11.

[0063] For example, the direction from part 1 21a to part 2 21b is defined as the X-axis direction. A direction perpendicular to the X-axis direction is defined as the Z-axis direction. A direction perpendicular to both the X-axis and Z-axis directions is defined as the Y-axis direction.

[0064] From the direction of the third part 21c toward the first magnetic layer 11, for example, along the Z-axis.

[0065] In this example, the first stack S1 also includes a first non-magnetic layer 11n. The first non-magnetic layer 11n is located between the first opposing magnetic layer 11o and the first magnetic layer 11.

[0066] In this example, the first stack S1 also includes a magnetic layer 11z. A first magnetic layer 11 exists between the third part 21c and the magnetic layer 11z.

[0067] The second element 12E includes a second conductive member 22 and a second laminate S2. The second conductive member 22 includes a fourth portion 22d, a fifth portion 22e, and a sixth portion 22f. The sixth portion 22f is located between the fourth portion 22d and the fifth portion 22e.

[0068] The second layer stack S2 includes a second magnetic layer 12 and a second opposing magnetic layer 12o. The second opposing magnetic layer 12o is located between the sixth part 22f and the second magnetic layer 12.

[0069] From the direction of the 6th part 22f toward the 2nd magnetic layer 12, for example, along the Z-axis.

[0070] In this example, the second stack S2 also includes a second non-magnetic layer 12n. The second non-magnetic layer 12n is located between the second opposing magnetic layer 12o and the second magnetic layer 12.

[0071] In this example, the second stack S2 also includes a magnetic layer 12z. A second magnetic layer 12 exists between part 6 22f and the magnetic layer 12z.

[0072] The first stack S1 and the second stack S2 include, for example, MTJ (Magnetic Tunnel Junction).

[0073] Part 21b is electrically connected to Part 42d. In this example, the arithmetic device 110 includes a conductive part 78f. The conductive part 78f electrically connects Part 21b and Part 42d. Regarding the material of the conductive part 78f, for example, the materials of the first conductive member 21 and the second conductive member 22 can also be used.

[0074] The control unit 70 is electrically connected to the connection point (terminal 5 T5) of the conductive part 78f via the conductive part 78e.

[0075] For example, the control unit 70 is electrically connected to the first part 21a via the conductive part 78a. For example, the control unit 70 is electrically connected to the second part 21b via the conductive part 78e. The control unit 70 can supply a first current ic1 to the first conductive member 21 via these conductive parts.

[0076] For example, the control unit 70 is electrically connected to the fifth part 22e via the conductive part 78c. For example, the control unit 70 is electrically connected to the fourth part 22d via the conductive part 78e. The control unit 70 can supply a second current ic2 to the second conductive member 22 via these conductive parts.

[0077] The control unit 70 is electrically connected to the first magnetic layer 11 via the conductive part 78b. The control unit 70 can set the potential of the first magnetic layer 11. The potential of the first magnetic layer 11 can essentially be regarded as the potential of the magnetic layer 11z or the potential of the conductive part 78b.

[0078] The control unit 70 is electrically connected to the second magnetic layer 12 via the conductive part 78d. The control unit 70 can set the potential of the second magnetic layer 12. The potential of the second magnetic layer 12 can essentially be regarded as the potential of the magnetic layer 12z or the potential of the conductive part 78d.

[0079] For example, the potential V1 of the first magnetic layer 11 can be set to either a first potential E1 or a second potential E2. The first potential E1 corresponds to a "Deactive" potential. The second potential E2 corresponds to an "Active" potential. When potential V1 is an "Active" potential, the first resistance of the first stack S1 becomes a value corresponding to the orientation of the first current ic1. When potential V1 is a "Deactive" potential, the first resistance does not substantially change even if the first current ic1 is supplied.

[0080] It is believed that the magnetic anisotropy of the first countermagnetic layer 11o changes because the potential V1 is either a "deactive" or "active" potential. Consequently, it is believed that the ease with which the orientation of the magnetization 11om of the first countermagnetic layer 11o changes.

[0081] When potential V1 is an "Active" potential, for example, the first resistance of the first laminate S1 can be changed according to the orientation of the first current ic1 flowing in the first conductive member 21. The change in resistance depends on the relationship between the orientation of the magnetization 11m of the first magnetic layer 11 and the orientation of the magnetization 11om of the first opposing magnetic layer 11o. The change in resistance is based, for example, on the magnetoresistance effect. The change in the orientation of the magnetization 11om is based, for example, on the spin Hall effect in the first conductive member 21.

[0082] For example, if the orientation of the magnetization 11om of the first opposing magnetic layer 11o contains the same component as the orientation of the magnetization 11m of the first magnetic layer 11, it is designated as a "parallel state" (P state). If the orientation of the magnetization 11om contains a component opposite to the orientation of the magnetization 11m, it is designated as an "anti-parallel state" (AP state).

[0083] For example, the potential V2 of the second magnetic layer 12 can be set to either a third potential E3 or a fourth potential E4. The third potential E3 corresponds to a "Deactive" potential. The fourth potential E4 corresponds to an "Active" potential. When potential V2 is an "Active" potential, the second resistance of the second stack S2 becomes a value corresponding to the orientation of the second current ic2. When potential V2 is a "Deactive" potential, the second resistance does not substantially change even if the second current ic2 is supplied.

[0084] It is believed that because potential V2 is either a "deactive" or "active" potential, the magnetic anisotropy of the second opposing magnetic layer 12o changes. Consequently, it is believed that the ease with which the orientation of the magnetization 12om of the second opposing magnetic layer 12o changes.

[0085] When potential V2 is an "Active" potential, for example, the second resistance of the second stack S2 can be changed according to the orientation of the second current ic2 flowing through the second conductive member 22. The change in resistance depends on the relationship between the orientation of the magnetization 12m of the second magnetic layer 12 and the orientation of the magnetization 12om of the second opposing magnetic layer 12o. The change in resistance is based, for example, on the magnetoresistance effect. The change in the orientation of the magnetization 12om is based, for example, on the spin Hall effect in the second conductive member 22.

[0086] For example, if the orientation of the magnetization 12om of the second opposing magnetic layer 12o contains the same component as the orientation of the magnetization 12m of the second magnetic layer 12, it is designated as a "parallel state" (P state). If the orientation of the magnetization 12om contains a component opposite to the orientation of the magnetization 12m, it is designated as an "anti-parallel state" (AP state).

[0087] "Low resistance state" corresponds to, for example, the P state. "High resistance state" corresponds to, for example, the AP state.

[0088] In the following examples, the polarity of the second potential E2 is opposite to that of the first potential E1. The polarity of the fourth potential E4 is opposite to that of the third potential E3. The polarity of the fourth potential E4 is opposite to that of the first potential E1.

[0089] The first magnetic layer 11 and the second magnetic layer 12 correspond, for example, to a reference layer. The first opposing magnetic layer 11o and the second opposing magnetic layer 12o correspond, for example, to a magnetized free layer, or, for example, to a storage layer.

[0090] Hereinafter, the polarity of the first potential E1 is set to positive ("+"), and the polarity of the second potential E2 is set to negative ("-"). In this case, the polarity of the third potential E3 is positive, and the polarity of the fourth potential E4 is negative. The polarities of the first potential E1 and the second potential E2 are, for example, based on the potential of the first conductive member 21. The polarities of the third potential E3 and the fourth potential E4 are, for example, based on the potential of the second conductive member 22.

[0091] like Figure 1 As shown, terminals T1 to T5 can also be provided. Terminal T1 is electrically connected to part 21a, for example. Terminal T2 is electrically connected to part 22e, for example. Terminal T3 is electrically connected to the first magnetic layer 11. Terminal T4 is electrically connected to the second magnetic layer 12. Terminal T5 is electrically connected to part 2b and part 22d.

[0092] The control unit 70 can be electrically connected to these terminals. As described later, a switching element such as a transistor may also be provided between the control unit 70 and these terminals. The case of connection using a switching element is also included in the "electrical connection state".

[0093] In this embodiment, the control unit 70 is capable of outputting XNOR values ​​for a first input and a second input. The first input corresponds to a first resistor in the first stack S1 and a second resistor in the second stack S2. The second input corresponds to the potential V1 of the first magnetic layer 11 and the potential V2 of the second magnetic layer 12. The potential V1 of the first magnetic layer 11 is, for example, a first potential E1 or a second potential E2. The potential V2 of the second magnetic layer 12 is, for example, a third potential E3 or a fourth potential E4.

[0094] The arithmetic device 110 with such a structure can provide an arithmetic device with a simple structure. Hereinafter, examples of the operation of the arithmetic device 110 will be described.

[0095] Figure 2 This is a flowchart illustrating the operation of the computing device according to the first embodiment.

[0096] like Figure 2 As shown, the first input and the second input are set (step S110). As described above, the first input corresponds to the first resistor of the first stack S1 and the second resistor of the second stack S2. The second input corresponds to the potential V1 of the first magnetic layer 11 and the potential V2 of the second magnetic layer 12. These inputs can be set according to the purpose of the operation.

[0097] like Figure 2 As shown, the control unit 70 performs the first supply operation (step S120). In the first supply operation, the control unit 70 supplies a first current ic1 to the first conductive member 21 and a second current ic2 to the second conductive member 22.

[0098] In one example, during the first supply operation, the first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0099] like Figure 2 As shown, the control unit 70 performs a measurement operation (step S130). During the measurement operation, the control unit 70 measures the first resistance after the supply of the first current ic1 and the second resistance after the supply of the second current ic2.

[0100] like Figure 2 As shown, the control unit 70 performs the second supply operation (step S140). In the second supply operation, after the above-mentioned measurement operation, the control unit 70 supplies a third current to the first conductive member 21 and a fourth current to the second conductive member 22.

[0101] As will be described later, in the second supply operation, when the third current has an orientation from the first part 21a to the second part 21b, the fourth current has an orientation from the fourth part 22d to the fifth part 22e. On the other hand, when the third current has an orientation from the second part 21b to the first part 21a, the fourth current has an orientation from the fifth part 22e to the fourth part 22d.

[0102] This approach allows us to obtain XNOR operation results using a simple structure and simple actions.

[0103] The following are examples of such actions.

[0104] In the following example, when the first resistor of the first stack S1 is in a "low resistance state" (first low resistance state: P) and the second resistor of the second stack S2 is in a "low resistance state" (second low resistance state: P), the first input is set to "0". When the first resistor is in a first high resistance state (AP) which is higher than the first low resistance state, and the second resistor is in a second high resistance state (AP) which is higher than the second low resistance state, the first input is set to "1".

[0105] Hereinafter, the combination of the first low resistance state and the second low resistance state is defined as either (L, L) or (P, P). The combination of the first low resistance state and the second high resistance state is defined as either (L, H) or (P, AP). The combination of the first high resistance state and the second low resistance state is defined as either (H, L) or (AP, P). The combination of the first high resistance state and the second high resistance state is defined as either (H, H) or (AP, AP).

[0106] In the following example, during the second supply operation, when the second input is "0", the first element 11E is set to "Deactive", and when the second input is "1", the first element 11E is set to "Active". On the other hand, the second element 12E is set to the "negation" of the second input. For example, when the second input is "0", the second element 12E is set to "Active", and when the second input is "1", the second element 12E is set to "Deactive".

[0107] For example, when the second input is "0", in the first supply operation (step S120), the potential V1 of the first magnetic layer 11 is the first potential E1, and the potential V2 of the second magnetic layer 12 is the fourth potential E4. When the second input is "1", in the first supply operation, the potential V1 of the first magnetic layer 11 is the second potential E2, and the potential V2 of the second magnetic layer 12 is the third potential E3.

[0108] Figure 3 (a) Figure 3 (b) Figure 4 (a) Figure 4 (b) Figure 5 (a) Figure 5 (b) Figure 6 (a) Figure 6 (b) Figure 7 (a) Figure 7 (b) Figure 8 (a) Figure 8 (b) Figure 9 (a) Figure 9 (b) Figure 10 (a) and Figure 10 (b) is a schematic perspective view illustrating the operation of the computing device according to the first embodiment.

[0109] In these figures, magnetic layers 11z and 12z are omitted.

[0110] exist Figure 3 (a) In the illustrated state a1, the first stack S1 and the second stack S2 are in a (P, P) state (e.g., a (L, L) state). When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12 in this state, the potential of the connection point (the fifth terminal T5) between the second part 21b and the fourth part 22d is about 1 / 2 of the first potential difference Va (i.e., Va / 2).

[0111] like Figure 3 (b) (State a2) As shown, in the first supply operation, the second input In2 is "0", and the potential V1 of the first magnetic layer 11 is the first potential E1. In the first supply operation, the potential V1 of the first magnetic layer 11 is set to the second input In2, and the potential V2 of the second magnetic layer 12 is set to the negation of the second input In2, "_In2". In this case, the potential V2 of the second magnetic layer 12 is the fourth potential E4. The first current ic1 supplied to the first conductive member 21 has an orientation from the second part 21b to the first part 21a. The second current ic2 supplied to the second conductive member 22 has an orientation from the fourth part 22d to the fifth part 22e.

[0112] exist Figure 4 (a) In the illustrated state b1, the first stack S1 and the second stack S2 are in a (P, P) state (e.g., a (L, L) state). In this state, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) is approximately half of the first potential difference Va (i.e., Va / 2).

[0113] like Figure 4 (b) (State b2) shows that in the first supply operation, the second input In2 is "1", the potential V1 of the first magnetic layer 11 is the second potential E2, and the potential V2 of the second magnetic layer 12 is the third potential E3. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0114] exist Figure 5 (a) In the illustrated state c1, the first stack S1 and the second stack S2 are in the (AP, AP) state (e.g., the (H, H) state). When in this state, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) is approximately 1 / 2 of the first potential difference Va (i.e., Va / 2).

[0115] like Figure 5 (b) (State c2) shows that in the first supply operation, the second input In2 is "0", the potential V1 of the first magnetic layer 11 is the first potential E1, and the potential V2 of the second magnetic layer 12 is the fourth potential E4. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0116] exist Figure 6 (a) In the illustrated state d1, the first stack S1 and the second stack S2 are in the (AP, AP) state (e.g., (H, H state). When the first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential of the connection point (the fifth terminal T5) is about 1 / 2 of the first potential difference Va (i.e., Va / 2).

[0117] like Figure 6 (b) (State d2) shows that in the first supply operation, the second input In2 is "1", the potential V1 of the first magnetic layer 11 is the second potential E2, and the potential V2 of the second magnetic layer 12 is the third potential E3. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0118] like Figure 7 As shown in (a), the measurement operation is performed in state a2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12 in state a2, the potential at the connection point (the fifth terminal T5) is higher than Va / 2 (>Va / 2). In state a2, the result obtained by the measurement operation is that the first resistance is in the first low resistance state and the second resistance is in the second high resistance state ((L,H) state).

[0119] like Figure 7 (b) As illustrated in state a3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (terminal T5). In the case of state a2, the result obtained by the measurement operation is a (L, H) state. The third current ic3 has an orientation from the first part 21a to the second part 21b, and the fourth current ic4 has an orientation from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0120] like Figure 8 As shown in (a), the measurement operation is performed in state b2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12 in state b2, the potential at the connection point (the fifth terminal T5) corresponds to Va / 2. In state b2, the result obtained by the measurement operation is that the first resistance is in the first low resistance state and the second resistance is in the second low resistance state ((L,L) state).

[0121] like Figure 8 (b) As illustrated in state b3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (terminal 5 T5). In the case of state b2, the result obtained by the measurement operation is the (L, L) state. The third current ic3 has an orientation from the second part 21b to the first part 21a. The fourth current ic4 has an orientation from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0122] like Figure 9 As shown in (a), the measurement operation is performed in state c2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) corresponds to Va / 2. In state c2, the result obtained by the measurement operation is that the first resistance is in the first high resistance state and the second resistance is in the second high resistance state ((H,H) state).

[0123] like Figure 9 (b) As illustrated in state c3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (terminal T5). In the case of state c2, the result obtained by the measurement operation is state (H, H). The third current ic3 has an orientation from the second part 21b to the first part 21a. The fourth current ic4 has an orientation from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0124] Figure 10 (a) shows the state d2 as follows Figure 7 (a) is the same as state a2. In state d2, the potential at the connection point (terminal 5 T5) is higher than Va / 2 (> Va / 2). In state a2, it is the (L, H) state.

[0125] exist Figure 10 (b) Under state d3 as shown, implement and Figure 7 (b) shows the same second supply operation as state a3. The third current ic3 has an orientation from the first part 21a to the second part 21b, and the fourth current ic4 has an orientation from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0126] As mentioned above Figure 8 (a) and Figure 9 (a) As illustrated, during the measurement operation, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (fifth terminal T5) of the second portion 21b and the fourth portion 22d sometimes corresponds to approximately 1 / 2 (Va / 2) of the first potential difference Va. In this case, as Figure 8 (b) and Figure 9 As illustrated in (b), the third current ic3 has an orientation from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0127] As mentioned above Figure 7 (a) and Figure 10 As illustrated in (a), during the measurement operation, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (fifth terminal T5) of the second portion 21b and the fourth portion 22d is sometimes higher than about half of the first potential difference Va (>Va / 2). In this case, as Figure 7 (b) and Figure 10 As shown in (b), the third current ic3 has an orientation from the first part 21a to the second part 21b, and the fourth current ic4 has an orientation from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0128] As already explained, potentials E1 and E3 correspond to the "Deactive" potentials. Potentials E2 and E4 correspond to the "Active" potentials.

[0129] When the potential V1 of the first magnetic layer 11 is the second potential E2, the state of the first resistance of the first stack S1 can be changed according to the direction of the current flowing through the first conductive member 21. When the potential V1 of the first magnetic layer 11 is the first potential E1, the state of the first resistance remains the same as before the current flowed through the first conductive member 21.

[0130] When the potential V2 of the second magnetic layer 12 is the fourth potential E4, the state of the second resistance of the second stack S2 can be changed according to the direction of the current flowing through the second conductive member 22. When the potential V2 of the second magnetic layer 12 is the third potential E3, the state of the second resistance remains the same as before the current flows through the second conductive member 22.

[0131] In the arithmetic device 110, when the first magnetic layer 11 is at the second potential E2, when a current flows through the first conductive member 21 from the second portion 21b to the first portion 21a, the first resistor becomes a first low resistance state. When the first magnetic layer 11 is at the second potential E2, when a current flows through the first conductive member 21 from the first portion 21a to the second portion 21b, the first resistor becomes a first high resistance state.

[0132] In the arithmetic device 110, when the second magnetic layer 12 is at the fourth potential E4, when a current flows through the second conductive member 22 in the direction from the fourth portion 22d to the fifth portion 22e, the second resistor becomes a second high resistance state. When the second magnetic layer 12 is at the fourth potential E4, when a current flows through the second conductive member 22 in the direction from the fifth portion 22e to the fourth portion 22d, the second resistor becomes a second low resistance state.

[0133] like Figure 1 As shown, the magnetization 11m of the first magnetic layer 11 has an orientation component at the location of the first magnetic layer 11, based on the current magnetic field having a current oriented from the first portion 21a to the second portion 21b. The magnetization 12m of the second magnetic layer 12 has an orientation component at the location of the second magnetic layer 12, based on the current magnetic field having a current oriented from the fourth portion 22d to the fifth portion 22e. The orientation of the above magnetization can also be changed, for example, according to the polarity of the spin Hall effect of the conductive member.

[0134] like Figure 7 (b) and Figure 10As shown in (b), the (H, H) state corresponds to "1". Figure 8 (b) and Figure 9 As shown in (b), the (L, L) state corresponds to "0".

[0135] Figure 11 as well as Figure 12 This is a schematic diagram illustrating the operation of the computing device according to the first embodiment.

[0136] like Figure 11 As shown, under the states (states a2, b2, c2, and d2) corresponding to the result Rs1 of the first supply action, the states (P, AP), (P, P), (AP, AP), and (P, AP) can be obtained corresponding to the first input In1 and the second input In2.

[0137] like Figure 12 As shown, under the states (states a3, b3, c3, and d3) corresponding to the result Rs2 of the second supply action, the states (AP, AP), (P, P), (P, P), and (AP, AP) can be obtained. The result Rs2 of the second supply action corresponds to the XNOR operation result of the first input In1 and the second input In2. Thus, the arithmetic unit 110 can derive the XNOR operation result of the first input In1 and the second input In2.

[0138] Figure 13 (a) and Figure 13 (b) is a schematic perspective view illustrating the computing device of the first embodiment.

[0139] like Figure 13 As shown in (a), in the computing device 111 of the embodiment, the fourth part 22d is continuous with the second part 21b. The orientation from the fourth part 22d to the fifth part 22e has a component of the orientation from the first part 21a to the second part 21b.

[0140] like Figure 13 (b) As shown, in the computing device 112 of the embodiment, the second part 21b and the fourth part 22d are electrically connected by the conductive part 78f. The direction from the fourth part 22d to the fifth part 22e has a component of the direction from the second part 21b to the first part 21a. Thus, the computing device of the embodiment may also include the conductive part 78f that electrically connects the second part 21b and the fourth part 22d.

[0141] (Second Implementation)

[0142] Figure 14 This is a schematic perspective view illustrating the computing device of the second embodiment.

[0143] like Figure 14 As shown, the arithmetic device 120 of the embodiment also includes a first element 11E, a second element 12E, and a control unit 70. In the arithmetic device 120, the orientation of the magnetization 12m of the second magnetic layer 12 is opposite to the orientation of the magnetization 11m of the first magnetic layer 11. Hereinafter, in the example of the arithmetic device 120, the description of the same parts as the arithmetic device 110 will be omitted.

[0144] In the arithmetic unit 120, when the first resistor of the first stack S1 is in a low resistance state (first low resistance state) and the second resistor of the second stack S2 is in a high resistance state (second high resistance state), the first input In1 is "0". In this case, the arithmetic element unit 50 is, for example, in a (L, H) state or in a (P, AP) state.

[0145] When the first resistor is in a high resistance state (first high resistance state) and the second resistor is in a low resistance state (second low resistance state), the first input In1 is "1". The first high resistance state is higher than the first low resistance state. The second low resistance state is lower than the second high resistance state. In this case, the arithmetic element 50 is in a (H, L) state, for example, in a (AP, P) state.

[0146] Figure 15 (a) Figure 15 (b) Figure 16 (a) Figure 16 (b) Figure 17 (a) Figure 17 (b) Figure 18 (a) Figure 18 (b) Figure 19 (a) Figure 19 (b) Figure 20 (a) Figure 20 (b) Figure 21 (a) Figure 21 (b) Figure 22 (a) and Figure 22 (b) is a schematic perspective view illustrating the operation of the computing device according to the second embodiment.

[0147] In these figures, magnetic layers 11z and 12z are omitted.

[0148] exist Figure 15 (a) and Figure 16 (a) In the illustrated states a1 and b1, the first stack S1 and the second stack S2 are in the (P, AP) state (e.g., the (L, H) state). When in this state, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) is higher than Va / 2.

[0149] like Figure 15 (b) (State a2) shows that in the first supply operation, the second input In2 is "0", and the potential V1 of the first magnetic layer 11 is the first potential E1. In this case, the potential V2 of the second magnetic layer 12 is the fourth potential E4 (negative "_In2"). The first current ic1 supplied to the first conductive member 21 has an orientation from the second part 21b to the first part 21a. The second current ic2 supplied to the second conductive member 22 has an orientation from the fourth part 22d to the fifth part 22e.

[0150] like Figure 16 (b) (State b2) shows that in the first supply operation, the second input In2 is "1", and the potential V1 of the first magnetic layer 11 is the second potential E2. In this case, the potential V2 of the second magnetic layer 12 is the third potential E3. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0151] exist Figure 17 (a) and Figure 18 (a) In the illustrated states c1 and d1, the first stack S1 and the second stack S2 are in the (AP, P) state (e.g., the (H, L) state). When in this state, when a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) is lower than Va / 2.

[0152] like Figure 17 (b) (State c2) shows that during the first supply operation, the second input In2 is "0", and the potential V1 of the first magnetic layer 11 is the first potential E1. In this case, the potential V2 of the second magnetic layer 12 is the fourth potential E4. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0153] like Figure 18 (b) (State d2) shows that in the first supply operation, the second input In2 is "1", and the potential V1 of the first magnetic layer 11 is the second potential E2. In this case, the potential V2 of the second magnetic layer 12 is the third potential E3. The first current ic1 has an orientation from the second part 21b to the first part 21a. The second current ic2 has an orientation from the fourth part 22d to the fifth part 22e.

[0154] like Figure 19As shown in (a), the measurement operation is performed in state a2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12 in state a2, the potential at the connection point (the fifth terminal T5) is essentially Va / 2 (>Va / 2). In state a2, in the results obtained by the measurement operation, the first resistance is in the first low resistance state, and the second resistance is in the second low resistance state ((L,L) state).

[0155] like Figure 19 (b) As illustrated in state a3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (terminal T5). In the case of state a2, the result obtained by the measurement operation is a (H, L) state. The third current ic3 has an orientation from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0156] like Figure 20 As shown in (a), the measurement operation is performed in state b2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12 in state b2, the potential at the connection point (the fifth terminal T5) is higher than Va / 2. In state b2, in the results obtained by the measurement operation, the first resistance is in the first low resistance state, and the second resistance is in the second high resistance state ((L,H) state).

[0157] like Figure 20 (b) As illustrated in state b3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (terminal T5). In the case of state b2, the result obtained by the measurement operation is a (L, H) state. The third current ic3 has an orientation from the second part 21b to the first part 21a. The fourth current ic4 has an orientation from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0158] like Figure 21 As shown in (a), the measurement operation is performed in state c2. When a first potential difference Va is applied to the first magnetic layer 11 with reference to the second magnetic layer 12, the potential at the connection point (the fifth terminal T5) is lower than Va / 2. In state c2, in the results obtained by the measurement operation, the first resistance is in the first high resistance state and the second resistance is in the second low resistance state ((H,L) state).

[0159] like Figure 21(b) As exemplified by the state c3, the second supply operation is performed. The second supply operation is performed based on the measurement result of the potential at the connection point (the fifth terminal T5). In the case of the state c2, the result obtained by the measurement operation is the (L, H) state. The third current ic3 has a direction from the second part 21b to the first part 21a. The fourth current ic4 has a direction from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0160] Figure 22 (a) The state d2 shown is as Figure 19 (a) shown is the same as the state a2. In the state d2, the potential at the connection point (the fifth terminal T5) is substantially Va / 2. In the state d2, it is the (L, L) state.

[0161] In Figure 22 (b) In the state d3 shown, the same second supply operation as Figure 19 (b) the state a3 shown is performed. The third current ic3 has a direction from the first part 21a to the second part 21b, and the fourth current ic4 has a direction from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0162] As described above, in as Figure 19 (a) and Figure 22 (a) exemplified, in the measurement operation, when the first potential difference Va is applied to the first magnetic layer 11 with the second magnetic layer 12 as a reference, the potential at the connection point (the fifth terminal T5) of the second part 21b and the fourth part 22d sometimes corresponds to approximately 1 / 2 of the first potential difference Va (Va / 2). In this case, as Figure 19 (b) and Figure 22 (b) exemplified, the third current ic3 has a direction from the first part 21a to the second part 21b, and the fourth current ic4 has a direction from the fourth part 22d to the fifth part 22e. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0163] As described above, in as Figure 20 (a) and Figure 21 (a) exemplified, in the measurement operation, when the first potential difference Va is applied to the first magnetic layer 11 with the second magnetic layer 12 as a reference, the potential at the connection point (the fifth terminal T5) of the second part 21b and the fourth part 22d is sometimes higher than Va / 2 (>Va / 2), or sometimes lower than Va / 2 (<Va / 2). In this case, as Figure 20(b) and Figure 21 As shown in (b), the third current ic3 has an orientation from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation from the fifth part 22e to the fourth part 22d. In the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4.

[0164] In the second embodiment, the XNOR operation result of the first input In1 and the second input In2 can also be derived. In the second embodiment, a computing device with a simple structure can also be provided.

[0165] In the second embodiment, also when the second input In2 is "0", during the first supply operation, the potential V1 of the first magnetic layer 11 is the first potential E1, and the potential V2 of the second magnetic layer 12 is the fourth potential E4 (see reference). Figure 19 (b) etc. When the second input In2 is "1", during the first supply operation, the potential V1 of the first magnetic layer 11 is the second potential E2, and the potential V2 of the second magnetic layer 12 is the third potential E3 (refer to...). Figure 20 (b) etc.

[0166] In the arithmetic device 120, when the first magnetic layer 11 is at the second potential E2, when a current flows through the first conductive member 21 from the second part 21b to the first part 21a, the first resistor becomes a first low resistance state (see reference). Figure 21 (b)). When the first magnetic layer 11 is at the second potential E2, when a current flows through the first conductive member 21 in the direction from the first part 21a to the second part 21b, the first resistance becomes a first high resistance state (see reference). Figure 22 (b)).

[0167] In the arithmetic device 120, when the second magnetic layer 12 is at the fourth potential E4, when a current flows through the second conductive member 22 in the direction from the fourth portion 22d to the fifth portion 22e, the second resistor becomes a second low resistance state (see reference). Figure 15 (b)). When the second magnetic layer 12 is at the fourth potential E4, when a current flows through the second conductive member 22 in the direction from the fifth part 22e to the fourth part 22d, the second resistor becomes a second high resistance state (see reference). Figure 21 (b)).

[0168] like Figure 14As shown, in the computing device 120, for example, the magnetization 11m of the first magnetic layer 11 has an orientation component at the position of the first magnetic layer 11 based on the current magnetic field having a current having an orientation from the first part 21a to the second part 21b. The magnetization of the second magnetic layer, for example, has an orientation component at the position of the second magnetic layer 12 based on the current magnetic field having a current having an orientation from the fifth part 22e to the fourth part 22d.

[0169] Figure 23 as well as Figure 24 This is a schematic diagram illustrating the operation of the computing device according to the second embodiment.

[0170] like Figure 23 As shown, under the states (states a2, b2, c2, and d2) corresponding to the result Rs1 of the first supply action, the states (P, P), (P, AP), (AP, P), and (P, P) can be obtained corresponding to the first input In1 and the second input In2.

[0171] like Figure 24 As shown, under the states (states a3, b3, c3, and d3) corresponding to the result Rs2 of the second supply action, the states (AP, P), (P, AP), (P, AP), and (AP, P) can be obtained. The result Rs2 of the second supply action corresponds to the XNOR operation result of the first input In1 and the second input In2. Thus, the arithmetic unit 120 can derive the XNOR operation result of the first input In1 and the second input In2.

[0172] Figure 25 (a) and Figure 25 (b) is a schematic perspective view illustrating the computing device of the second embodiment.

[0173] like Figure 25 As shown in (a), in the computing device 121 of the embodiment, the fourth part 22d is continuous with the second part 21b. The orientation from the fourth part 22d to the fifth part 22e has a component of the orientation from the first part 21a to the second part 21b.

[0174] like Figure 25 (b) As shown, in the computing device 122 of the embodiment, the second part 21b and the fourth part 22d are electrically connected by a conductive part 78f. The direction from the fourth part 22d to the fifth part 22e has a component of the direction from the second part 21b to the first part 21a. Thus, the computing device of the embodiment may also include a conductive part 78f that electrically connects the second part 21b and the fourth part 22d.

[0175] The same implementation can also be repeated in the computing devices of the first and second embodiments. Figure 2 At least a portion of the illustrated process. The control unit 70, for example, can repeatedly perform the process including the first supply action, the measurement action, and the second supply action. The repeatedly performed process may also include setting actions for the first input In1 and the second input In2 (step S110).

[0176] (Third Implementation)

[0177] Figure 26 This is a schematic diagram illustrating the computing device of the third embodiment.

[0178] like Figure 26 As shown, the computing device 130 of the embodiment includes, in addition to the computing element unit 50, wiring BLv1, wiring BLv2, wiring BLc1, wiring BLc2, wiring BLc3, wiring WL1, and wiring WL2. The computing element unit 50 has the structure described with respect to the first embodiment or the second embodiment. Multiple computing element units 50 may also be provided.

[0179] In this example, routing BLv1, routing BLv2, routing BLc1, routing BLc2, and routing BLc3 extend along the Y-axis. Routing WL1 and routing WL2 extend along the X-axis.

[0180] Wiring BLc1 can be electrically connected to the first terminal T1 of one of the multiple arithmetic element units 50 via the first transistor Tr1. Wiring BLc2 can be electrically connected to the second terminal T2 of one of the multiple arithmetic element units 50 via the second transistor Tr2. Wiring BLc3 can be electrically connected to the fifth terminal T5 of one of the multiple arithmetic element units 50 via the fifth transistor Tr5.

[0181] Wiring BLv1 can be electrically connected to the third terminal T3 of one of the multiple arithmetic element units 50 via the third transistor Tr3. Wiring BLv2 can be electrically connected to the fourth terminal T4 of one of the multiple arithmetic element units 50 via the fourth transistor Tr4.

[0182] The gates of transistors Tr1, Tr2, Tr3, and Tr4 are electrically connected to wiring WL1. The gate of transistor Tr5 is electrically connected to wiring WL2.

[0183] Routing BLv1 is, for example, the first voltage control bit line. Routing BLv2 is, for example, the second voltage control bit line. Routing BLc1 is the first write current bit line. Routing BLc2 is, for example, the second write current bit line. Routing BLc3 is, for example, the second write current bit line. Routing WL1 is, for example, the first word line. Routing WL2 is, for example, the second word line.

[0184] These wirings are electrically connected to the control unit 70. The control unit 70 performs the above-mentioned operations via these wirings. The above-mentioned operations are performed by selecting each of the multiple arithmetic element units 50. The first to fifth transistors Tr1 to Tr5 may also be included in the control unit 70.

[0185] exist Figure 26 In the example, multiple computing element units 50 are arranged in the Y-axis direction. In other embodiments, the multiple computing element units 50 may also be arranged in a matrix along both the Y-axis and X-axis directions.

[0186] Figure 27 This is a schematic diagram illustrating the computing device of the third embodiment.

[0187] like Figure 27 As shown, in the computing device 131 of the embodiment, an array region AR0 and a peripheral region PRO are provided. At least one computing element unit 50 is provided in the array region AR0. At least a portion of the control unit 70 is provided in the peripheral region PRO.

[0188] The arithmetic unit 131 includes a selector SEL1. A portion of the selector SEL1 may also be disposed in the array region AR0. A portion of the selector SEL1 may also be disposed in the peripheral region PR0. At least a portion of the selector SEL1 may also be included in the control unit 70.

[0189] In this example, the control unit 70 includes a write driver WD1, a sense amplifier SA1, and a control circuit CC. The write driver WD1 writes data to the arithmetic element unit 50. The sense amplifier SA1 detects the state of the resistors in the arithmetic element unit 50. A signal Sg1 corresponding to the state of the resistors is supplied from the sense amplifier SA1 to the control circuit CC. The control circuit CC controls the write driver WD1, for example, based on the signal Sg1. The above-described operation is performed by such a control unit 70.

[0190] The arithmetic unit 131 may also include multiple arithmetic element units 50 and a selector SEL1. The selector SEL1 can control the read operation, write operation, and logic operation of information (resistance) in the multiple arithmetic element units 50. The selector SEL1 may also be shared by at least two of the multiple arithmetic element units 50.

[0191] Selector SEL1 can also correspond to a bit selector. Selector SEL1 can also correspond to a column selector. Selector SEL1 can also include both bit selectors and column selectors.

[0192] By utilizing a structure like that of the arithmetic device 131, for example, a large number of XNOR logic gates can share fewer write drivers or fewer read amplifiers. This, for example, reduces the footprint. For example, it reduces the number of write drivers and read amplifiers in each operating state. This, in turn, significantly reduces power consumption.

[0193] Figure 28 This is a schematic diagram illustrating the computing device of the third embodiment.

[0194] like Figure 28 As shown, in the computing device 132 of the embodiment, a logic gate region LGR, a logic write circuit peripheral region PRW, a logic read circuit peripheral region PRR, a memory array region MAR, a memory write circuit peripheral region MPW, and a memory read circuit peripheral region MPR are provided.

[0195] In the logic gate region (LGR), the logic write circuit perimeter region (PRW), and the logic read circuit perimeter region (PRR), it is possible to apply... Figure 27 The structure of the array region AR0 and the surrounding region PR0 is described.

[0196] At least one memory element section 51 is provided in the memory array region MAR. The memory element section 51 includes, for example, a first memory conductive member 25M, a second memory conductive member 26M, a first memory stack SM1, and a second memory stack SM2. The structures described for the first conductive member 25M and the second memory conductive member 26M can be applied. The structures described for the first stack S1 and the second stack S2 can be applied. The memory element section 51 can, for example, store information.

[0197] Alternatively, a selector SEL2 may be provided in the arithmetic unit 132. At least a portion of the selector SEL2 may also be provided in the memory array region MAR. At least a portion of the selector SEL2 may also be provided in at least one of the memory write circuit peripheral region MPW and the memory read circuit peripheral region MPR. A memory write driver WD2 is provided in the memory write circuit peripheral region MPW. A memory read amplifier SA2 is provided in the memory read circuit peripheral region MPR. A signal Sg2 obtained from the memory read amplifier SA2 is supplied to the control circuit CC. The control circuit CC controls the memory write driver WD2, for example, based on the signal Sg2. The storage operation (read operation and write operation, etc.) in the memory array region MAR is performed by such a control unit 70.

[0198] The memory array region (MAR) can store the results of operations performed in the logic gate region (LGR), the logic write circuit perimeter region (PRW), and the logic read circuit perimeter region (PRR). The logic gate region (LGR), the logic write circuit perimeter region (PRW), and the logic read circuit perimeter region (PRR) can perform operations based on the information stored in the memory array region (MAR).

[0199] The control unit 70 may also include, for example, at least a portion of a logic write circuit peripheral area PRW, a logic read circuit peripheral area PRR, a memory write circuit peripheral area MPW, a memory read circuit peripheral area MPR, and a control circuit CC. The control unit 70 may also include, for example, at least a portion of selectors SEL1 and SEL2.

[0200] In the example of computing device 132, the logic gates section and the memory array section are located in different regions. For example, such a structure is used when setting up a large-scale memory array.

[0201] Figure 29 (a) and Figure 29 (b) is a schematic diagram illustrating the computing device of an illustrative embodiment.

[0202] These figures illustrate the application of the computing device in embodiments 1 through 3. In this example, the computing device of the embodiment is applied to a neural network. In this example, the neural network corresponds to a BNN (Binary Neural Network). Figure 29 (b) shows a magnified view Figure 29 (a) is part of P1.

[0203] like Figure 29As shown in (a), the neural network includes, for example, an input layer IL, multiple intermediate layers ML, and an output layer OL.

[0204] like Figure 29 As shown in (b), during learning and inference, the product of multiple inputs (inputs x1, x2, x3, and x4, etc.) and weights (weights w1, w2, w3, and w4, etc.) is calculated. That is, a weighted product sum operation WS1 is performed. The result of the product sum operation WS1 is output as a function F1 (e.g., a step function). This output is input to the next layer, where the sum of multiple products is calculated. The output based on the sum is determined.

[0205] For example, in the product summation operation WS1, an XNOR operation is performed. The computing device of the embodiment may also implement at least a portion of the product summation operation.

[0206] During learning and inference, information is repeatedly stored in logic gates. As devices used as logic gates, high resilience to rewriting is required. Logic gates are preferably capable of maintaining the non-volatile nature of computation results. Because the computation results are non-volatile, there is no need to store them in separate memory locations, thus reducing power consumption. Since logic gates operate repeatedly during learning and inference, low power consumption is preferable.

[0207] The computing device described in this embodiment exhibits high resistance to rewriting. It can perform operations with lower current. It can implement efficient operations using a simple structure.

[0208] Hereinafter, examples of the structure of the elements included in the computing device of the embodiments will be described.

[0209] At least one of the first conductive member 21 and the second conductive member 22 comprises at least one material selected from the group including Ta, W, Re, Os, Ir, Pt, Au, Cu, Ag and Pd. The thickness of these conductive members is, for example, 3 nm and less than 10 nm (e.g., 5 nm).

[0210] At least one of the first magnetic layer 11 and the second magnetic layer 12 comprises at least one element selected from the group including Fe and Co. These magnetic layers may also comprise a multilayer film. The multilayer film, for example, has a structure of CoFe film (2 nm thick) / Ru film (0.8 nm thick) / Co film / CoFeB film (2 nm thick).

[0211] At least one of the first opposing magnetic layer 11o and the second opposing magnetic layer 12o comprises at least one compound selected from the group including Fe and Co, and boron. The thickness of these magnetic layers is, for example, 1 nm and less than 2 nm (e.g., 1.6 nm).

[0212] At least one of the first nonmagnetic layer 11n and the second nonmagnetic layer 12n contains Mg and oxygen. The thickness of these nonmagnetic layers is, for example, 1 nm and less than 2 nm (e.g., 1.4 nm).

[0213] At least one of the magnetic layers 11z and 12z comprises at least one selected from the group including IrMn and PtMn.

[0214] The descriptions relating to the aforementioned materials and thickness are examples of how the structure of the elements contained in the computing device can be changed.

[0215] To make edge computing devices practical as key devices for IoT or AI (Artificial Intelligence), inexpensive and low-power logic gates and memory are required. For example, there is a need for non-volatile logic gates that can be implemented with simple construction as key components of Binary Neural Networks (BNNs).

[0216] In one implementation, for example, a structure using two Voltage-Controlled Spintronics Memory (VoCSM) elements is employed, employing a unique operational sequence. This allows the generation of XNORLogic-Gates.

[0217] For example, the rapid advancements in edge computing and cloud computing have necessitated energy-efficient operating memory that exchanges information with the CPU (Central Processing Unit) and MPU (Micro Processing Unit). Operating memory includes, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0218] For example, in AI and ML (Machine Learning), data is frequently rewritten at high speed during learning and inference. Such applications require high-frequency, ultra-low-power, and non-volatile working memory, as well as single-function, inexpensive, and ultra-low-power computing devices. The implementation method can be applied to such applications.

[0219] In VoCSM devices, a bias voltage is applied to the MTJ element to control the magnetic anisotropy of the magnetized free layer (e.g., the memory layer). For example, writing based on SOT (Spin Orbit Torque) is performed while in VCMA (Voltage Control of Magnetic Anisotropy) mode.

[0220] In VoCSM devices, write current flows through conductive components. These conductive components, for example, correspond to SHE (Spin-Hall Electrode). Low resistance is easily achieved in these conductive components. The write energy per bit is less than 1 / 100th of that in STT (Spin Torque Transfer) devices. High-melting-point metals such as Ta can be used as conductive components. High resistance to electromigration is achieved in these conductive components. A very high number of write cycles is possible.

[0221] In this implementation, for example, a simple structure can be used to provide XNOR logic gates as the key for the BNN. The arithmetic element unit 50 in this implementation includes, for example, a VoCSM element. VoCSM elements are non-volatile and low-power. XNOR operations can be performed using a simple construction and a simple sequence of operations. In this implementation, multiple arithmetic element units 50 may share a write driver or a sense amplifier (such as a sense amplifier). This reduces the proprietary area. For example, power consumption can be significantly reduced.

[0222] For example, in XNOR operations using edge devices that utilize BNNs in AI applications, a computing device with the aforementioned implementation method can be applied. This implementation method can provide innovation.

[0223] The implementation method may also include the following structure.

[0224] (Structure 1)

[0225] A computing device comprising:

[0226] The arithmetic unit; and

[0227] Control Department

[0228] The computing element unit includes:

[0229] A first element includes a first conductive member and a first laminate, wherein the first conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion; the first laminate includes a first magnetic layer and a first opposing magnetic layer disposed between the third portion and the first magnetic layer; and

[0230] The second element includes a second conductive member and a second laminate, wherein the second conductive member includes a fourth portion, a fifth portion, and a sixth portion between the fourth portion and the fifth portion; the second laminate includes a second magnetic layer and a second opposing magnetic layer disposed between the sixth portion and the second magnetic layer; the second portion is electrically connected to the fourth portion.

[0231] The control unit is capable of performing XNOR operations on the first input and the second input, wherein the first input corresponds to the first resistance of the first stack and the second resistance of the second stack, and the second input corresponds to the potential of the first magnetic layer and the potential of the second magnetic layer.

[0232] (Structure 2)

[0233] According to the arithmetic device described in Structure 1, wherein,

[0234] The control unit performs a first supply operation of supplying a first current to the first conductive member and a second current to the second conductive member. The first current has an orientation from the second part to the first part, and the second current has an orientation from the fourth part to the fifth part.

[0235] The operation of measuring the first resistance after the supply of the first current and the second resistance after the supply of the second current is performed.

[0236] Following the measurement operation, a second supply operation is performed, supplying a third current to the first conductive member and a fourth current to the second conductive member.

[0237] If the third current has an orientation from the first part to the second part, then the fourth current has an orientation from the fourth part to the fifth part.

[0238] When the third current has an orientation from the second part to the first part, the fourth current has an orientation from the fifth part to the fourth part.

[0239] (Structure 3)

[0240] According to the arithmetic device described in structure 2, wherein,

[0241] When the first resistor is in a first low resistance state and the second resistor is in a second low resistance state, the first input is "0".

[0242] When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second high resistance state (higher than the second low resistance state), the first input is "1".

[0243] When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential.

[0244] When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential.

[0245] The polarity of the second potential is opposite to that of the first potential.

[0246] The polarity of the fourth potential is opposite to that of the third potential.

[0247] The polarity of the fourth potential is opposite to the polarity of the first potential.

[0248] (Structure 4)

[0249] According to the arithmetic device described in structure 2, wherein,

[0250] When the first resistor is in a first low resistance state and the second resistor is in a second low resistance state, the first input is "0".

[0251] When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second high resistance state (higher than the second low resistance state), the first input is "1".

[0252] When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the third potential.

[0253] When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the fourth potential.

[0254] When the potential of the first magnetic layer is the second potential, the state of the first resistor can be changed according to the direction of the current flowing through the first conductive member.

[0255] When the potential of the first magnetic layer is the first potential, the state of the first resistor remains the same as before the current flowed through the first conductive member.

[0256] When the potential of the second magnetic layer is the fourth potential, the state of the second resistor can be changed according to the direction of the current flowing through the second conductive member.

[0257] When the potential of the second magnetic layer is the third potential, the state of the second resistor remains the same as before the current flows through the second conductive member.

[0258] (Structure 5)

[0259] According to the arithmetic device described in structure 3 or 4, wherein,

[0260] If the result obtained through the measurement action is that the first resistance is in the first low resistance state and the second resistance is in the second high resistance state,

[0261] The third current has the orientation from the first part to the second part, and the fourth current has the orientation from the fourth part to the fifth part.

[0262] In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0263] (Structure 6)

[0264] According to the arithmetic device described in structure 3 or 4, wherein,

[0265] If the result obtained through the measurement action is that the first resistor is in the first low resistance state and the second resistor is in the second low resistance state, or the first resistor is in the first high resistance state and the second resistor is in the second high resistance state, then...

[0266] The third current has the orientation from the second portion to the first portion, and the fourth current has the orientation from the fifth portion to the fourth portion.

[0267] In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0268] (Structure 7)

[0269] According to the arithmetic device described in structure 3 or 4, wherein,

[0270] In the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to approximately half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0271] In the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point of the second part and the fourth part is higher than about 1 / 2 of the first potential difference, the third current has the direction from the first part to the second part, and the fourth current has the direction from the fourth part to the fifth part. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0272] (Structure 8)

[0273] According to the arithmetic device described in any one of structures 3 to 7, wherein,

[0274] When the first magnetic layer is at the second potential, when a current flows through the first conductive member from the second part to the first part, the first resistance becomes the first low resistance state.

[0275] When the first magnetic layer is at the second potential, when a current flows through the first conductive member from the first portion to the second portion, the first resistance becomes the first high-resistance state.

[0276] When the second magnetic layer is at the fourth potential, when a current flows through the second conductive member from the fourth portion to the fifth portion, the second resistance becomes the second high-resistance state.

[0277] When the second magnetic layer is at the fourth potential, when a current flows through the second conductive member in the direction from the fifth part to the fourth part, the second resistor becomes the second low resistance state.

[0278] (Structure 9)

[0279] According to the arithmetic device described in any one of structures 3 to 8, wherein,

[0280] The magnetization of the first magnetic layer has an oriented component at the location of the first magnetic layer, based on the current magnetic field having a current oriented from the first part to the second part.

[0281] The magnetization of the second magnetic layer has an orientation component at the location of the second magnetic layer, based on the current magnetic field having a current oriented from the fourth part to the fifth part.

[0282] (Structure 10)

[0283] According to the arithmetic device described in structure 2, wherein,

[0284] When the first resistor is in a first low resistance state and the second resistor is in a second high resistance state, the first input is "0".

[0285] When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second low resistance state (lower than the second high resistance state), the first input is "1".

[0286] When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential.

[0287] When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential.

[0288] The polarity of the second potential is opposite to that of the first potential.

[0289] The polarity of the fourth potential is opposite to that of the third potential.

[0290] The polarity of the fourth potential is opposite to the polarity of the first potential.

[0291] (Structure 11)

[0292] According to the arithmetic device described in structure 2, wherein,

[0293] When the first resistor is in a first low resistance state and the second resistor is in a second high resistance state, the first input is "0".

[0294] When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second low resistance state (lower than the second high resistance state), the first input is "1".

[0295] When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the third potential.

[0296] When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the fourth potential.

[0297] When the potential of the first magnetic layer is the second potential, the state of the first resistor can be changed according to the direction of the current flowing through the first conductive member.

[0298] When the potential of the first magnetic layer is the first potential, the state of the first resistor remains the same as before the current flowed through the first conductive member.

[0299] When the potential of the second magnetic layer is the fourth potential, the state of the second resistor can be changed according to the direction of the current flowing through the second conductive member.

[0300] When the potential of the second magnetic layer is the third potential, the state of the second resistor remains the same as before the current flows through the second conductive member.

[0301] (Structure 12)

[0302] According to the arithmetic device described in structure 10 or 11, wherein,

[0303] If the result obtained through the measurement action is that the first resistance is in the first low resistance state and the second resistance is in the second high resistance state, or the first resistance is in the first high resistance state and the second resistance is in the second low resistance state, then...

[0304] The third current has the orientation from the second portion to the first portion, and the fourth current has the orientation from the fifth portion to the fourth portion.

[0305] In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0306] (Structure 13)

[0307] According to the arithmetic device described in structure 10 or 11, wherein,

[0308] If the result obtained through the measurement action is that the first resistance is in the first low resistance state and the second resistance is in the second low resistance state,

[0309] The third current has the orientation from the first part to the second part, and the fourth current has the orientation from the fourth part to the fifth part.

[0310] In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0311] (Structure 14)

[0312] According to the arithmetic device described in structure 10 or 11, wherein,

[0313] In the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to approximately half of the first potential difference, the third current has the direction from the first portion to the second portion, and the fourth current has the direction from the fourth portion to the fifth portion. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0314] In the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point of the second part and the fourth part is higher than or lower than about half of the first potential difference, the third current has the direction from the second part to the first part, and the fourth current has the direction from the fifth part to the fourth part. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential.

[0315] (Structure 15)

[0316] According to the arithmetic device described in any one of structures 10 to 14, wherein,

[0317] When the first magnetic layer is at the second potential, when a current flows through the first conductive member from the second part to the first part, the first resistance becomes the first low resistance state.

[0318] When the first magnetic layer is at the second potential, when a current flows through the first conductive member from the first portion to the second portion, the first resistance becomes the first high-resistance state.

[0319] When the second magnetic layer is at the fourth potential, when a current flows through the second conductive member from the fourth portion to the fifth portion, the second resistance becomes the second low-resistance state.

[0320] When the second magnetic layer is at the fourth potential, the second resistor becomes the second high resistance state when a current flows through the second conductive member from the fifth part to the fourth part.

[0321] (Structure 16)

[0322] According to the arithmetic device described in any one of structures 10 to 15, wherein,

[0323] The magnetization of the first magnetic layer has an oriented component at the location of the first magnetic layer, based on the current magnetic field having a current oriented from the first part to the second part.

[0324] The magnetization of the second magnetic layer has an orientation component at the location of the second magnetic layer, based on the current magnetic field having a current oriented from the fifth part to the fourth part.

[0325] (Structure 17)

[0326] According to the arithmetic device described in any one of structures 1 to 16, wherein,

[0327] The fourth part is continuous with the second part.

[0328] (Structure 18)

[0329] According to the arithmetic device described in structure 17, wherein,

[0330] The orientation from the fourth part to the fifth part has a component of the orientation from the first part to the second part.

[0331] (Structure 19)

[0332] According to the arithmetic device described in any one of structures 1 to 18, wherein,

[0333] The computing device includes a plurality of the aforementioned computing element units.

[0334] The control unit includes a selector.

[0335] The selector can select at least one of the plurality of arithmetic element units to perform the XNOR operation.

[0336] (Structure 20)

[0337] According to the arithmetic device described in structure 19, wherein,

[0338] The selector is shared by the plurality of computing elements.

[0339] Figure 30 (a)~ Figure 30 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0340] These figures illustrate the operation of the computing device 110 in the already described embodiments. Figure 30 (d) illustrates the orientation of the magnetization 11m of the first magnetic layer 11 and the orientation of the magnetization 12m of the second magnetic layer 12.

[0341] like Figure 30 As shown in (a), in the definition of DF0 in the operation, when the first resistance of the first stack S1 is in the first low resistance state (L and P) and the second resistance of the second stack S2 is in the second low resistance state (L and P), it corresponds to "0". When the first resistance of the first stack S1 is in the first high resistance state (H and AP) and the second resistance of the second stack S2 is in the second high resistance state (H and AP), it corresponds to "1".

[0342] like Figure 30 As shown in (a), when the first input In1 is “0”, it is (P, P) and when the first input In1 is “1”, it is (AP, AP).

[0343] like Figure 30 As shown in (a), in the first supply operation (step S120), a second input In2 is input to the first stack S1 (first magnetic layer 11). An inverted version of the second input In2, iIn2 (corresponding to the negation "_In2"), is input to the second stack S2 (second magnetic layer 12). In the first supply operation (step S120), when the second input In2 is "0", the potential V1 of the first magnetic layer 11 is the first potential E1 (e.g., "Deactive", e.g., positive), and the potential V2 of the second magnetic layer 12 is the fourth potential E4 (e.g., "Active", e.g., negative). In the first supply operation (step S120), when the second input In2 is "1", the potential V1 of the first magnetic layer 11 is the second potential E2 (e.g., "Active", e.g., negative), and the potential V2 of the second magnetic layer 12 is the third potential E3 (e.g., "Deactive", e.g., positive).

[0344] like Figure 30As shown in (a), in the first supply operation (step S120), the first current ic1 supplied to the first conductive member 21 has an orientation I21 from the second part 21b to the first part 21a. In the first supply operation (step S120), the second current ic2 supplied to the second conductive member 22 has an orientation I45 from the fourth part 22d to the fifth part 22e.

[0345] like Figure 30 As shown in (b), the magnetization structure MG1 of the first stack S1 and the second stack S2 is determined in accordance with the data DAT1 of the first input In1. In the result Rs1 of the first supply operation based on the first input In1 and the second input In2, the (P, AP) state, (P, P) state, (AP, AP) state, and (P, AP) state can be obtained.

[0346] like Figure 30 As shown in (b), the value VD obtained by the measurement action (step S130) becomes, according to the calculation result, a value corresponding to half of the first potential difference Va or a value different from half of the first potential difference Va. The result corresponds to the XNOR of the first input In1 and the second input In2 in the data DAT2 of the calculation result.

[0347] like Figure 30 As shown in (c), in the second supply operation (step S140), the third current ic3 is supplied to the first conductive member 21, and the fourth current ic4 is supplied to the second conductive member 22. In this example, in the operations of (0, 0) and (1, 1), the third current ic3 has an orientation I12 from the first part 21a to the second part 21b. In the operation of (1, 0), the third current ic3 has an orientation I21 from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation I54 from the fifth part 22e to the fourth part 22d. As already explained, in the second supply operation, in the data overlay, the potential V1 of the first magnetic layer 11 and the potential V2 of the second magnetic layer 12 are set to "Active" potentials. Therefore, in the result Rs2 of the second supply action (step S140), the states (AP, AP), (P, P), (P, P), and (AP, AP) can be obtained. The result Rs2 corresponds to the result of the XNOR operation.

[0348] Thus, in the computing devices of the embodiments (e.g., computing devices 110-112, 120-122, and 130-132, etc.), the control unit 70 can perform a first supply operation, a measurement operation, and a second supply operation. In the first supply operation, the control unit 70 supplies a first current ic1 to the first conductive member 21 and a second current ic2 to the second conductive member 22. In the measurement operation, the control unit 70 measures a first resistance after the supply of the first current ic1 and a second resistance after the supply of the second current ic2. In the second supply operation, after the measurement operation, the control unit supplies a third current ic3 to the first conductive member 21 and a fourth current ic4 to the second conductive member 22. The third current ic3 and the fourth current ic4 are determined based on the measurement results.

[0349] For example, the first current ic1 has an orientation I21 from the second part 21b to the first part 21a, and the second current ic2 has an orientation I45 from the fourth part 22d to the fifth part 22e. Alternatively, as described later, the first current ic1 may also have an orientation I12 from the first part 21a to the second part 21b, and the second current ic2 may also have an orientation I54 from the fifth part 22e to the fourth part 22d.

[0350] In one example (e.g., arithmetic unit 110, etc.), such as Figure 30 As shown in (a), the first current ic1 is directed towards I21, and the second current ic2 is directed towards I45. Figure 30 As shown in (a), when the first resistor is in the first low resistance state and the second resistor is in the second low resistance state, the first input In1 is "0". When the first resistor is in the first high resistance state and the second resistor is in the second high resistance state, the first input In1 is "1". Figure 30 As shown in (a), when the second input In2 is "0", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4. When the second input In2 is "1", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3. In the measurement operation, the connection point CN of the second part 21b and the fourth part 22d is measured when the first potential difference Va is applied to the first magnetic layer 11 with the second magnetic layer 12 as a reference (refer to...). Figure 30 The potential at (d)).

[0351] like Figure 30 (b) and Figure 30As shown in (c), when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 has an orientation I21 from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation I54 from the fifth part 22e to the fourth part 22d. For example, in the second supply operation, the first magnetic layer 11 is at the second potential E2. For example, in the second supply operation, the second magnetic layer 12 is at the fourth potential E4.

[0352] like Figure 30 (b) and Figure 30 (c) shows that when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 has an orientation I12 from the first part 21a to the second part 21b. In this case, during the second supply operation, the first magnetic layer 11 is at the second potential E2, and the second magnetic layer 12 is at the fourth potential E4. In the second supply operation when the first input In1 is “0” and the second input In2 is “1”, the same operation as the second supply operation when the first input In1 is “1” and the second input In2 is “0” can also be performed.

[0353] Hereinafter, several examples of the computing device of the embodiments will be described. In the following description, parts that are the same as those of the computing device 110 will be omitted as appropriate.

[0354] Figure 31 (a)~ Figure 31 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0355] These figures illustrate the operation of the computing device 110a in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0356] like Figure 31 As shown in (a), in the arithmetic device 110a, during the first supply operation (step S120), the inverted value of the second input In2, iIn2, is input to the first magnetic layer 11. The second input In2 is input to the second magnetic layer 12. During the first supply operation (step S120), when the second input In2 is "0", potential V1 is the second potential E2, and potential V2 is the third potential E3. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. The first current ic1 is directed towards I12, and the second current ic2 is directed towards I54.

[0357] like Figure 31 (b) and Figure 31(c) shows that when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 is directed towards I21, and the fourth current ic4 is directed towards I54. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 is directed towards I45. In such a computing device 110a, XNOR operations can also be performed using a simple structure.

[0358] Figure 32 (a)~ Figure 32 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0359] These figures illustrate the operation of the computing device 114 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0360] like Figure 32 As shown in (a), in the arithmetic device 114, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the second potential E2, and potential V2 is the third potential E3. The first current ic1 is directed towards I12, and the second current ic2 is directed towards I54.

[0361] like Figure 32 (b) and Figure 32 As shown in (c), when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21. In such a computing device 114, XNOR operations can also be performed using a simple structure.

[0362] Figure 33 (a)~ Figure 33 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0363] These figures illustrate the operation of the computing device 114a in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0364] like Figure 33As shown in (a), in the arithmetic device 114a, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the second potential E2, and potential V2 is the third potential E3. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. The first current ic1 is directed towards I21, and the second current ic2 is directed towards I45.

[0365] like Figure 33 (b) and Figure 33 As shown in (c), when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 has an orientation towards I12, and the fourth current ic4 has an orientation towards I45. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 has an orientation towards I54. In such a computing device 114a, XNOR operations can also be performed using a simple structure.

[0366] Figure 34 (a)~ Figure 34 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0367] These figures illustrate the operation of the computing device 115 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0368] like Figure 34 As shown in (a), in the definition of DF0 in the operation, the state where the first resistance of the first stack S1 is the first high resistance state (H and AP) and the second resistance of the second stack S2 is the second high resistance state (H and AP) corresponds to "0". The state where the first resistance is the first low resistance state (L and P) which is lower than the first high resistance state and the second resistance is the second low resistance state (L and P) which is lower than the second high resistance state corresponds to "1".

[0369] like Figure 34 As shown in (a), in the (AP, AP) state, the first input In1 is "0". In the (P, P) state, the first input In1 is "1".

[0370] like Figure 34As shown in (a), in the arithmetic unit 115, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the second potential E2, and potential V2 is the third potential E3. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. The first current ic1 is directed towards I12, and the second current ic2 is directed towards I54.

[0371] like Figure 34 (b) and Figure 34 (c) shows that when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 is directed towards I21, and the fourth current ic4 is directed towards I54. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 is directed towards I45. In such a computing device 115, XNOR operations can also be performed using a simple structure.

[0372] Figure 35 (a)~ Figure 35 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0373] These figures illustrate the operation of the computing device 115a in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0374] like Figure 35 As shown in (a), in the arithmetic device 115a, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the second potential E2, and potential V2 is the third potential E3. The first current ic1 is directed towards I21, and the second current ic2 is directed towards I45.

[0375] like Figure 35 (b) and Figure 35 As shown in (c), when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 is directed towards I21, and the fourth current ic4 is directed towards I54. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12. In such a computing device 115a, XNOR operations can also be performed using a simple structure.

[0376] Figure 36 (a)~ Figure 36 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0377] These figures illustrate the operation of the computing device 116 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0378] like Figure 36 As shown in (a), in the arithmetic device 116, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the second potential E2, and potential V2 is the third potential E3. The first current ic1 is directed towards I12, and the second current ic2 is directed towards I54.

[0379] like Figure 36 (b) and Figure 36 (c) shows that when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21. In such a computing device 116, XNOR operations can also be performed using a simple structure.

[0380] Figure 37 (a)~ Figure 37 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0381] These figures illustrate the operation within the computing device 116a of the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0382] like Figure 37 As shown in (a), in the arithmetic device 116a, during the first supply operation (step S120), when the second input In2 is "0", potential V1 is the second potential E2, and potential V2 is the third potential E3. During the first supply operation (step S120), when the second input In2 is "1", potential V1 is the first potential E1, and potential V2 is the fourth potential E4. The first current ic1 is directed towards I21, and the second current ic2 is directed towards I45.

[0383] like Figure 37(b) and Figure 37 As shown in (c), when the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation (step S130), the third current ic3 has an orientation towards I12, and the fourth current ic4 has an orientation towards I45. When the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 has an orientation towards I54. In such a computing device 116a, XNOR operations can also be performed using a simple structure.

[0384] Figure 38 (a)~ Figure 38 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0385] These figures illustrate the operation of the computing device 120 in the already described embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0386] like Figure 38 As shown in (a), when the first resistance of the first stack S1 is in the first low resistance state (L and P) and the second resistance of the second stack S2 is in the first high-low resistance state (H and AP), the first input In1 is "0". When the first resistance is in the first high resistance state (H and AP), which is higher than the first low resistance state, and the second resistance is in the second low resistance state (L and P), which is lower than the second high resistance state, the first input In1 is "1".

[0387] like Figure 38 As shown in (a), the first current ic1 has an orientation I21 from the second part 21b to the first part 21a. The second current ic2 has an orientation I45 from the fourth part 22d to the fifth part 22e. When the second input In2 is "0", during the first supply operation, the potential V1 of the first magnetic layer 11 is the first potential E1, and the potential V2 of the second magnetic layer 12 is the fourth potential E4. When the second input In2 is "1", during the first supply operation, the potential V1 of the first magnetic layer 11 is the second potential E2, and the potential V2 of the second magnetic layer 12 is the third potential E3. As already explained, the polarity of the second potential E2 is opposite to the polarity of the first potential E1. The polarity of the fourth potential E4 is opposite to the polarity of the third potential E3. The polarity of the fourth potential E4 is opposite to the polarity of the first potential E1.

[0388] like Figure 38 (b) and Figure 38(c) As shown, during the measurement operation, the potential at the connection point CN of the second part 21b and the fourth part 22d is measured when a first potential difference Va is applied to the first magnetic layer 11 with the second magnetic layer 12 as a reference. When the potential at the connection point CN is higher or lower than approximately half of the first potential difference Va, the third current ic3 has an orientation I21 from the second part 21b to the first part 21a, and the fourth current ic4 has an orientation I54 from the fifth part 22e to the fourth part 22d. When the potential at the connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 has an orientation I12 from the first part 21a to the second part 21b. In such a computing device 120, XNOR operations can be performed using a simple structure.

[0389] Figure 39 (a)~ Figure 39 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0390] These figures illustrate the operation of the computing device 120a in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0391] like Figure 39 As shown in (a), when the first resistance of the first stack S1 is in the first high resistance state (H and AP) and the second resistance of the second stack S2 is in the second low resistance state (L and P), the first input In1 is "0". When the first resistance is in the first low resistance state (L and P), which is lower than the first high resistance state, and the second resistance is in the second high resistance state (H and AP), which is higher than the second low resistance state, the first input In1 is "1".

[0392] like Figure 39 As shown in (a), the first current ic1 has an orientation I12 from the first part 21a to the second part 21b, and the second current ic2 has an orientation I54 from the fifth part 22e to the fourth part 22d. When the second input In2 is "0", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3. When the second input In2 is "1", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4.

[0393] like Figure 39 (b) and Figure 39As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21. In such a computing device 120a, XNOR calculations can be performed using a simple structure.

[0394] Figure 40 (a)~ Figure 40 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0395] These figures illustrate the operation of the computing device 124 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0396] like Figure 40 As shown in (a), the first current ic1 is directed towards I12, and the second current ic2 is directed towards I54. When the second input In2 is "0", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3. When the second input In2 is "1", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4.

[0397] like Figure 40 (b) and Figure 40 As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21, and the fourth current ic4 is directed towards I54. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 is directed towards I45. In such a computing device 124, XNOR operations can be performed using a simple structure.

[0398] Figure 41 (a)~ Figure 41 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0399] These figures illustrate the operation within the computing device 124a of the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0400] like Figure 41As shown in (a), the first current ic1 is directed towards I21, and the second current ic2 is directed towards I45. When the second input In2 is "0", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4. When the second input In2 is "1", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3.

[0401] like Figure 41 (b) and Figure 41 As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21, and the fourth current ic4 is directed towards I54. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12. In such a computing device 124a, XNOR operations can be performed using a simple structure.

[0402] Figure 42 (a)~ Figure 42 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0403] These figures illustrate the operation of the computing device 125 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0404] like Figure 42 As shown in (a), the first current ic1 is directed towards I21, and the second current ic2 is directed towards I45. When the second input In2 is "0", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4. When the second input In2 is "1", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3.

[0405] like Figure 42 (b) and Figure 42 As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21. In such a computing device 125, XNOR calculations can be performed using a simple structure.

[0406] Figure 43 (a)~ Figure 43(d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0407] These figures illustrate the operation of the computing device 125a in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0408] like Figure 43 As shown in (a), the first current ic1 is directed towards I21, and the second current ic2 is directed towards I45. When the second input In2 is "0", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3. When the second input In2 is "1", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4.

[0409] like Figure 43 (b) and Figure 43 As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 is directed towards I45. In such a computing device 125a, XNOR calculations can be performed using a simple structure.

[0410] Figure 44 (a)~ Figure 44 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0411] These figures illustrate the operation of the computing device 126 in the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0412] like Figure 44 As shown in (a), the first current ic1 is directed towards I12, and the second current ic2 is directed towards I54. When the second input In2 is "0", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4. When the second input In2 is "1", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3.

[0413] like Figure 44 (b) and Figure 44As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I21. In such a computing device 126, XNOR operations can be performed using a simple structure.

[0414] Figure 45 (a)~ Figure 45 (d) is a schematic diagram illustrating the operation of the computing device in an illustrative embodiment.

[0415] These figures illustrate the operation within the computing device 126a of the embodiment. These figures correspond to... Figure 30 (a)~ Figure 30 (d) illustrates the structure.

[0416] like Figure 45 As shown in (a), the first current ic1 is directed towards I21, and the second current ic2 is directed towards I45. When the second input In2 is "0", in the first supply operation, potential V1 is the second potential E2, and potential V2 is the third potential E3. When the second input In2 is "1", in the first supply operation, potential V1 is the first potential E1, and potential V2 is the fourth potential E4.

[0417] like Figure 45 (b) and Figure 45 As shown in (c), when the potential at connection point CN is higher or lower than approximately half of the first potential difference Va during the measurement operation, the third current ic3 is directed towards I12, and the fourth current ic4 is directed towards I45. When the potential at connection point CN corresponds to approximately half of the first potential difference Va during the measurement operation, the fourth current ic4 is directed towards I54. In such a computing device 126a, XNOR calculations can be performed using a simple structure.

[0418] In the above-described computing device of the embodiment, during the second supply operation, the potential V1 of the first magnetic layer 11 and the potential V2 of the second magnetic layer 12 correspond, for example, to the potential of "Active".

[0419] Multiple arithmetic element units 50 may also be provided in the arithmetic device. At least one of the multiple arithmetic element units 50 may have any of the structures described above. The control unit 70 may also include a selector SEL1 (see reference). Figure 27 Selector SEL1 can also select at least one of the multiple arithmetic element sections 50 to perform XNOR operation.

[0420] According to the implementation method, a computing device with a simple structure can be provided.

[0421] In this application specification, "perpendicular" and "parallel" include not only strict perpendicularity and strict parallelism, but also deviations in the manufacturing process, as long as they are substantially perpendicular and substantially parallel.

[0422] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, any specific structure of the conductive members, elements, laminates, magnetic layers, non-magnetic layers, conductive parts, and control parts included in the computing device is included within the scope of the present invention, as long as those skilled in the art can appropriately select from the known range and similarly implement the present invention to obtain the same effect.

[0423] Any example that combines any two or more elements in each specific instance within the scope of technically possible means is also included within the scope of this invention, provided it contains the spirit of the invention.

[0424] In addition, all computing devices implemented by those skilled in the art based on the computing device described above as an embodiment of the present invention, which can be appropriately modified by design, are also within the scope of the present invention as long as they contain the spirit of the present invention.

[0425] In addition, it should be understood that within the scope of the ideas of this invention, various modifications and alterations can be conceived by those skilled in the art, and such modifications and alterations also fall within the scope of this invention.

[0426] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention as set forth in the claims and its equivalents.

Claims

1. A computing device comprising: The arithmetic unit; and Control Department The computing element unit includes: A first element includes a first conductive member and a first laminate, wherein the first conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion; the first laminate includes a first magnetic layer and a first opposing magnetic layer disposed between the third portion and the first magnetic layer; and The second element includes a second conductive member and a second laminate, wherein the second conductive member includes a fourth portion, a fifth portion, and a sixth portion between the fourth portion and the fifth portion; the second laminate includes a second magnetic layer and a second opposing magnetic layer disposed between the sixth portion and the second magnetic layer; the second portion is electrically connected to the fourth portion. The control unit is capable of performing XNOR operations on a first input and a second input, wherein the first input corresponds to a first resistance of the first stack and a second resistance of the second stack, and the second input corresponds to the potential of the first magnetic layer and the potential of the second magnetic layer. The control unit is capable of performing the first supply action, the measurement action, and the second supply action. In the first supply operation, the control unit supplies a first current to the first conductive member and a second current to the second conductive member. During the measurement operation, the control unit measures the first resistance after the supply of the first current and the second resistance after the supply of the second current. In the second supply operation, after the measurement operation, the control unit supplies a third current to the first conductive member and a fourth current to the second conductive member.

2. The computing device according to claim 1, wherein, The first current has an orientation from the second portion to the first portion, and the second current has an orientation from the fourth portion to the fifth portion, or... The first current has an orientation from the first part to the second part, and the second current has an orientation from the fifth part to the fourth part.

3. The computing device according to claim 2, wherein, The first current has an orientation from the second portion to the first portion, and the second current has an orientation from the fourth portion to the fifth portion. When the first resistor is in a first low resistance state and the second resistor is in a second low resistance state, the first input is "0". When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second high resistance state (higher than the second low resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

4. The computing device according to claim 3, wherein, During the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to half of the first potential difference, the third current has the orientation from the second portion to the first portion, and the fourth current has the orientation from the fifth portion to the fourth portion. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point is higher or lower than 1 / 2 of the first potential difference, the fourth current has the orientation from the fourth part to the fifth part.

5. The computing device according to claim 2, wherein, The first current has an orientation from the first portion to the second portion, and the second current has an orientation from the fifth portion to the fourth portion. When the first resistor is in a first low resistance state and the second resistor is in a second low resistance state, the first input is "0". When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second high resistance state (higher than the second low resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

6. The computing device according to claim 5, wherein, In the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point is higher or lower than 1 / 2 of the first potential difference, the fourth current has the orientation from the fourth part to the fifth part.

7. The computing device according to claim 2, wherein, The first current has an orientation from the second portion to the first portion, and the second current has an orientation from the fourth portion to the fifth portion. When the first resistor is in a first high resistance state and the second resistor is in a second high resistance state, the first input is "0". When the first resistor is in a first low resistance state (lower than the first high resistance state) and the second resistor is in a second low resistance state (lower than the second high resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

8. The computing device according to claim 7, wherein, In the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point is higher or lower than 1 / 2 of the first potential difference, the third current has the orientation from the first part to the second part.

9. The computing device according to claim 2, wherein, The first current has an orientation from the first portion to the second portion, and the second current has an orientation from the fifth portion to the fourth portion. When the first resistor is in a first high resistance state and the second resistor is in a second high resistance state, the first input is "0". When the first resistor is in a first low resistance state (lower than the first high resistance state) and the second resistor is in a second low resistance state (lower than the second high resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

10. The computing device according to claim 9, wherein, In the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point of the second and fourth portions corresponds to half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. In the second supply operation, the first magnetic layer is the second potential, and the second magnetic layer is the fourth potential. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point is higher or lower than 1 / 2 of the first potential difference, the fourth current has the orientation from the fourth part to the fifth part.

11. The computing device according to claim 2, wherein, The first current has an orientation from the second portion to the first portion, and the second current has an orientation from the fourth portion to the fifth portion. When the first resistor is in a first low resistance state and the second resistor is in a second high resistance state, the first input is "0". When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second low resistance state (lower than the second high resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

12. The computing device according to claim 11, wherein, During the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point between the second and fourth portions is higher or lower than half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point corresponds to half of the first potential difference, the third current has the orientation from the first part to the second part.

13. The computing device according to claim 2, wherein, The first current has an orientation from the first portion to the second portion, and the second current has an orientation from the fifth portion to the fourth portion. When the first resistor is in a first high resistance state and the second resistor is in a second low resistance state, the first input is "0". When the first resistor is in a first low resistance state (lower than the first high resistance state) and the second resistor is in a second high resistance state (higher than the second low resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

14. The computing device according to claim 13, wherein, During the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point between the second and fourth portions is higher or lower than half of the first potential difference, the third current has the direction from the first portion to the second portion, and the fourth current has the direction from the fourth portion to the fifth portion. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point corresponds to half of the first potential difference, the third current has the orientation from the second part to the first part.

15. The computing device according to claim 2, wherein, The first current has an orientation from the first portion to the second portion, and the second current has an orientation from the fifth portion to the fourth portion. When the first resistor is in a first low resistance state and the second resistor is in a second high resistance state, the first input is "0". When the first resistance is a first high resistance state (higher than the first low resistance state) and the second resistance is a second low resistance state (lower than the second high resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

16. The computing device according to claim 15, wherein, During the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point between the second and fourth portions is higher or lower than half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point corresponds to half of the first potential difference, the fourth current has the orientation from the fourth part to the fifth part.

17. The computing device according to claim 2, wherein, The first current has an orientation from the second portion to the first portion, and the second current has an orientation from the fourth portion to the fifth portion. When the first resistor is in a first high resistance state and the second resistor is in a second low resistance state, the first input is "0". When the first resistor is in a first low resistance state (lower than the first high resistance state) and the second resistor is in a second high resistance state (higher than the second low resistance state), the first input is "1". When the second input is "0", during the first supply operation, the potential of the first magnetic layer is the first potential, and the potential of the second magnetic layer is the fourth potential. When the second input is "1", during the first supply operation, the potential of the first magnetic layer is the second potential, and the potential of the second magnetic layer is the third potential. The polarity of the second potential is opposite to that of the first potential. The polarity of the fourth potential is opposite to that of the third potential. The polarity of the fourth potential is opposite to the polarity of the first potential.

18. The computing device according to claim 17, wherein, During the measurement operation, when a first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, if the potential at the connection point between the second and fourth portions is higher or lower than half of the first potential difference, the third current has the direction from the second portion to the first portion, and the fourth current has the direction from the fifth portion to the fourth portion. During the measurement operation, when the first potential difference is applied to the first magnetic layer with reference to the second magnetic layer, and the potential at the connection point corresponds to half of the first potential difference, the third current has the orientation from the first part to the second part.

19. The computing device according to claim 1, wherein, The computing device includes a plurality of the aforementioned computing element units. The control unit includes a selector. The selector can select at least one of the plurality of arithmetic element units to perform the XNOR operation.

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