Self-verifying data voting system

Abstract

This invention provides a self-verifying data voting system, including an input verification unit, an output logic unit, an output verification unit, and a verification processing unit. Both the input and output verification units incorporate an XOR unit, a multi-channel dual-track code verifier, and a code verifier. By performing an XOR operation on two different bits of the input data, and then combining this with the multi-channel dual-track code verifier to generate a randomized test set, the code verifier can obtain a complete test code, avoiding the loss of test information. The verification processing unit determines the state of the data voting system and the processing method based on the second verification result of the input verification unit and the fifth verification result of the output verification unit. This achieves verification of both the input data and the data voting system itself, realizing true self-verification and improving the reliability of the electronic system.

Description

Technical Field

[0001] This invention relates primarily to the field of reliability analysis of electronic systems, and more particularly to a self-verifying data voting system. Background Technology

[0002] In complex electromagnetic environments such as space, electronic systems are inevitably affected by high-energy charged particles, solar electromagnetic radiation, plasma, the Earth's magnetic field, cosmic rays, and other complex space environmental factors, resulting in single-event events that can cause errors in the data stored in the electronic system. To reduce the impact of complex electromagnetic environments on data, redundant data can be added, data can be stored in a distributed manner, and data arbitration methods can be used to extract correct data unaffected by single-event events from the redundant data, thereby improving the reliability of the electronic system.

[0003] Voting systems are a crucial part of data arbitration. Errors in the voting system can lead to errors in the entire arbitration result. However, current voting systems often lack the ability to detect their own errors. Using other error-detecting units introduces additional reliability issues, potentially causing further problems. Therefore, the goal is to design a voting system with self-checking capabilities to improve the reliability of electronic systems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a self-checking data voting system that can simultaneously detect errors in input data and errors in the voting system itself.

[0005] To solve the above technical problems, the present invention provides a self-verifying data voting system, including an input verification unit, an output logic unit, an output verification unit, and a verification processing unit. The input verification unit includes N1 first XOR units, N1 first multi-channel dual-track code verifiers, and a first code verifier. The first code verifier is a code verifier that takes N1 codes from 2*N1. The input verification unit receives N2 input data channels, which are redundant. Each input data channel includes M bits of data. The N2 input data channels are combined in pairs to form N1 data groups. Each first multi-channel dual-track code verifier receives one data group, compares it, and outputs a first verification result based on the comparison result. Each first XOR unit performs XOR processing on two different bits of one input data channel to obtain a first XOR result. The first XOR unit also generates a pair of first test codes based on the first XOR result and the first verification result. N1 pairs of first test codes form the first input test set of the first code verifier. The first code verifier outputs a second verification result based on the first input test set. In this system, N1 is a positive integer greater than or equal to 3, and N2 is an odd number greater than or equal to 3. The output logic unit is used to receive the first verification result and output a third verification result, the third verification result including the first verification result with the majority agreement. The output verification unit includes N1 second XOR units, N1 second multi-channel dual-track code verifiers and second code verifiers. The second code verifier is a code verifier that takes N1 codes from 2*N1. Each second multi-channel dual-track code verifier is used to receive one input data and one third verification result and compare them, and output a fourth verification result based on the comparison result. Each second XOR unit is used to perform XOR processing on two different bits in one input data to obtain a second XOR result. The second XOR unit is also used to generate a pair of second test codes based on the second XOR result and the fourth verification result. N1 pairs of second test codes form the second input test set of the second code verifier. The second code verifier outputs a fifth verification result based on the second input test set. The verification processing unit is used to determine the state of the data voting system based on the second verification result and the fifth verification result.

[0006] In one embodiment of this application, each pair of the first test codes is a two-bit data including [0,1] or [1,0], and each pair of the second test codes is a two-bit data including [0,1] or [1,0].

[0007] In one embodiment of this application, different first XOR units perform XOR processing on different bits in the input data, and different second XOR units perform XOR processing on different bits in the input data.

[0008] In one embodiment of this application, the second verification result includes two data bits. The second verification result includes four types: [0,1], [1,0], [0,0], and [1,1]. Among them, [0,1] and [1,0] indicate that both the second verification result and the input verification unit are normal, and [0,0] and [1,1] indicate that either the second verification result or the input verification unit is faulty.

[0009] In one embodiment of this application, the fifth verification result includes two data bits. The fifth verification result includes four types: [0,1], [1,0], [0,0], and [1,1]. Among them, [0,1] and [1,0] indicate that the fifth verification result and the output verification unit are both normal, and [0,0] and [1,1] indicate that the fifth verification result or the output verification unit is faulty.

[0010] In one embodiment of this application, the verification processing unit is further configured to determine a first processing method based on the second verification result and the fifth verification result. The first processing method includes any one or a combination of the following: no processing, refreshing the input data, refreshing the first code verifier, refreshing the first multi-channel dual-track code verifier, refreshing the second code verifier, and refreshing the second code verifier.

[0011] In one embodiment of this application, the verification processing unit is further configured to determine a second processing method based on the state of the data voting system after executing the first processing method. The state of the data voting system includes any one of normal, input verification unit error, output verification unit error, and output logic error. The second processing method includes: outputting an error report or refreshing the output logic unit.

[0012] In one embodiment of this application, the output logic unit is further configured to output the judgment result of each input data channel, the judgment result including normal and error.

[0013] In one embodiment of this application, the output logic unit is further configured to output the second verification result and the fifth verification result.

[0014] In one embodiment of this application, the input data is in units of one byte, and each input data includes 8 bits of data.

[0015] The data voting system of this application incorporates an XOR unit, a multi-channel dual-track code checker, and a code checker in both the input and output verification units. By performing an XOR operation on two different bits of the input data, and then combining this with the multi-channel dual-track code checker to generate a randomized test set, the code checker can obtain a complete test code, avoiding information loss during testing. The verification processing unit determines the state and processing method of the data voting system based on the second verification result of the input verification unit and the fifth verification result of the output verification unit. This achieves verification of both the input data and the data voting system itself, realizing true self-verification and improving the reliability of the electronic system. Attached Figure Description

[0016] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of the invention. In the drawings:

[0017] Figure 1 This is a block diagram of a self-verifying data voting system according to an embodiment of this application;

[0018] Figure 2 This is a structural block diagram of the input verification unit and the output logic unit in a self-verifying data voting system according to an embodiment of this application;

[0019] Figure 3 This is a structural block diagram of the output verification unit in a self-verifying data voting system according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the circuit structure of a dual-track code verifier;

[0021] Figure 5 yes Figure 2 and Figure 3 The circuit structure diagram of the first multi-channel dual-track code verifier and the second multi-channel dual-track code verifier is shown in the figure.

[0022] Figure 6 Yes, yes Figure 2 and Figure 3 The circuit structure diagram of the first code verifier and the second code verifier shown in the figure;

[0023] Figure 7 This is a schematic diagram of the circuit structure of the input verification unit in a data voting system according to an embodiment of this application;

[0024] Figure 8 This is a schematic diagram of the circuit structure of the output verification unit in a data voting system according to an embodiment of this application. Detailed Implementation

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0026] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0027] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0028] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0029] The self-verifying data voting system of this application can be applied to any electronic device, including those operating in complex electromagnetic environments. Preferably, the electronic device is one used on a spacecraft in the complex electromagnetic environment of space.

[0030] Figure 1 This is a block diagram of a self-verifying data voting system according to an embodiment of this application. (Reference) Figure 1 As shown, the data voting system 100 of this embodiment includes an input verification unit 110, an output logic unit 120, an output verification unit 130, and a verification processing unit 140. The input verification unit 110 includes N1 first XOR units, N1 first multi-channel dual-track code verifiers, and a first code verifier. The first code verifier is a code verifier that takes N1 codes from 2*N1. The input verification unit 110 is used to receive N2 input data 101, which are redundant data. Each input data 101 includes M bits of data. The N2 input data 101 are combined in pairs to form N1 data groups. Each first multi-channel dual-track code verifier is used to receive a data group and compare it, and output a first verification result based on the comparison result. Each first XOR unit is used to perform XOR processing on two different bits of data in one input data to obtain a first XOR result. The first XOR unit is also used to generate a pair of first test codes based on the first XOR result and the first verification result. N1 pairs of first test codes form the first input test set of the first code verifier. The first code verifier outputs a second verification result Ei based on the first input test set, where N1 is a positive integer greater than or equal to 3, and N2 is an odd number greater than or equal to 3. Output logic unit 120 receives the first verification result and outputs the third verification result OUT, which includes the first verification result that matches the majority. Output verification unit 130 includes N1 second XOR units, N1 second multiplexed dual-track code verifiers, and a second code verifier. The second code verifier is a code verifier that takes N1 codes from 2*N1. Each second multiplexed dual-track code verifier receives one input data and one third verification result, compares them, and outputs a fourth verification result based on the comparison result. Each second XOR unit performs XOR processing on two different bits in one input data to obtain a second XOR result. The second XOR unit also generates a pair of second test codes based on the second XOR result and the fourth verification result. N1 pairs of second test codes form the second input test set of the second code verifier. The second code verifier outputs a fifth verification result Eo based on the second input test set. Verification processing unit 140 determines the state of data voting system 100 based on the second verification result Ei and the fifth verification result Eo.

[0031] Current voting systems often include only one input validation unit to validate input data and one output logic unit to output the validation result, thus failing to achieve self-validation. The data voting system described in this application addresses this issue by... Figure 1 This setup allows for the verification of input data and the verification of the data voting system itself, achieving true self-verification and improving the reliability of the electronic system.

[0032] This specification will describe the data voting system using specific embodiments with N1=3 and N2=3. Those skilled in the art can extend N1 to any integer greater than 3 and N2 to any odd number greater than 3 based on the ideas of this application.

[0033] Figure 2 This is a structural block diagram of the input verification unit and output logic unit in a self-verifying data voting system according to an embodiment of this application. In this embodiment, N1 = N2 = 3. (See reference...) Figure 2 As shown, the three input data channels are D1, D2, and D3. These three data channels are redundant. When applied to electronic devices in a space environment, these three data channels can serve as redundant data to prevent data errors. In some embodiments, these three data channels can be random numbers used to test the data voting system 100. In some embodiments, M = 8, meaning each input data channel includes 8 bits of data, i.e., one byte. For example, input data D1 is a series of data units in bytes, as are D2 and D3.

[0034] like Figure 2 As shown, the input verification unit 110 includes three first XOR units 211, 212, and 213, represented by dashed boxes. It should be noted that... Figure 2 The first XOR unit shown is for illustrative purposes only. Figure 2 Although two XOR gate icons are shown in each dashed box, this does not limit the first XOR unit to containing only two XOR gates, nor does it limit the specific connection relationship between the first XOR unit and the first multi-channel dual-track code verifier. The specific structure of the first XOR unit in the input verification unit 110 and its specific connection relationship with the first multi-channel dual-track code verifier will be discussed later. Figure 7 illustrate.

[0035] refer to Figure 2 The three input data streams are combined in pairs to form three data groups: (D1, D2), (D2, D3), and (D1, D3). Each data group corresponds to a first multi-channel dual-track code checker. For example... Figure 2 Data groups (D1, D2) correspond to the first multi-channel dual-track code verifier 221, data groups (D1, D3) correspond to the first multi-channel dual-track code verifier 222, and data groups (D2, D3) correspond to the first multi-channel dual-track code verifier 223. Each first multi-channel dual-track code verifier receives a set of data groups, compares them, and outputs a first verification result based on the comparison result. For example, the first multi-channel dual-track code verifier 221 compares the two input data groups D1 and D2 in the data group (D1, D2) and outputs a first verification result. The first XOR unit performs XOR processing on two different bits in the input data D1 to obtain a first XOR result. Figure 2The first check result and the first XOR result are not directly shown. However, Figure 2 The data output by the first multi-channel dual-track code checker 221 to the 3 / 6 code checker 230 is a pair of first test codes generated by the first XOR result and the first check result. The output data of the first multi-channel dual-track code checkers 222 and 223 are generated in the same way, generating a total of 3 pairs of first test codes.

[0036] It should be noted that the number N1 of the first multi-channel dual-code verifiers and the number of input data channels N2 can be equal or unequal. In the above embodiment, N1 = N2. In other embodiments, N1 may not be equal to N2; theoretically, N1 can be greater than N2. For example, when N2 = 5, the five data channels can be combined in pairs to generate 10 combinations, namely D1D2, D1D3, D1D4, D1D5, D2D3, D2D4, D2D5, D3D4, D3D5, and D4D5. In this case, N1 can be equal to 10, meaning each data group is input to one first multi-channel dual-code verifier. However, to achieve the purpose of data verification, it is only necessary to select adjacent data combinations, namely the five data groups D1D2, D2D3, D3D4, D4D5, and D5D1, which requires only five first multi-channel dual-code verifiers. According to these embodiments, N1 = N2, and the input data of adjacent channels are taken as the input signals of the first multi-channel dual-code verifiers.

[0037] like Figure 2 As shown, the first code checker in this embodiment is a 3 / 6 code checker 230. The 3 / 6 code checker 230 is a code checker that takes 3 bits from 6 codes. Each first XOR unit and the corresponding first multi-channel dual-track code checker together output a pair of first test codes to the 3 / 6 code checker 230. The 3 / 6 code checker 230 receives a total of 3 pairs of first test codes, totaling 6 bits of data. After passing through the 3 / 6 code checker 230, it outputs two bits as the second check result Ei.

[0038] It should be noted that when N1 takes other numbers, the first code checker becomes the code checker that takes the N1 code from the corresponding 2*N1.

[0039] Figure 2 The output logic unit 240 in is Figure 1 This is a specific embodiment of the output logic unit 120 shown. The input of the output logic unit 240 is... Figure 2The output logic unit 240 outputs the third verification result OUT based on the three sets of first verification results obtained by the first multi-channel dual-track code verifiers 221, 222, and 223 (not shown). The output logic unit 240 outputs the majority-consistent first verification result as the third verification result OUT. For example, corresponding to input data D1, D2, and D3, each consisting of 8 bits, if the 8 bits in the two bytes of D1 and D2 are consistent, then the consistent byte is output as the third verification result OUT.

[0040] Figure 3 This is a structural block diagram of the output verification unit in a self-verifying data voting system according to an embodiment of this application. This embodiment is similar to... Figure 2 The embodiments shown are consistent, with N1 = N2 = 3. Figure 3 The output verification unit 300 shown is Figure 1 One specific implementation of the output verification unit 130 in the example. For example... Figure 3 As shown, the three input data channels D1, D2, and D3 are... Figure 2 The three input data channels are input to the input verification unit 110. In addition, the input data will also be... Figure 2 The third verification result OUT output by the output logic unit 240 is input into the output verification unit 300.

[0041] Specifically, the output verification unit 300 includes three second XOR units 311, 312, and 313, three second multi-channel dual-track code verifiers 321, 322, and 323, and one second code verifier. In this embodiment, the second code verifier is a 3 / 6 code verifier 330. The internal structure and working principle of the second XOR units, second multi-channel dual-track code verifiers, and 3 / 6 code verifier 330 in the output verification unit 300 are the same as or similar to the internal structure and working principle of the first XOR unit, first multi-channel dual-track code verifier, and 3 / 6 code verifier 230 in the input verification unit 110, respectively, with the difference being the input and output. The specific structure of the second XOR unit in the output verification unit 300 and its specific connection relationship with the second multi-channel dual-track code verifier will be discussed later. Figure 8 illustrate.

[0042] It should be noted that when N1 takes other numbers, the second code checker correspondingly becomes a code checker that takes the N1 code from the 2*N1 sequence. For example... Figure 3The second multi-channel dual-track code check 321 receives input data D1 and the third check result OUT, compares them, and outputs a fourth check result. The second multi-channel dual-track code check 322 receives input data D2 and the third check result OUT, compares them, and outputs a fourth check result. The second multi-channel dual-track code check 323 receives input data D3 and the third check result OUT, compares them, and outputs a fourth check result. The second XOR unit 311 performs XOR processing on two different bits in input data D1 to obtain a second XOR result. The second XOR unit 312 performs XOR processing on two different bits in input data D2 to obtain a second XOR result. The second XOR unit 313 performs XOR processing on two different bits in input data D3 to obtain a second XOR result. Figure 3 The second verification result and the second XOR result are not directly shown. The fourth verification result output by the second multi-channel dual-track code verification 321 and the second XOR result output by the second XOR unit 311 generate a pair of second test codes, generating a total of 3 pairs of second test codes.

[0043] like Figure 3 As shown, the 3 / 6 code checker 330 receives a total of 3 pairs of second test codes, totaling 6 bits of data. After passing through the 3 / 6 code checker 330, it outputs two bits as the fifth check result Eo.

[0044] The data voting system of this application can be implemented using any form of software or hardware. The inventors of this application used an FPGA to construct, simulate, and test the data voting system. Those skilled in the art can also implement the data voting system in other ways based on the ideas of this application. The following circuit diagrams implemented using an FPGA illustrate one implementation of the input verification unit, output logic unit, and output verification unit in the data voting system of this application, and are not intended to limit the specific structure of these units.

[0045] Firstly adopt Figure 4 This paper describes the circuit structure of a dual-track code verifier. This dual-track code verifier is composed of... Figure 2 The first multi-channel dual-track code checker and Figure 3 The basic unit of the second multi-channel dual-track code checker. For example... Figure 4 As shown, A1, A2, B1, and B2 each represent one bit of input data, and C1 and C2 each represent one bit of output data. Using... Figure 4 The dual-track code verifier shown has the operational logic as shown in Table 1.

[0046] Table 1. Output characteristics of the dual-track code checker

[0047] B2B1 A2A1 C2C1 01 01 10 01 10 01 10 01 01 10 10 10

[0048] The input to the dual-track code checker is two two-bit signal values. One set of signals is inverted and then input. When each bit is the inverted comparison result, the output is normal, outputting [0,1] or [1,0]. It can be extended to more bits by cascading, and the final result is still two bits.

[0049] Figure 5 yes Figure 2 and Figure 3 The circuit diagrams of the first and second multi-channel dual-track code verifiers shown are collectively referred to as multi-channel dual-track code verifiers. Figure 4 Based on the above, the method is improved by taking two raw data streams, raw_data1[7,…,0] and raw_data2[7,…,0], each with 8 bits, as input data. The two identical bits of these two data streams are input into a two-rail checker, thereby realizing the comparison and verification of the 8 bits of data and outputting the first verification result C2C1.

[0050] If both raw_data1[7,…,0] and raw_data2[7,…,0] are correct, C2C1 outputs [0,1] or [1,0]. If the first verification result C2C1 is directly input to the 3 / 6 code checker, the 3 / 6 code checker will not be able to obtain the complete combination input.

[0051] Figure 6 Yes, yes Figure 2 and Figure 3 The circuit diagrams of the first and second code checkers shown are specifically 3 / 6 code checkers. Code checkers that take N1 bits from 2*N1 code have strict input requirements; that is, N1 bits of the input 2*N1 data must be 1. Since the data content is uncertain, the input data cannot be directly used as the input to the code checker. The data voting system of this application uses two sets of data for comparison as the input to the aforementioned multi-channel dual-track code checker, and then uses the output of the multi-channel dual-track code checker as the input to the 3 / 6 code checker, thus solving the problem of data not being directly input. According to the requirement of complete self-checking, in order for the 3 / 6 code checker to perform complete self-checking, it is necessary to quickly and completely input the test code at least once after inputting data before the second error occurs. Therefore, the input of the 3 / 6 code checker should cover all test codes. Table 2 shows the complete test set of the 3 / 6 code checker.

[0052] Table 2.3 / 6 Code Verifier Complete Test Set

[0053] X1 X2 X3 X4 X5 X6 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1

[0054] Since the normal output of the dual-track code checker is [0,1] or [1,0], based on the duality of the 3 / 6 code checker, X1X4, X2X5, and X3X6 can be connected to the outputs of three multiplexed dual-track code checkers. This allows the data input to the 3 / 6 code checker to traverse its complete test set.

[0055] Furthermore, considering the aforementioned output characteristics of the dual-track code checker, repeatedly checking a single data bit is equivalent to removing that data bit. While this achieves differentiated input, it results in the loss of test information. Therefore, this application introduces a first XOR unit and a second XOR unit in its data voting system. These units XOR the two different data bits in each input data stream to generate a single differentiated data bit as the input, thus avoiding the loss of test information. Further, the processing methods for two-bit signals also include AND and OR logic. However, the probabilities of 0 and 1 in the outputs obtained using these two logic operations cannot be kept equal, which can affect the checker's output. Therefore, this application employs XOR logic, i.e., setting up a first XOR unit and a second XOR unit, to ensure that the probability of the newly added data bit 0 and 1 is consistent, avoiding the influence of different error probability preferences on the design.

[0056] Figure 7 This is a schematic diagram of the circuit structure of the input verification unit in a data voting system according to an embodiment of this application. Figure 7 As shown, three input data channels, data1[7,…,0], data2[7,…,0], and data3[7,…,0], are displayed. These three input data channels can correspond to... Figure 2 The input data are D1, D2, and D3. Figure 7 It also includes three first XOR units 711, 712, and 713, three first multi-channel dual-track code checkers 721, 722, and 723, and a 3 / 6 code checker 730, which correspond to respectively Figure 2 The input verification unit 110 shown includes the first XOR units 211, 212, 213, the first multi-channel dual-track code verifiers 221, 222, 223, and the 3 / 6 code verifier 230. Figure 7 As shown, the first XOR unit mainly includes some XOR gates that implement XOR logic, but also includes some AND gates. Taking the first XOR unit 711 as an example, two different bits of input data D1, namely data1[1] and data1[2], are XORed by the first XOR unit 711 to obtain the first XOR result. At the same time, input data D1 and D2 are input into the first multi-channel dual-track code checker 721, which compares the two 8-bit data and outputs the first check result, such as Figure 7The data1_result0 and data1_result1 shown are further processed by the first XOR unit 711, and finally generated together with the first XOR result to form a pair of first test codes X3X6, which serve as a pair of inputs to the 3 / 6 code checker 730. Similarly, the two different bits of D2, namely data2[3] and data1[4], are XORed by the first XOR unit 712 to obtain the first XOR result. The input data D1 and D3 are processed by the first multi-channel dual-track code checker 722 and output the second check result data2_result0 and data2_result1, which finally generate a pair of first test codes X2X5. The two different bits of D3, namely data3[5] and data3[6], are XORed by the first XOR unit 713 to obtain the first XOR result. The input data D2 and D3 are processed by the first multi-channel dual-track code checker 723 to output the second check result data3_result0 and data3_result1, finally generating a pair of first test codes X1X4. According to this setting, the first input test set composed of the first test codes can traverse all the test codes in the test set required by the 3 / 6 code checker 730 to realize the complete self-checking process. Figure 7 As shown, the output of the 3 / 6 code checker 730 is Ei0 and Ei1, which are the two bits of the second check result Ei.

[0057] In some embodiments, different first XOR units perform XOR operations on different bits in one input data path. For example... Figure 7 As shown, in these embodiments, each first XOR unit corresponds to one input data path, and the number of data bits processed is different. For example, the first XOR unit 711 processes data1[1] and data1[2] in D1, that is, the 1st and 2nd bits; the first XOR unit 712 processes data2[3] and data2[4] in D2, that is, the 3rd and 4th bits, which is different from the number of bits of D1 processed by the first XOR unit 711; the first XOR unit 713 processes data3[5] and data3[6] in D3, that is, the 5th and 6th bits, which is different from the number of bits of D1 and D2 processed by the first XOR units 711 and 712. Figure 7 The example shown is merely an illustration. In other embodiments, it is sufficient to simply use different numbers of bits, such as D1 taking data1[1] and data1[3], D2 taking data2[2] and data2[4], and D3 taking data3[3] and data3[6]. This setting introduces randomness, making the probabilities of [1,0] and [0,1] appearing in the first input test set of the 3 / 6 code checker 730 similar, thus making the testing process more complete.

[0058] Figure 8 This is a schematic diagram of the circuit structure of the output verification unit in a data voting system according to an embodiment of this application. Figure 8 As shown, three input data channels, data1[7,…,0], data2[7,…,0], and data3[7,…,0], are displayed. These three input data channels can correspond to... Figure 3 The input data are D1, D2, and D3. Simultaneously, the third verification result OUT also serves as the input signal for this output verification unit. Figure 8 It also includes three second XOR units 811, 812, and 813, three second multi-channel dual-track code checkers 821, 822, and 823, and a 3 / 6 code checker 830, which correspond to respectively Figure 3 The output verification unit 300 shown includes the second XOR units 311, 312, 313, the second multi-channel dual-track code verifiers 321, 322, 323, and the 3 / 6 code verifier 330. Figure 8 As shown, the second XOR unit mainly includes some XOR gates that implement XOR logic, but also includes some AND gates. Taking the second XOR unit 811 as an example, two different bits of input data D1, namely data1[1] and data1[2], are XORed by the second XOR unit 811 to obtain the second XOR result. At the same time, the input data D1 and the third verification result OUT are input to the second multi-channel dual-track code verifier 821. The second multi-channel dual-track code verifier 821 compares the two 8-bit data and outputs a fourth verification result. Figure 8 The fourth verification result is not marked, but it can be known that the fourth verification result is output by the C2C1 pin of the second multi-channel dual-track code checker 821. The fourth verification result is further processed by the second XOR unit 811, and finally generates a pair of second test codes X3X6 together with the second XOR result, which serve as a pair of inputs to the 3 / 6 code checker 830. Similarly, the two different bits of D2, namely data2[3] and data1[4], are XORed by the second XOR unit 812 to obtain the second XOR result. The input data D2 and the third verification result OUT are processed by the second multi-channel dual-track code checker 822 to output a fourth verification result, and finally generate a pair of second test codes X2X5. The two different bits of D3, namely data3[5] and data3[6], are XORed by the second XOR unit 813 to obtain the second XOR result. The input data D2 and the third verification result OUT are processed by the second multi-channel dual-track code checker 823 to output a fourth verification result, and finally generate a pair of second test codes X1X4. With this setup, the second input test set, composed of the second test codes, can iterate through all the test codes in the test set required by the 3 / 6 code checker 830, thus achieving a complete self-checking process. For example... Figure 8As shown, the output of the 3 / 6 code checker 830 is Eo0 and Eo1, which are the two bits of the fifth check result Eo.

[0059] In some embodiments, different second XOR units perform XOR operations on different bits in one input data path. For example... Figure 8 As shown, in these embodiments, each second XOR unit corresponds to one input data path, and the number of data bits processed is different. For example, the second XOR unit 811 processes data1[1] and data1[2] in D1, that is, the 1st and 2nd bits; the second XOR unit 812 processes data2[3] and data2[4] in D2, that is, the 3rd and 4th bits, which is different from the number of bits of D1 processed by the second XOR unit 711; the second XOR unit 813 processes data3[5] and data3[6] in D3, that is, the 5th and 6th bits, which is different from the number of bits of D1 and D2 processed by the second XOR units 811 and 812. Figure 8 The example shown is merely an illustration. In other embodiments, the number of bits can be different, for example, D1 can take data1[1] and data1[3], D2 can take data2[2] and data2[4], D3 can take data3[3] and data3[6], etc. This setting introduces randomness, making the probability of [1,0] and [0,1] appearing in the second input test set input to the 3 / 6 code checker 830 similar, and the testing process is more complete.

[0060] As can be seen from the above embodiments, each pair of first test codes consists of two data bits including [0,1] or [1,0], and each pair of second test codes consists of two data bits including [0,1] or [1,0].

[0061] according to Figure 7 The input verification unit shown has a second verification result consisting of two data bits. The second verification result has four possible values: [0,1], [1,0], [0,0], and [1,1]. [0,1] and [1,0] indicate that both the second verification result and the input verification unit are normal, while [0,0] and [1,1] indicate that either the second verification result or the input verification unit is faulty.

[0062] according to Figure 8 The output verification unit shown has a fifth verification result consisting of two data bits. There are four possible fifth verification results: [0,1], [1,0], [0,0], and [1,1]. [0,1] and [1,0] indicate that both the fifth verification result and the output verification unit are normal, while [0,0] and [1,1] indicate that either the fifth verification result or the output verification unit is faulty.

[0063] According to the above embodiments, the data voting system of this application can not only verify the input data and determine whether the input data is correct, but also verify the data voting system itself, specifically the input verification unit and the output verification unit, to achieve true self-verification.

[0064] Return to this application Figure 1 As shown, the verification processing unit 140 receives the second verification result Ei from the input verification unit 110 and the fifth verification result Eo from the output verification unit 130, thus determining the state of the data voting system. This state includes normal, abnormal, and the specific location of the abnormality. For example, if both Ei and Eo are normal, the data voting system is considered normal in terms of both the input data and the system itself. If Ei is abnormal, it indicates an internal error in the input verification unit 110; if Eo is abnormal, it indicates an internal error in the output verification unit 130 or the output logic unit 120.

[0065] In some embodiments, the verification processing unit 140 is further configured to determine a first processing mode based on the second verification result Ei and the fifth verification result Eo. The first processing mode includes any one or a combination of several of the following: no processing, refreshing input data, refreshing the first code verifier, refreshing the first multi-channel dual-track code verifier, refreshing the second code verifier, and refreshing the second code verifier. (See reference) Figure 1 As shown, the arrow pointing from the verification processing unit 140 to the input verification unit 110 indicates that a refresh instruction or command can be issued from the verification processing unit 140 to the input verification unit 110; the arrow pointing from the verification processing unit 140 to the output verification unit 130 indicates that a refresh instruction or command can be issued from the verification processing unit 140 to the output verification unit 130.

[0066] In some embodiments, the verification processing unit 140 is further configured to determine a second processing method based on the state of the data voting system after executing the first processing method. The state of the data voting system includes any one of normal, input verification unit error, output verification unit error, and output logic error. The second processing method includes: outputting an error report or refreshing the output logic unit 120. Table 3 shows the processing logic of the verification processing unit 140 in these embodiments.

[0067] Table 3. Processing logic of verification processing unit 140

[0068]

[0069]

[0070] As shown in Table 3, when both Ei and Eo are normal, no processing is required. When Ei is abnormal and Eo is normal, the voting system indicates an internal error in the input verification unit 110. First, the 3 / 6 code checker (i.e., the first code checker) in the input verification unit 110 is refreshed. If it returns to normal after the refresh, no further processing is needed; otherwise, the refresh continues. When both Ei and Eo are abnormal, the data voting system is judged to be in error in both the input verification unit 110 and the output verification unit 130. However, at this time, a first processing method can be performed first, i.e., re-reading the data and refreshing the first multi-channel dual-track code checker in the input verification unit 110. After the first processing method, the states of Ei and Eo are determined. If they are both normal, it indicates that the previous error was caused by an input data error; otherwise, it indicates that the input data is inconsistent. Further processing then reports the inconsistent data result to the output logic unit 120. Figure 1 The arrow from the verification processing unit 140 to the output logic unit 120 indicates the reporting direction of the result, and the arrow indicates that the verification processing unit 140 can output data and / or commands to the output logic unit 120.

[0071] In some embodiments, the output logic unit 120 is further configured to output the judgment result of each input data channel, the judgment result including normal and error.

[0072] As shown in Table 3, when Ei is normal and Eo is abnormal, the first processing method is to refresh the 3 / 6 code checker (i.e., the second code checker) in the output check unit 130. If it is normal after the refresh, the voting system status is that the output check unit 130 is faulty; otherwise, it is the output logic unit 120. The further processing in this case is to refresh the output logic unit 120. Figure 1 The arrow from the verification processing unit 140 to the output logic unit 120 indicates the direction of the refresh instruction.

[0073] In some embodiments, the output logic unit 120 is further configured to output the second verification result Ei and the fifth verification result Eo.

[0074] In summary, the different embodiments described above, Figure 1 The output data 102 can include the following three contents: (1) the third verification result OUT; (2) the judgment result of each input data; (3) the second verification result Ei and the fifth verification result Eo. Of course, the output logic unit 120 can also output other data or commands to external units as needed, and this application does not limit this.

[0075] Table 4 shows the processing logic of the verification processing unit 140 in some other embodiments. Compared with Table 3, this processing logic adds consideration of the predicted error state DATA_ERROR for each data path, that is, the judgment result of each input data path that the output logic unit 120 described above can output. Furthermore, the refresh function used here refreshes the entire data voting system, rather than only refreshing the 3 / 6 code checker as shown in Table 3. DATA_ERROR uses three data bits to represent the status of the three data paths, with 0 indicating that the data path is correct and 1 indicating that the data path is incorrect. The voter in Table 4 refers to the data voting system.

[0076] Table 4. Processing logic of verification processing unit 140

[0077]

[0078]

[0079] As shown in Table 4, when both Ei and Eo are normal, if DATA_ERROR is 000, it means that each data channel is normal and no processing is required. Otherwise, the received data is checked again. If DATA_ERROR becomes 000, no processing is required; otherwise, the voter is considered to be faulty.

[0080] When Ei is normal but Eo is abnormal, or when Ei is abnormal but Eo is normal, regardless of the DATA_ERROR value, the voter is refreshed, and the result is that the voter itself is faulty.

[0081] When both Ei and Eo are abnormal, different processing and judgment results are given according to the different DATA_ERROR values. When any one channel fails, the received data is re-verified. If DATA_ERROR is found, it indicates that the voter is correct and the input data is incorrect; otherwise, it indicates that the voter is incorrect. When all three data channels fail, the received data is re-verified, and a request for re-input data is made. If the error persists, the request is repeated. The health management unit here is an external unit of the data voting system, used to control input data 101 and receive output data 102, and further control the data voting system based on output data 102, such as issuing refresh commands. The data processing module is the module used to generate input data 101. The health management unit can issue refresh commands to this data processing module to obtain updated input data.

[0082] In some embodiments, input data 101 is generated by a data processing module and stored in a register. The data voting system 100 can obtain the required input data 101 from the register.

[0083] refer to Figure 1The data voting system 100 of this application not only verifies the input data 101 through the input verification unit 110, but also performs a second verification through the output verification unit 130 by combining the second verification result Ei and the third verification result OUT of the output logic unit 120 to obtain the fifth verification result Eo. The verification processing unit 140 determines the state of the data voting system 100 and the processing method to be taken based on the second verification result Ei and the fifth verification result Eo. It can verify both the input data and the data voting system itself at the same time, realizing true self-verification, which is beneficial to improving the reliability of the electronic system.

[0084] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0085] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0086] Some aspects of this application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "component," or "system." The processor may be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. Furthermore, aspects of this application may manifest as computer products residing in one or more computer-readable media, including computer-readable program code. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes, etc.), optical discs (e.g., compressed CDs, digital multifunction DVDs, etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0087] A computer-readable medium may contain a propagated data signal containing computer program code, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and so on, or suitable combinations thereof. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program code located on the computer-readable medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signals, or similar media, or any combination of the above media.

[0088] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0089] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. A self-checking data voting system, characterized by, It includes an input verification unit, an output logic unit, an output verification unit, and a verification processing unit, wherein, The input verification unit includes N1 first XOR units, N1 first multi-channel dual-track code verifiers, and a first code verifier. The first code verifier is a code verifier that takes N1 codes from 2*N1. The input verification unit is used to receive N2 input data, which are redundant data. Each input data includes M bits. The N2 input data are combined in pairs to form N1 data groups. Each first multi-channel dual-track code verifier is used to receive one group of the data groups, compare them, and output a first verification result based on the comparison result. Each first XOR unit is used to perform XOR processing on two different bits in one input data to obtain a first XOR result. The first XOR unit is also used to generate a pair of first test codes based on the first XOR result and the first verification result. N1 pairs of first test codes form the first input test set of the first code verifier. The first code verifier outputs a second verification result based on the first input test set. Here, N1 is a positive integer greater than or equal to 3, and N2 is an odd number greater than or equal to 3. The output logic unit is used to receive the first verification result and output a third verification result, wherein the third verification result includes a majority of consistent first verification results; The output verification unit includes N1 second XOR units, N1 second multi-channel dual-track code verifiers, and a second code verifier. The second code verifier is a code verifier that takes N1 bits from 2*N1. Each second multi-channel dual-track code verifier receives one input data path and one third verification result, compares them, and outputs a fourth verification result based on the comparison result. Each second XOR unit performs an XOR operation on two different bits in one input data path to obtain a second XOR result. The second XOR unit also generates a pair of second test codes based on the second XOR result and the fourth verification result. N1 pairs of second test codes form the second input test set of the second code verifier. The second code verifier outputs a fifth verification result based on the second input test set. The verification processing unit is used to determine the state of the data voting system based on the second verification result and the fifth verification result.

2. The data voting system of claim 1, wherein, Each pair of the first test codes consists of two bits including [0,1] or [1,0], and each pair of the second test codes consists of two bits including [0,1] or [1,0].

3. The data voting system of claim 1, wherein, Different first XOR units perform XOR processing on different bits in the input data, and different second XOR units perform XOR processing on different bits in the input data.

4. The data voting system of claim 1, wherein, The second verification result includes 2 data bits. The second verification result includes four types, namely [0,1], [1,0], [0,0], and [1,1]. Among them, [0,1] and [1,0] indicate that the second verification result and the input verification unit are both normal, and [0,0] and [1,1] indicate that the second verification result or the input verification unit is faulty.

5. The data voting system of claim 1, wherein, The fifth verification result includes two data bits and four types: [0,1], [1,0], [0,0], and [1,1]. [0,1] and [1,0] indicate that both the fifth verification result and the output verification unit are normal, while [0,0] and [1,1] indicate that either the fifth verification result or the output verification unit is faulty.

6. The data voting system of claim 1, wherein, The verification processing unit is further configured to determine a first processing method based on the second verification result and the fifth verification result. The first processing method includes any one or a combination of the following: no processing, refreshing the input data, refreshing the first code verifier, refreshing the first multi-channel dual-track code verifier, refreshing the second code verifier, and refreshing the second code verifier.

7. The data voting system as described in claim 6, characterized in that, The verification processing unit is further configured to determine a second processing method based on the state of the data voting system after executing the first processing method. The state of the data voting system includes any one of normal, input verification unit error, output verification unit error, and output logic error. The second processing method includes: outputting an error report or refreshing the output logic unit.

8. The data voting system as described in claim 1, characterized in that, The output logic unit is also used to output the judgment result of each input data channel, and the judgment result includes normal and error.

9. The data voting system as described in claim 1, characterized in that, The output logic unit is also used to output the second verification result and the fifth verification result.

10. The data voting system as described in claim 1, characterized in that, The input data is in units of one byte, and each input data consists of 8 bits.

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