NOR gate device and method for manufacturing the same

Abstract

The application discloses a NOR gate device and a preparation method thereof, which can be applied to the field of semiconductor devices. The device comprises a first conductive type substrate, a second conductive type substrate, a first conductive type doped region, a second conductive type doped region, a first gate structure and a second gate structure. The first conductive type substrate, the first gate structure and the second conductive type substrate are sequentially arranged along a first direction. The second gate structure is arranged along a third direction with the first gate structure. Two second conductive type doped regions are respectively arranged at two ends of the side of the first conductive type substrate which is in contact with the first gate structure. Two first conductive type doped regions are respectively arranged at two ends of the side of the second conductive type substrate which is in contact with the first gate structure. Thus, the sidewall channel is controlled by the first gate structure, and the surface channel is controlled by the second gate structure, so that the combination of the carrier surface transport and the longitudinal transport is realized, the limitation of the plane layout is broken, and the layout area of the NOR gate is greatly compressed.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a NOR gate device and its fabrication method. Background Technology

[0002] As integrated circuits continue to develop towards higher integration and smaller size, the demand for the number of logic gates per unit area of ​​chips is increasing. As a core general-purpose logic device in mathematical logic, the layout area of ​​NOR gates directly affects the overall integration density of chips.

[0003] Currently, NOR gates generally employ a two-dimensional planar structure, with each gate consisting of four independent transistors. Two P-channel MOS transistors (PMOS) are connected in series as pull-up diodes connected to the power supply, and two N-channel MOS transistors (NMOS) are connected in parallel as pull-down diodes connected to ground. A single NOR gate must occupy the entire layout space of four independent transistors, and isolation gaps must be reserved between the transistors to avoid crosstalk between devices. Due to the limitations of the two-dimensional physical layout, even with miniaturization through photolithography or optimization of the planar layout design, the reduction in the layout area of ​​NOR gates remains limited.

[0004] Therefore, how to reduce the layout area of ​​NOR gates becomes a problem that needs to be solved. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a NOR gate device and its fabrication method, which can reduce the layout area of ​​the NOR gate.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a NOR gate device, the device comprising: a first conductivity type substrate, a second conductivity type substrate, a first conductivity type doped region, a second conductivity type doped region, a first gate structure, and a second gate structure;

[0008] The first conductivity type substrate, the first gate structure, and the second conductivity type substrate are arranged sequentially along a first direction; the second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure, and the second conductivity type substrate.

[0009] Two second conductivity type doped portions are respectively disposed at both ends on the side where the first conductivity type substrate contacts the first gate structure; two first conductivity type doped portions are respectively disposed at both ends on the side where the second conductivity type substrate contacts the first gate structure.

[0010] The first gate structure is in contact with the undoped regions of the first conductivity type substrate and the second conductivity type substrate; the second gate structure is in contact with the first gate structure, the undoped regions of the first conductivity type substrate and the second conductivity type substrate.

[0011] Optionally, the first conductivity type doped region includes a first lightly doped region and a first heavily doped region; the doping concentration and doping depth of the first heavily doped region are both greater than those of the first lightly doped region.

[0012] The first highly doped region is located on the side of the first lightly doped region near the edge of the substrate of the second conductivity type.

[0013] Optionally, the device further includes an insulating barrier located between the first conductivity type doped region and the second conductivity type doped region.

[0014] Optionally, the first gate structure includes: a first spacer layer and a first gate;

[0015] The two first spacer layers are disposed at both ends of the first gate in the second direction, and are used to isolate the first gate from the first conductivity type doped region and the second conductivity type doped region; the second direction is the arrangement direction of the two first conductivity type doped regions.

[0016] Optionally, the first gate structure further includes: a first gate dielectric layer;

[0017] The first gate dielectric layer is located on the first gate sidewall.

[0018] Optionally, the second gate structure includes: a second spacer layer and a second gate;

[0019] The two second spacer layers are disposed at both ends of the second gate in the second direction.

[0020] Optionally, the device further includes: a shared drain contact, a first source contact, and a second source contact;

[0021] The shared drain contact is connected to one doped region of the first conductivity type and one doped region of the second conductivity type; the first source contact is connected to another doped region of the first conductivity type; and the second source contact is connected to another doped region of the second conductivity type.

[0022] Optionally, the height of the first gate structure in the third direction is greater than or equal to the height of the first conductivity type substrate and the second conductivity type substrate in the third direction.

[0023] Secondly, embodiments of this application provide a method for fabricating a NOR gate device, the method comprising:

[0024] Provide a base;

[0025] A substrate is epitaxially grown on the substrate;

[0026] The substrate is divided into a first substrate and a second substrate by etching to form trenches that penetrate the substrate;

[0027] The first substrate is implanted with ions of a first conductivity type to form a substrate of the first conductivity type; the second substrate is implanted with ions of a second conductivity type to form a substrate of the second conductivity type.

[0028] A first gate structure is fabricated within the trench;

[0029] A second gate structure is fabricated above the first gate structure, the first conductivity type substrate, and the second conductivity type substrate; the second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure, and the second conductivity type substrate;

[0030] Ion implantation of a second conductivity type is performed at both ends of the side where the first conductivity type substrate contacts the first gate structure to form a second conductivity type doped region; ion implantation of a first conductivity type is performed at both ends of the side where the second conductivity type substrate contacts the first gate structure to form a first conductivity type doped region; the first gate structure and the second gate structure are in contact with the undoped regions of the first conductivity type substrate and the second conductivity type substrate.

[0031] Optionally, the step of performing ion implantation of a first conductivity type at both ends on the side where the second conductivity type substrate contacts the first gate structure to form a first conductivity type doped region includes:

[0032] Ion implantation of the first conductivity type is performed at both ends of the side where the second conductivity type substrate contacts the first gate structure to form a first lightly doped region;

[0033] In the first lightly doped region, ions of the first conductivity type are implanted again on the side near the edge of the substrate of the second conductivity type to form a first highly doped region; the doping concentration and doping depth of the first highly doped region are both greater than those of the first lightly doped region.

[0034] Compared with the prior art, this application has the following beneficial effects:

[0035] This application provides a NOR gate device, comprising: a first conductivity type substrate, a second conductivity type substrate, a first conductivity type doped region, a second conductivity type doped region, a first gate structure, and a second gate structure; the first conductivity type substrate, the first gate structure, and the second conductivity type substrate are arranged sequentially along a first direction; the second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure, and the second conductivity type substrate; two second conductivity type doped regions are disposed at both ends on the side where the first conductivity type substrate and the first gate structure are in contact; two first conductivity type doped regions are disposed at both ends on the side where the second conductivity type substrate and the first gate structure are in contact; the first gate structure is in contact with the undoped regions of the first conductivity type substrate and the second conductivity type substrate; the second gate structure is in contact with the first gate structure, the undoped regions of the first conductivity type substrate, and the undoped regions of the second conductivity type substrate.

[0036] Thus, the first conductivity type substrate, the first gate structure, and the second conductivity type substrate are stacked along the first direction, and the second gate structure is located above the first conductivity type substrate, the first gate structure, and the second conductivity type substrate. The N-type substrate, the P-type doped region, and the gate structure form a PMOS, and the P-type substrate, the N-type doped region, and the gate structure form an NMOS. The sidewall channel is controlled by the first gate structure, and the surface channel is controlled by the second gate structure. By combining the buried gate (first gate structure) and the conventional gate (second gate structure), the same channel is controlled in parallel by multiple gate inputs, realizing dual-input port gate integration. The combination of carrier surface transport and vertical transport is realized by the buried gate sidewall and the conventional gate bottom, breaking through the planar layout limitation and significantly compressing the layout area of ​​the NOR gate. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A three-dimensional structural diagram of a NOR gate device provided in an embodiment of this application;

[0039] Figure 2 A top cross-sectional view of a NOR gate device provided in an embodiment of this application;

[0040] Figure 3 A side cross-sectional view of a NOR gate device provided in an embodiment of this application;

[0041] Figure 4 A three-dimensional structural diagram of another NOR gate device provided in an embodiment of this application;

[0042] Figure 5 A top view of a NOR gate device provided in an embodiment of this application;

[0043] Figure 6 A top view of another NOR gate device provided in an embodiment of this application;

[0044] Figure 7 A three-dimensional structural diagram of another NOR gate device provided in an embodiment of this application;

[0045] Figure 8 A three-dimensional structural diagram of another NOR gate device provided in the embodiments of this application.

[0046] Figure 9 This is a flowchart illustrating a method for fabricating a NOR gate device, as provided in an embodiment of this application.

[0047] Explanation of reference numerals in the attached figures: 100 - Substrate; 110 - Substrate of the first conductivity type; 120 - Substrate of the second conductivity type; 210 - Doped region of the first conductivity type; 211 - First lightly doped region; 212 - First heavily doped region; 220 - Doped region of the second conductivity type; 221 - Second lightly doped region; 222 - Second heavily doped region; 310 - First gate structure; 311 - First spacer layer; 312 - First gate; 313 - First gate dielectric layer; 320 - Second gate structure; 321 - Second spacer layer; 322 - Second gate; 400 - Insulating barrier; 510 - Shared drain contact; 520 - First source contact; 530 - Second source contact; 600 - Buried oxide layer. Detailed Implementation

[0048] The NOR gate device and its fabrication method provided in this application can be used in the field of semiconductor devices. The above is only an example and does not limit the application field of the NOR gate device and its fabrication method provided in this application.

[0049] The terms "first," "second," "third," and "fourth," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.

[0050] In the embodiments of this application, the terms "as an example" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "as an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.

[0051] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0052] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0053] See Figure 1 The figure is a three-dimensional structural diagram of a NOR gate device provided in an embodiment of this application. The NOR gate device includes: a first conductivity type substrate 110, a second conductivity type substrate 120, a first conductivity type doped region 210, a second conductivity type doped region 220, a first gate structure 310, and a second gate structure 320.

[0054] The first conductivity type is either N-type or P-type; the second conductivity type is either P-type or N-type, which is the opposite of the first conductivity type.

[0055] The first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120 are arranged sequentially along a first direction; the second gate structure 320 and the first gate structure 310 are arranged along a third direction; the third direction is perpendicular to the plane in which the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120 are located.

[0056] The first conductivity type substrate 110 and the second conductivity type substrate 120 can be fabricated by constant doping ion doping, that is, the impurity concentration is uniformly distributed throughout the entire region and does not change with depth or lateral position. This avoids potential inhomogeneity caused by concentration fluctuations, ensuring the consistency of the transistor threshold voltage, and can be achieved through a single ion implantation or uniform diffusion, making the fabrication process relatively simple.

[0057] PMOS and NMOS have different carrier types, resulting in a natural difference in mobility. NMOS uses electrons as carriers, which move faster under the same electric field, generating a larger conduction current. PMOS uses holes as carriers, and the mobility of holes is only 1 / 3 to 1 / 2 that of electrons, resulting in a much smaller conduction current under the same conditions. To avoid excessive pull-down current in NMOS and insufficient pull-up current in PMOS due to the mobility difference, the ion doping concentration of the first conductivity type substrate 110 and the second conductivity type substrate 120 can be adjusted to balance the current driving capabilities of PMOS and NMOS.

[0058] For example, in the first conductivity type substrate 110 and the second conductivity type substrate 120, the N-type substrate can have a higher doping concentration to reduce electron mobility and avoid excessive pull-down current that could lead to excessively rapid charge discharge at the output terminal. For instance, the doping concentration of the N-type substrate can be 3e18cm. -3 To control the Vth of the NMOS within the typical range of 0.5~1V, ensuring full conduction at an input of 2.5V and complete cutoff at an input of -2.5V; the P-type substrate can use a lower doping concentration to improve hole mobility, compensating for its mobility disadvantage and ensuring that the PMOS has a sufficiently large pull-up current. For example, the doping concentration of the P-type substrate can be 1e18cm. -3 This is to control the Vth of the PMOS within the typical value of -0.5 to -1V, ensuring full conduction when the input is -2.5V and complete cut-off when the input is 2.5V.

[0059] Two second conductivity type doped regions 220 are respectively disposed at both ends of the side where the first conductivity type substrate 110 contacts the first gate structure 310; two first conductivity type doped regions 210 are respectively disposed at both ends of the side where the second conductivity type substrate 120 contacts the first gate structure 310. The first gate structure 310 is in contact with the undoped regions of the first conductivity type substrate 110 and the second conductivity type substrate 120; the second gate structure 320 is in contact with the first gate structure 310, the undoped region of the first conductivity type substrate 110, and the undoped region of the second conductivity type substrate 120.

[0060] The first gate structure 310 is used to control, for example Figure 2 The sidewall channel IN1 is shown. As an example, the height of the first gate structure 310 in the third direction is greater than or equal to the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction.

[0061] The height fluctuations of the first conductivity type substrate 110, the second conductivity type substrate 120, and the first gate structure 310 in the third direction have a relatively small impact on device performance. A larger process window can be configured in production. For example, the center value of the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction can be 0.25 μm, which is consistent with the epitaxial layer thickness of the development platform. In production, its height can be allowed to fluctuate within the range of 0.25 μm ± 10% to be compatible with existing mass production capabilities. The height of the first gate structure 310 in the third direction can be 0.3 μm to match the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction. In production, its height can be allowed to fluctuate within the range of 0.3 μm ± 0.1 μm.

[0062] For example, the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction can be 0.225 μm to provide a smaller vertical stacking height and further optimize area efficiency; or the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction can be 0.25 μm to match the carrier transport requirements and ensure the device's conduction efficiency; or the height of the first conductivity type substrate 110 and the second conductivity type substrate 120 in the third direction can be 0.275 μm to increase the silicon material reserve in the channel region and improve the device's current drive capability. The height of the first gate structure 310 in the third direction can be 0.2 μm to compress the vertical dimension; or it can be 0.3 μm to balance device size and gate control capability; or it can be 0.4 μm to ensure that the first gate structure 310 completely covers the substrate sidewalls and enhances the gate control capability.

[0063] Therefore, the electric field of the sidewall of the first gate structure (buried gate) 310 can completely cover the N-type channel region and the P-type channel sidewall in the third direction, which can more effectively modulate the carrier concentration in the channel. The buried gate independently controls the conduction state of the sidewall channel. When the buried gate input is high (2.5V), the NMOS sidewall channel is turned on and the PMOS sidewall channel is turned off; when the buried gate input is low (-2.5V), the PMOS sidewall channel is turned on and the NMOS sidewall channel is turned off.

[0064] The second gate structure 320 is used to control, for example... Figure 3 The surface trench IN2 is shown. The height of the second gate structure 320 in the third-order direction must be less than the substrate height to avoid excessive thickness of the second gate structure 320, which would increase the gate capacitance, reduce the switching speed, and prevent substrate stress imbalance that could lead to wafer breakage during processing. Fluctuations in the height of the second gate structure 320 in the third-order direction have a relatively small impact on device performance, allowing for a larger process window in production. For example, if the substrate height is within the range of 0.25μm ± 10%, the height of the second gate structure 320 can be 0.125μm, consistent with the development platform, to ensure compatibility with existing mass production capabilities. In production, the height of the second gate structure 320 can fluctuate within the range of 0.125μm ± 10%, such as 0.137μm, 0.125μm, or 0.113μm.

[0065] The second gate structure (conventional gate) 320 independently controls the conduction state of the surface channel. When the conventional gate input is high (2.5V), the NMOS surface channel is turned on and the PMOS surface channel is turned off; when the conventional gate input is low (-2.5V), the PMOS surface channel is turned on and the NMOS surface channel is turned off.

[0066] As long as the NMOS in either the surface channel or the sidewall channel is turned on, the overall pull-down transistor is turned on, and the output is pulled to VSS (0V). Only when both PMOS in both channels are turned on, the overall pull-up transistor is turned on, and the output is pulled to VDD (2.5V), thus realizing the OR NOT gate logic function.

[0067] Optionally, the first conductivity type substrate 110 and the second conductivity type substrate 120 can be formed on the substrate by epitaxial growth, such as on the buried oxide layer 600 formed in the substrate. The height of the buried oxide layer 600 in the third direction is much greater than the height difference between the gate structure 300 and the substrate. Its height fluctuation has a small impact on device performance, and a larger process window can be configured in production. For example, the height of the buried oxide layer 600 can be 0.75 μm, consistent with the development platform, to be compatible with existing mass production capabilities. In production, the height of the buried oxide layer 600 can fluctuate within the range of 0.75 μm ± 10%.

[0068] The buried oxide layer 600 provides physical support and a stable space reference for NMOS and PMOS, and isolates the NMOS and PMOS located above the buried oxide layer 600 from the lower part of the substrate, ensuring that the transistors can operate independently.

[0069] Thus, the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120 are stacked along the first direction, and the second gate structure 320 is located above the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120. The N-type substrate, the P-type doped region, and the gate structure form a PMOS, and the P-type substrate, the N-type doped region, and the gate structure form an NMOS. The first gate structure 310 controls the sidewall channel, and the second gate structure 320 controls the surface channel. By combining the buried gate (first gate structure 310) and the conventional gate (second gate structure 320), the same channel is controlled in parallel by multiple gate inputs, realizing dual-input port gate integration. By combining the surface transport and vertical transport of charge carriers through the buried gate sidewall and the conventional gate bottom, the planar layout limitation is broken, and the layout area of ​​the NOR gate can be greatly compressed, which can reduce the area occupied by the NOR gate by 60%~70%.

[0070] As an example, such as Figure 4 As shown, the first conductivity type doped region 210 can be a gradient doped region. Specifically, the first conductivity type doped region 210 includes a first lightly doped region 211 and a first heavily doped region 212; the doping concentration and doping depth of the first heavily doped region 212 are both greater than those of the first lightly doped region 211; the first heavily doped region 212 is located on the side of the first lightly doped region 211 near the edge of the second conductivity type substrate 120.

[0071] Similarly, the second conductivity type doped region 220 can also be a gradient doped region. Specifically, the second conductivity type doped region 220 includes a second lightly doped region 221 and a second highly doped region 222; the doping concentration and doping depth of the second highly doped region 222 are both greater than those of the second lightly doped region 221; the second highly doped region 222 is located on the side of the second lightly doped region 221 near the edge of the first conductivity type substrate 110.

[0072] Among them, the first highly doped region 212 and the second highly doped region 222 are the main carrier injection regions, which are used to provide sufficient carriers; the first lightly doped region 211 and the second lightly doped region 221 are the transition regions between the highly doped region and the channel, which are used to connect the carrier concentration gradient between the channel and the highly doped region.

[0073] For example, the highly doped region (i.e., the source / drain region, SD) can be selected from 3e20cm. -3 ~5e20cm -3 High peak doping concentrations, such as a doping concentration of 4e20cm. -3 This ensures that the highly doped region provides sufficient electron or hole carriers for the device; the lightly doped region (LDD) can use 1e19cm -3 ~3e19cm -3 Low to medium peak doping concentrations, such as a doping concentration of 2e19cm. -3 This creates a smooth concentration gradient between the channel, lightly doped region, and heavily doped region. This reduces the migration resistance of charge carriers caused by abrupt concentration changes during transport, allowing charge carriers to be efficiently injected into the channel from the heavily doped region through the lightly doped region.

[0074] The doping concentration in the heavily doped and lightly doped regions affects the logic stability of the device. To ensure high consistency in the fabricated devices, a smaller process window can be set for the doping concentration in the heavily doped and lightly doped regions, such as controlling the doping concentration to fluctuate within ±5% of the corresponding center value. For example, the doping concentration in the heavily doped region can be selected from 4e20cm. -3 Within ±5%, for example, it can be 3.8e20cm. -3 4e20cm -3 Or 4.2e20cm -3 To balance low on-current and low impurity diffusion risk, the doping concentration in the low-doped region can be selected from 2e19cm. -3 Within ±5%, for example, it can be 1.9e19cm. -3 2e19cm -3 Or 2.1e19cm -3 This is done to match the doping concentration in the highly doped region and smooth the concentration gradient.

[0075] The doping depth of the heavily doped region is greater than that of the lightly doped region. Heavier doping reduces the bulk resistance of the source / drain regions, facilitating the formation of ohmic contacts between the metal and semiconductor. Lightly doped regions serve as current transition channels between the channel and source / drain regions, reducing carrier losses during transport and improving the transmission efficiency of pull-down current in NMOS and pull-up current in PMOS. The doping depth of the heavily and lightly doped regions affects the logic stability of the device. To ensure high consistency in the fabricated devices, a smaller process window can be set for the doping depth of the heavily and lightly doped regions, such as controlling the doping depth to fluctuate within ±5% of the corresponding center value. For example, the doping depth of the highly doped region can be in the range of 0.25 μm ± 5%, such as 0.238 μm, 0.25 μm or 0.262 μm, to match the substrate thickness and ensure effective contact between the source / drain region and the channel; the doping depth of the lightly doped region can be in the range of 0.05 μm ± 5%, such as 0.048 μm, 0.05 μm or 0.052 μm, to match the doping depth of the highly doped region and optimize the electric field distribution.

[0076] Gradient doping design is performed on the first conductivity type doped region 210 and the second conductivity type doped region 220. By gradient transition of doping concentration and doping depth, the gate's control capability over the channel can be enhanced, avoiding increased leakage current or logic misjudgment caused by short-channel effect, and improving gate control accuracy.

[0077] See Figure 5 The figure is a top view of a NOR gate device provided in an embodiment of this application, wherein the first gate structure 310 includes a first spacer layer 311 and a first gate 312.

[0078] Two first spacer layers 311 are disposed at both ends of the first gate 312 in the second direction, for isolating the first gate 312 from the first conductivity type doped region 210 and the second conductivity type doped region 220; wherein, the second direction is the arrangement direction of the two first conductivity type doped regions 210.

[0079] The first gate 312 is located at a position corresponding to the undoped region of the sidewall of the first conductivity type substrate 110 and the second conductivity type substrate 120. The first spacer layer 311 is partially or completely in contact with the first conductivity type doped region 210 and the second conductivity type doped region 220. The first spacer layer 311 is used to block the electrical connection between the first gate 312 and the first conductivity type doped region 210 and the second conductivity type doped region 220, and to isolate the parasitic leakage current between the first gate 312 and the source / drain region.

[0080] The length of the first gate 312 in the second direction needs to be matched with the distance between two doped regions of the same conductivity type to determine the switching characteristics of the device. For example, the length of the first gate 312 in the second direction can be selected from the range of 0.6 μm ± 0.2 μm. For instance, the length of the first gate 312 in the second direction can be 0.4 μm to reduce channel resistance and improve switching speed by shortening the gate length; or the length of the first gate 312 in the second direction can be 0.8 μm to suppress short-channel effects by increasing the gate length; or the length of the first gate 312 in the second direction can be 0.6 μm to balance switching speed and short-channel effects.

[0081] The first spacer layer 311 is used to prevent the first gate 312 from directly contacting the source / drain and causing a short circuit. Its length in the second direction matches the distance between two doped regions of the same conductivity type and the length of the first gate 312. Exemplarily, the length of the first spacer layer 311 in the second direction can be selected from the range of 0.15 μm ± 0.05 μm. For example, the length of the first spacer layer 311 in the second direction can be 0.1 μm, 0.15 μm, or 0.2 μm.

[0082] like Figure 6 As shown, this figure is a top view of another NOR gate device provided in the embodiment of this application. The first gate structure 310 may also include a first gate dielectric layer 313. The first gate dielectric layer 313 is located on the sidewall of the first gate 312 and is used to isolate the first gate 312 from the sidewall channel, prevent direct current conduction between the two, and avoid short circuit due to direct physical contact between the first gate 312 and the sidewall channel.

[0083] The thinner the first gate dielectric layer 313, the larger the gate capacitance, the stronger the drive current, and the faster the switching speed. However, if the first gate dielectric layer 313 is too thin, it will cause gate tunneling leakage. In one embodiment, the thickness of the first gate dielectric layer 313 in the first direction can fluctuate within the range of 5nm ± 0.2nm to balance the requirements of fast drive and low leakage.

[0084] As an example, the width of the first gate 312 in the first direction is matched with the current conduction capability, for example, it can be selected from the range of 0.3 μm ± 10%; the widths of the first conductivity type doped region 210 and the second conductivity type doped region 220 in the first direction are constrained by the channel length, for example, they can fluctuate within the range of 0.1 μm ± 5% during production.

[0085] See Figure 7 The figure is a three-dimensional structural diagram of another NOR gate device provided in the embodiment of this application, wherein the second gate structure 320 includes a second spacer layer 321 and a second gate 322.

[0086] Two second spacer layers 321 are disposed at both ends of the second gate 322 in the second direction.

[0087] The second gate 322 is located at a position corresponding to the undoped region on the upper surface of the first conductivity type substrate 110 and the second conductivity type substrate 120. The second spacer layer 321 is partially or completely in contact with the first conductivity type doped region 210 and the second conductivity type doped region 220. The second spacer layer 321 is used to block the electrical connection between the second gate 322 and the first conductivity type doped region 210 and the second conductivity type doped region 220, and to isolate the parasitic leakage current between the second gate 322 and the source / drain regions.

[0088] The length of the second gate 322 in the second direction needs to match the distance between two doped regions of the same conductivity type to determine the switching characteristics of the device. In one embodiment, the length of the second gate 322 in the second direction can be greater than the length of the first gate 312 in the second direction and less than the total length of the first gate structure 310 in the second direction. For example, the length of the second gate 322 in the second direction can be selected from the range of 0.7 μm ± 0.5 nm, such as 0.7 μm.

[0089] The second spacer layer 321 is used to prevent the second gate 322 from directly contacting the source / drain, thus preventing a short circuit. Its length in the second direction matches the distance between two doped regions of the same conductivity type and the length of the second gate 322. Exemplarily, the length of the second spacer layer 321 in the second direction can be selected from the range of 0.15 μm ± 0.05 μm. For example, the length of the second spacer layer 311 in the second direction can be 0.1 μm, 0.15 μm, or 0.2 μm.

[0090] The second gate structure 320 may also include a second gate dielectric layer, which is located at the bottom of the second gate 322 and is used to isolate the second gate 322 from the surface channel, prevent direct current conduction between the two, and avoid short circuit due to direct physical contact between the second gate 322 and the surface channel.

[0091] The thinner the second gate dielectric layer, the larger the gate capacitance, the stronger the drive current, and the faster the switching speed. However, an excessively thin second gate dielectric layer can lead to gate tunneling leakage. In one embodiment, the thickness of the second gate dielectric layer in the first direction can fluctuate within the range of 5nm ± 0.2nm to balance the requirements of fast drive and low leakage.

[0092] The width of the second gate 322 in the first direction can be equal to the sum of the widths of the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120 in the first direction. For example, the width of the second gate 322 can be 2.3 μm.

[0093] See Figure 8 The figure is a three-dimensional structural diagram of another NOR gate device provided in the embodiment of this application. The NOR gate device includes: an insulating isolation wall 400, a shared drain contact 510, a first source contact 520, and a second source contact 530.

[0094] The insulating barrier 400 is located between the first conductivity type doped region 210 and the second conductivity type doped region 220; the shared drain contact 510 connects one first conductivity type doped region 210 and one second conductivity type doped region 220; the first source contact 520 connects to another first conductivity type doped region 210; and the second source contact 530 connects to another second conductivity type doped region 220.

[0095] The shared drain contact 510 is used to connect to the output terminal; of the first source contact 520 and the second source contact 530, the contact located at the PMOS source is used to connect to the power supply, and the contact located at the NMOS source is used to connect to ground. Thus, when the PMOS is turned on, the drain pulls the output to VDD (high level); when the NMOS is turned on, the drain pulls the output to VSS (low level), thereby outputting a NOR logic result through the shared drain contact 510.

[0096] See Figure 9 The figure is a flowchart of a method for fabricating a NOR gate device according to an embodiment of this application. The method includes:

[0097] S901: Provides a substrate.

[0098] As an example, the substrate may include, but is not limited to, a buried oxide layer 600, which provides physical support and a stable space reference for the NMOS and PMOS and isolates the NMOS and PMOS located above the buried oxide layer 600 from the lower part of the substrate.

[0099] S902: Epitaxial growth of substrate 100 on a substrate.

[0100] For example, such as Figure 9 As shown in (a), a Si substrate 100 can be epitaxially grown over a buried oxide layer 600.

[0101] S903: By etching, a trench is formed through the substrate 100, dividing the substrate 100 into a first substrate 101 and a second substrate 102.

[0102] Specifically, etching can be used to divide the substrate 100 corresponding to a single NOR gate device into two parts, namely a first substrate 101 and a second substrate 102, as shown below. Figure 9 As shown in (b). The first substrate 101 and the second substrate 102 may have the same dimensions.

[0103] S904: Ion implantation of a first conductivity type is performed on the first substrate 101 to form a first conductivity type substrate 110; ion implantation of a second conductivity type is performed on the second substrate 102 to form a second conductivity type substrate 120.

[0104] Specifically, ion implantation can be performed on the first substrate 101 and the second substrate 102 using a constant doping method to obtain substrates with different conductivity types, such as... Figure 9 As shown in (d), the ion implantation energy can be 3e18cm⁻¹. -3 .

[0105] Ion implantation energy affects the logic stability of devices. A smaller process window can be set, for example, a process window of 3e18cm. -3 ±5%.

[0106] For example, to avoid ion implantation into the trench between the first substrate 101 and the second substrate 102 during ion implantation, a shallow trench isolation deposition can be performed in the trench before ion implantation to deposit an insulating oxide 01, such as silicon oxide, into the trench to fill it. Figure 9 As shown in (c).

[0107] S905: The first gate structure 310 is fabricated in the trench.

[0108] Specifically, the insulating oxide 01 deposited in the trench can be etched first to obtain the first gate trench and the insulating isolation wall 400; then, an insulating material, such as silicon nitride, is deposited in the gate trench; subsequently, the insulating material is etched to obtain the second gate trench and the first spacer layer 311; finally, a gate material, such as polysilicon, is filled in the second gate trench to form the first gate 312, such as... Figure 9 As shown in (e), a first gate structure 310 comprising a first spacer layer 311 and a first gate 312 is thus obtained.

[0109] For example, after obtaining the second gate trench and the first spacer layer 311, a first gate dielectric layer 313 covering the sidewalls and bottom of the second gate trench can be deposited first, and then gate material can be filled in the second gate trench to form the first gate 312.

[0110] S906: A second gate structure 320 is fabricated over the first gate structure 310, the first conductivity type substrate 110, and the second conductivity type substrate 120.

[0111] The second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure and the second conductivity type substrate.

[0112] Specifically, a gate material, such as polysilicon, can be deposited first over the undoped regions of the first gate structure 310, the first conductivity type substrate 110, and the second conductivity type substrate 120; then, the gate material layer is etched to form a second gate 322 located over the undoped regions of the first gate structure 310, the first conductivity type substrate 110, and the second conductivity type substrate 120. Figure 9 As shown in (f); finally, a second spacer layer 321 is deposited at both ends of the second gate 322 in the second direction, as shown in (f). Figure 9 As shown in (g), a second gate structure 320 including a second spacer layer 321 and a second gate 322 is obtained.

[0113] For example, before depositing the gate material, a second gate dielectric layer may be deposited over the first gate structure 310, the undoped region of the first conductivity type substrate 110, and the undoped region of the second conductivity type substrate 120 to isolate the second gate 322 from the surface channel.

[0114] S907: Ion implantation of the second conductivity type is performed at both ends of the first conductivity type substrate 110 and the first gate structure 310 on the contact side to form a second conductivity type doped region 220; ion implantation of the first conductivity type is performed at both ends of the second conductivity type substrate 120 and the first gate structure 310 on the contact side to form a first conductivity type doped region 210.

[0115] The first gate structure 310 and the second gate structure 320 are in contact with the undoped regions of the first conductivity type substrate 110 and the second conductivity type substrate 120.

[0116] Optionally, ion implantation of a first conductivity type with a lower doping concentration and shallower doping depth can be performed at both ends of the side where the second conductivity type substrate 120 contacts the first gate structure 310 to form a first lightly doped region 211; ion implantation of a second conductivity type with a lower doping concentration and shallower doping depth can be performed at both ends of the side where the first conductivity type substrate 110 contacts the first gate structure 310 to form a second lightly doped region 221, such as... Figure 9 As shown in (h); then, in the first lightly doped region 211, ions of the first conductivity type with a higher doping concentration and deeper doping depth are implanted again on the side near the edge of the second conductivity type substrate 120 to form the first heavily doped region 212; in the second lightly doped region 221, ions of the second conductivity type with a higher doping concentration and deeper doping depth are implanted again on the side near the edge of the first conductivity type substrate 110 to form the second heavily doped region 222, as shown in (h); then, ions of the second conductivity type with a higher doping concentration and deeper doping depth are implanted again on the side near the edge of the first conductivity type substrate 110 to form the second heavily doped region 222, as shown in (h); Figure 9As shown in (i). The doping concentration and doping depth of the first highly doped region 212 are both greater than those of the first lightly doped region 211; the doping concentration and doping depth of the second highly doped region 222 are both greater than those of the second lightly doped region 221.

[0117] After forming the second gate structure 320, a shared drain contact 510, a first source contact 520, and a second source contact 530 can be fabricated using a metal deposition process. The shared drain contact 510 connects a first conductivity type doped region 210 and a second conductivity type doped region 220; the first source contact 520 connects to another first conductivity type doped region 210; and the second source contact 530 connects to another second conductivity type doped region 220, as shown below. Figure 9 As shown in (j).

[0118] Thus, the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120 are stacked along the first direction, and the second gate structure 320 is located above the first conductivity type substrate 110, the first gate structure 310, and the second conductivity type substrate 120. The N-type substrate, the P-type doped region, and the gate structure form a PMOS, and the P-type substrate, the N-type doped region, and the gate structure form an NMOS. The first gate structure 310 controls the sidewall channel, and the second gate structure 320 controls the surface channel. By combining the buried gate (first gate structure 310) and the conventional gate (second gate structure 320), the same channel is controlled in parallel by multiple gate inputs, realizing dual-input port gate integration. By combining the surface transport and vertical transport of charge carriers through the buried gate sidewall and the conventional gate bottom, the planar layout limitation is broken, and the layout area of ​​the NOR gate can be greatly compressed, which can reduce the area occupied by the NOR gate by 60%~70%.

[0119] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the structural embodiments. The method embodiments described above are merely illustrative, and some or all of the steps can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement them without creative effort.

[0120] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A NOR gate device, characterized in that, The device includes: a first conductivity type substrate, a second conductivity type substrate, a first conductivity type doped region, a second conductivity type doped region, a first gate structure, and a second gate structure; The first conductivity type substrate, the first gate structure, and the second conductivity type substrate are arranged sequentially along a first direction; the second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure, and the second conductivity type substrate. Two second conductivity type doped portions are respectively disposed at both ends on the side where the first conductivity type substrate contacts the first gate structure; two first conductivity type doped portions are respectively disposed at both ends on the side where the second conductivity type substrate contacts the first gate structure. The first gate structure is in contact with the undoped regions of the first conductivity type substrate and the second conductivity type substrate; the second gate structure is in contact with the first gate structure, the undoped regions of the first conductivity type substrate and the second conductivity type substrate.

2. The device according to claim 1, characterized in that, The first conductivity type doped region includes a first lightly doped region and a first heavily doped region; the doping concentration and doping depth of the first heavily doped region are both greater than those of the first lightly doped region; The first highly doped region is located on the side of the first lightly doped region near the edge of the substrate of the second conductivity type.

3. The device according to claim 1, characterized in that, The device further includes an insulating isolation wall located between the first conductivity type doped region and the second conductivity type doped region.

4. The device according to claim 1, characterized in that, The first gate structure includes: a first spacer layer and a first gate; The two first spacer layers are disposed at both ends of the first gate in the second direction, and are used to isolate the first gate from the first conductivity type doped region and the second conductivity type doped region; the second direction is the arrangement direction of the two first conductivity type doped regions.

5. The device according to claim 4, characterized in that, The first gate structure further includes: a first gate dielectric layer; The first gate dielectric layer is located on the first gate sidewall.

6. The device according to claim 1, characterized in that, The second gate structure includes: a second spacer layer and a second gate; The two second spacer layers are disposed at both ends of the second gate in the second direction.

7. The device according to claim 1, characterized in that, The device further includes: a shared drain contact, a first source contact, and a second source contact; The shared drain contact is connected to one doped region of the first conductivity type and one doped region of the second conductivity type; the first source contact is connected to another doped region of the first conductivity type; and the second source contact is connected to another doped region of the second conductivity type.

8. The device according to claim 1, characterized in that, The height of the first gate structure in the third direction is greater than or equal to the height of the first conductivity type substrate and the second conductivity type substrate in the third direction.

9. A method for fabricating a NOR gate device, characterized in that, The method includes: Provide a base; A substrate is epitaxially grown on the substrate; The substrate is divided into a first substrate and a second substrate by etching to form trenches that penetrate the substrate; The first substrate is implanted with ions of a first conductivity type to form a substrate of the first conductivity type; the second substrate is implanted with ions of a second conductivity type to form a substrate of the second conductivity type. A first gate structure is fabricated within the trench; A second gate structure is fabricated above the first gate structure, the first conductivity type substrate, and the second conductivity type substrate; the second gate structure and the first gate structure are arranged along a third direction; the third direction is perpendicular to the plane containing the first conductivity type substrate, the first gate structure, and the second conductivity type substrate; Ion implantation of a second conductivity type is performed at both ends of the side where the first conductivity type substrate contacts the first gate structure to form a second conductivity type doped region; ion implantation of a first conductivity type is performed at both ends of the side where the second conductivity type substrate contacts the first gate structure to form a first conductivity type doped region; the first gate structure and the second gate structure are in contact with the undoped regions of the first conductivity type substrate and the second conductivity type substrate.

10. The method according to claim 9, characterized in that, The step of performing ion implantation of the first conductivity type at both ends on the side where the second conductivity type substrate contacts the first gate structure to form a first conductivity type doped region includes: Ion implantation of the first conductivity type is performed at both ends of the side where the second conductivity type substrate contacts the first gate structure to form a first lightly doped region; In the first lightly doped region, ions of the first conductivity type are implanted again on the side near the edge of the substrate of the second conductivity type to form a first highly doped region; the doping concentration and doping depth of the first highly doped region are both greater than those of the first lightly doped region.

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