Self-heating effect modeling and parameter extraction method

Abstract

The present invention provides a self-heating effect modeling and parameter extraction method, comprising the following steps: designing a self-heating effect measurement structure; performing an AC impedance test on the gate resistance of a device; dynamically scanning the device power and measuring the change in the gate resistance of the device; drawing a temperature-power curve and extracting the device thermal resistance from it. By introducing AC impedance measurement, the present invention only requires two additional gate resistance measurement ports, reducing the demand for device measurement ports, and at the same time, the bias of the gate will not cause the uneven potential distribution to cause the self-heating effect characterization of the device to be offset.

Description

Technical Field

[0001] The invention relates to the field of microelectronic technology, and in particular to a self-heating effect modeling and parameter extraction method. Background Art

[0002] The self-heating effect is an important device characteristic that affects the performance of current integrated circuits. Due to the poor thermal conductivity of the SOI process, the device can experience a dynamic change mechanism in which the channel temperature affects the working state of the device. The test method based on the Kelvin structure mainly adopted in the existing technology requires a four-port measurement of the gate resistance. Figure 1 The figure shows a gate resistance test model based on Kelvin structure in the prior art. The problem of this method is that the test accuracy is low and the measurement structure is complicated. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a self-heating effect modeling and parameter extraction method with high test accuracy and simple measurement structure.

[0004] In order to solve the above problems, the present invention provides a self-heating effect modeling and parameter extraction method, comprising the following steps: designing a self-heating effect measurement structure; performing an AC impedance test on the device gate resistance; dynamically scanning the device power and measuring the change of the device gate resistance at the same time; drawing a temperature-power curve and extracting the device thermal resistance therefrom.

[0005] The present invention introduces AC impedance measurement, which only requires two additional gate resistance measurement ports, reducing the demand for device measurement ports. At the same time, the bias of the gate will not cause the uneven distribution of potential to cause the self-heating effect of the device to be offset. Because the test of the gate resistance requires the formation of current at both ends of the device gate, the IR loss generated by the current flowing through the device gate can produce a voltage change on the gate, which causes the vertical voltage of the device channel to be unevenly distributed along the channel width. In the high electric field area, the vertical electric field of the device gate is relatively high, resulting in a relatively large current density, which can cause the gradient of the device's heat and dissipation changes in the channel, causing measurement errors. At the same time, this method also requires the use of four-port test conditions on the gate, and the additional three ports of the accessory device require seven ports for testing, which increases the test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Attached Figure 1 The figure shows a gate resistance test model based on Kelvin structure in the prior art.

[0007] Attached Figure 2 Shown is a gate resistance test method model based on AC impedance according to a specific embodiment of the present invention.

[0008] Attached Figure 3 The figure shows the comparison results of the channel power and the temperature rise of the device under different thermal resistance extraction methods according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0009] The specific implementation of the self-heating effect modeling and parameter extraction method provided by the present invention is described in detail below with reference to the accompanying drawings.

[0010] The following is a specific implementation of a self-heating effect modeling and parameter extraction method described in the present invention, which includes the following steps: Step S11, designing a self-heating effect measurement structure; Step S12, performing an AC impedance test on the device gate resistance; Step S13, dynamically scanning the device power and measuring the change in the device gate resistance at the same time; Step S14, drawing a temperature-power curve and extracting the device thermal resistance therefrom.

[0011] Referring to step S11, a related self-heating effect measurement structure is designed, and the resistance at both ends of the device gate is led out as a measurement port, which is port A and port B respectively, and the straight-line distance between the led-out ports and the device active area is controlled to be a constant value on different devices. The drain, source and substrate of the device are led out as ports D, S and B respectively.

[0012] Referring to step S12, the AC impedance test is performed on the gate resistance of the device, and the ThermalChuck ambient temperature is controlled at the same time to obtain the AC impedance values ​​of the gate resistance under different temperature environments. The applied AC impedance test condition is a DC bias condition of 0V, and the AC bias condition is a low-frequency small signal. In this process, the mapping relationship between the AC impedance parameters and the ambient temperature can be obtained, that is, R=f(T), where R is the AC impedance of the device gate resistance and T is the ambient temperature.

[0013] Referring to step S13, the device power is dynamically scanned while measuring the change in the gate resistance of the device. The gate ports A and B of the device still maintain the excitation conditions in step 2, that is, the DC bias remains at 0V and the AC remains at an AC small signal to measure the AC impedance of the device.

[0014] Attached Figure 2The model of the gate resistance test method based on AC impedance of this specific implementation method is shown. Taking NMOS as an example, the DC bias condition of the source S and substrate B of the device is set to -Vdd, so that Vgs = Vdd, Vbs = 0V, and the DC bias condition of the drain D of the device is set to -Vdd / 2~Vdd, so that Vds = Vdd / 2~Vdd scan changes. Wherein, for each DC bias change condition during the scanning process, the gate resistance of the device performs an impedance test. During the above change process, the drain-source voltage of the device is not limited to a fixed value. Here, only a typical measurement method is taken as an example. The key step is that the DC bias condition of the gate is always 0V to avoid affecting the vertical voltage distribution of the channel of the device. The following functional relationship can be obtained through the above test, R = g(P, T), where R is the AC impedance of the gate resistance of the device, P is the channel power of the device, which can be obtained by P = Ids*Vds, and T is the ambient temperature of the device.

[0015] Referring to step S14, a temperature-power curve is drawn and the device thermal resistance is extracted from the curve. Figure 3 The figure shows the comparison results of the channel power and device temperature rise of the device under different thermal resistance extraction methods. By scanning the channel power, it is found that the device temperature rise can be significantly reduced under low power conditions. This point is that the direct parameter mapping used in the improved thermal resistance method extraction will seriously underestimate the self-heating effect of the device. In this specific implementation, by adopting the power scanning state, the influence of the device leads on the measurement results under low device power conditions can be reduced. The two comparison results of the thermal resistance method in the figure show that the results of single-point measurement and this method can produce significant differences.

[0016] Therefore, the thermal resistance can be extracted by the following extraction formula,

[0017]

[0018] Where R is the AC impedance of the device gate, T is the device ambient temperature, ΔT0 is the temperature difference between the device gate temperature and the device channel temperature, P is the power of the device, and tanθ is the slope value of the device in the above TP curve. Because the above ΔT0 can be ignored in the differential, this method can obtain higher thermal resistance value extraction accuracy.

[0019] The above technical solution introduces AC impedance measurement, which only requires two additional gate resistance measurement ports, reducing the demand for device measurement ports. At the same time, the gate bias will not have uneven potential distribution, which will cause the self-heating effect of the device to be offset. Because the test of the gate resistance requires the formation of current at both ends of the device gate, the IR loss generated by the current flowing through the device gate can produce voltage changes on the gate, which causes the vertical voltage of the device channel to be unevenly distributed along the channel width. In the high electric field region, the vertical electric field of the device gate is high, resulting in a relatively large current density. At this time, the heating and dissipation changes of the device may change in the gradient within the channel, causing measurement errors. At the same time, this method also requires the use of four-port test conditions on the gate, and the additional three ports of the accessory device require seven ports for testing, which increases the test cost.

[0020] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A self-heating effect modeling and parameter extraction method, characterized in that: The steps include: Design a self-heating effect measurement structure, design a related self-heating effect measurement structure, lead out the resistance at both ends of the device gate as measurement ports, namely port A and port B, and the straight-line distance between the lead-out ports and the device active area is controlled to be a constant value on different devices, and lead out the drain, source and substrate of the device, namely ports D, S and B respectively; Performing an AC impedance test on the gate resistance of the device, specifically, performing an AC impedance test on the gate resistance of the device, and controlling the ambient temperature of the Thermal Chuck at the same time, obtaining the AC impedance values ​​of the gate resistance under different temperature environments, the applied AC impedance test condition is a 0V DC bias condition, and the AC bias condition is a low-frequency small signal. In this process, the mapping relationship between the AC impedance parameter and the ambient temperature can be obtained, that is, R=f(T), where R is the AC impedance of the gate resistance of the device, and T is the ambient temperature; Dynamically scan the device power and measure the change of the device's gate resistance at the same time; Plot the temperature-power curve and extract the device thermal resistance from it.

2. The method according to claim 1, characterized in that: The step of dynamically scanning the device power further comprises: At the same time, the gate resistance change of the device is measured. The gate ports A and B of the device still maintain the excitation conditions in the steps of the AC impedance test, that is, the DC bias is maintained at 0V, and the AC maintains an AC small signal to measure the AC impedance of the device.

3. The method according to claim 1, characterized in that The tangent of the slope angle of the temperature-power curve is the thermal resistance.

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