Instruction execution unit, processing unit, and related apparatus and methods

Abstract

Embodiments of the present application provide an instruction execution unit, a processing unit and related devices and methods, which are suitable for various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set) or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips and the like. The instruction execution unit comprises: an acquisition subunit configured to acquire a pipeline flush request for the instruction execution unit when a speculation failure occurs; and a flush subunit configured to respond to the pipeline flush request, flush the pipeline of the instruction execution unit according to an execution delay of the instruction execution unit and an architecture by a first flush mode and / or a second flush mode, wherein the first flush mode clears speculative instructions on an error path before the instructions are executed, and the second flush mode makes the speculative instructions on the error path have no execution effect. The present application can improve the efficiency of pipeline flushing.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an instruction execution unit, a processing unit, and related devices and methods. Background Technology

[0002] In the design of high-performance processors, the concept of speculative execution is introduced to improve processor performance. Through speculative execution, the processor can predict program flow and branch directions, and execute instructions within the corresponding program flow based on the prediction results. When program flow prediction or branch prediction errors occur, a speculative failure occurs. In this case, the processor may contain instructions on the correct path that need to be executed, or instructions on the incorrect path that do not need to be executed. When a speculative failure occurs, the processor needs to perform a pipeline flushing operation to preserve instructions on the correct path while clearing instructions on the incorrect path, ensuring the correctness of the overall execution behavior.

[0003] Currently, for out-of-order processors, after a pipeline flush request is generated, it is necessary to wait for all instructions in the processor to be executed before speculative instructions located on the wrong path can be identified. This prevents speculative instructions on the wrong path from having any effect, while allowing speculative instructions on the correct path to have an effect, thus completing the pipeline flush.

[0004] However, waiting for all instructions in the processor to complete before preventing speculative instructions on the error path from executing takes a long time, resulting in low pipeline flushing efficiency. Summary of the Invention

[0005] In view of this, embodiments of this application provide an instruction execution unit, a processing unit, and related apparatus and methods to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, an instruction execution unit is provided, comprising: an acquisition subunit, configured to acquire a pipeline flushing request for the instruction execution unit when a speculative failure occurs; and a flushing subunit, configured to, in response to the pipeline flushing request, perform pipeline flushing on the instruction execution unit according to the execution delay and architecture of the instruction execution unit, through a first flushing mode and / or a second flushing mode, wherein the first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having an execution effect.

[0007] According to a second aspect of the embodiments of this application, a processing unit is provided, comprising: an instruction fetching unit for fetching an instruction to be executed; an instruction decoding unit for decoding the instruction to be executed; an instruction sending unit for sending the decoded instruction to be executed to an instruction execution unit; and at least one instruction execution unit as described in the first aspect above.

[0008] According to a third aspect of the embodiments of this application, a computing device is provided, comprising: a processing unit as described in the second aspect above; and a memory coupled to the processing unit for storing the instructions to be executed.

[0009] According to a fourth aspect of the embodiments of this application, a pipeline flushing method is provided, comprising: when a speculative failure occurs, obtaining a pipeline flushing request for an instruction execution unit; in response to the pipeline flushing request, performing pipeline flushing on the instruction execution unit through a first flushing mode and / or a second flushing mode according to the execution delay and architecture of the instruction execution unit, wherein the first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having an execution effect.

[0010] According to the pipeline flushing scheme provided in the embodiments of this application, when a speculative failure occurs, the acquisition subunit obtains a pipeline flushing request. The flushing subunit responds to the pipeline flushing request and, based on the execution latency and architecture of the instruction execution unit, performs pipeline flushing on the instruction execution unit through a first flushing mode and / or a second flushing mode. Since the first flushing mode clears speculative instructions on the error path before the instruction is executed, the pipeline flushing speed is faster, but it is only applicable to instruction execution units of certain architecture types. The second flushing mode prevents speculative instructions on the error path from having any execution effect and is applicable to instruction execution units of various architecture types. The flushing subunit can perform pipeline flushing on the instruction execution unit through the first flushing mode and / or the second flushing mode according to the execution latency and architecture of the instruction execution unit. Based on the ability to perform pipeline flushing on instruction execution units of different architectures, the pipeline flushing speed can be improved, thereby improving pipeline flushing efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 This is a schematic diagram of a computing device used in one embodiment of this application;

[0013] Figure 2 This is a schematic diagram of a processing unit according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of an instruction execution unit according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of an instruction sequence according to an embodiment of this application;

[0016] Figure 5 This is a flowchart of a production line flushing method according to an embodiment of this application. Detailed Implementation

[0017] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0018] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0019] Speculative execution: Speculative execution is an optimization technique. Processors that use speculative execution can predict program flow and branch direction based on available information. Based on the prediction results, they can use idle time to execute subsequent instructions in the program flow in advance. The instructions executed in advance may or may not be used later.

[0020] Correct path: The path the program flow will take when a speculation failure occurs. Speculation instructions on the correct path need to produce an effect, and these instructions are older than the speculation failure instructions that led to subsequent speculation failures.

[0021] Error path: A path that the program flow will not reach when a speculation failure occurs. Speculation instructions located on error paths do not need to have any effect; they are updates relative to the speculation failure instructions that led to subsequent speculation failures.

[0022] Speculation failure order: A speculation order that causes speculation to fail. Speculation orders newer than the speculation failure order do not need to complete their execution effect, while speculation orders older than the speculation failure order do need to complete their execution effect.

[0023] Pipeline flushing: When a speculation failure occurs, the processor clears the internal speculation instructions located on the wrong path.

[0024] computing devices

[0025] Figure 1 A schematic block diagram of a computing device 10 is shown. The computing device 10 can be built based on various types of processing units and driven by any operating system such as Windows, UNIX, or Linux. Furthermore, the computing device 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0026] like Figure 1 As shown, the computing device 10 may include one or more processing units 12 and a memory 14. The memory 14 in the computing device 10 may serve as main memory (or simply main memory or RAM) for storing instruction information and / or data information represented by data signals. For example, the memory 14 may store data provided by the processing unit 12 (e.g., budget results) and may also be used to realize data exchange between the processing unit 12 and the external storage device 16 (or auxiliary memory or external memory).

[0027] In some cases, the processing unit 12 needs to access the memory 14 via the bus 11 to retrieve or modify data in the memory 14. Since the access speed of the memory 14 is relatively slow, to alleviate the speed difference between the processing unit 12 and the memory 14, the computing device 10 also includes a cache memory 18 communicatively connected to the bus 11. The cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly accessed. The cache memory 18 can be implemented using a storage device such as Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a Level 1 cache (L1Cache), a Level 2 cache (L2Cache), and a Level 3 cache (L3Cache). The cache memory 18 can also be a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the Level 1 cache, or both the Level 1 cache and the Level 2 cache) can be integrated inside the processing unit 12 or integrated with the processing unit 12 on the same on-chip system.

[0028] Based on this, the processing unit 12 may include an instruction execution unit 121 and a memory management unit 122, among other components. When executing instructions that require memory modification, the instruction execution unit 121 initiates a write access request, specifying the data to be written into memory and its corresponding physical address. The memory management unit 122 translates the virtual addresses specified by these instructions into the physical addresses mapped to those virtual addresses. The physical address specified in the write access request may be consistent with the physical address specified in the corresponding instruction.

[0029] Information exchange between memory 14 and cache memory 18 can be organized according to data blocks. In some embodiments, cache memory 18 and memory 14 can be divided into data blocks with the same spatial size. A data block can serve as the smallest unit of data exchange between cache memory 18 and memory 14 (including one or more data of a preset length). For the sake of brevity and clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses. Each data block in memory 14 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses and / or memory block addresses may include physical address tags used to locate data blocks.

[0030] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 14; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 14, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 14. When processing unit 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If the content to be accessed is already stored in cache memory 18, cache memory 18 is hit, and processing unit 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed is not stored in cache memory 18, cache memory 18 and processing unit 12 need to access memory 14 via bus 11 to find the corresponding information in memory 14. Because the access speed of cache memory 18 is very fast, the efficiency of processing unit 12 can be significantly improved when cache memory 18 is hit, thereby improving the performance and efficiency of the entire computing device 10.

[0031] In addition, the computing device 10 may also include a storage device 16, a display device, an audio device, a mouse / keyboard, and other input / output devices. The storage device 16 may be a hard disk, optical disk, or flash memory, etc., coupled to the bus 11 via a corresponding interface, for storing and retrieving information. The display device may be coupled to the bus 11 via a corresponding graphics card, and is used to display information according to the display signals provided by the bus 11.

[0032] The computing device 10 may also include a communication device 17, enabling the computing device 10 to communicate with networks or other devices in various ways. The communication device 17 may include one or more communication modules, including wireless communication modules adapted to specific wireless communication protocols. For example, the communication device 17 may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication device 17 may include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols. The communication device 17 may also include communication modules employing other protocols, such as a Bluetooth module, or other custom-type communication modules. The communication device 17 may also be a port for serial data transmission.

[0033] It should be noted that the structure of different computing devices 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computing devices are equipped with an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processing unit 12 or independent of the processing unit 12.

[0034] Processing unit

[0035] Figure 2 This is a schematic block diagram of a processing unit 12 according to one embodiment of this application. Figure 2As shown, each processing unit 12 may include one or more processor cores 120 for processing instructions. The processing and execution of instructions can be controlled by a user (e.g., through an application program) and / or the system platform. Each processor core 120 can be used to process a specific instruction set, which can support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW) based computation. Specifically, processor core 120 is suitable for processing the RISC-V instruction set. Different processor cores 120 can each process different or the same instruction sets. Processor core 120 may also include other processing modules, such as a Digital Signal Processor (DSP). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a positive integer.

[0036] Figure 1 The cache memory 18 shown can be wholly or partially integrated into the processing unit 12. Depending on the architecture, the cache memory 18 can be a single or multi-level internal cache memory located within and / or outside each processor core 120 (e.g., ...). Figure 2 The three-level cache memory L1 to L3 are shown. Figure 2 The cache memory (referred to as 18 in the original text) may include instruction-oriented cache and instruction cache, as well as data cache. The components in processing unit 12 may share at least a portion of the cache memory; for example, processor cores 1 to m may share the third-level cache L3. Processing unit 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processing unit 12.

[0037] like Figure 2 As shown, the processing unit 12 may include a register file 126, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types, such as integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in the register file 126 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of the processing unit 12.

[0038] Processing unit 12 may include a memory management unit (MMU) 122 for translating virtual addresses to physical addresses. The memory management unit 122 caches a portion of the entries in the page table and can also retrieve uncached entries from memory. Each processor core 120 may have one or more memory management units 122. The memory management units 122 in different processor cores 120 can be synchronized with those in other processing units or processor cores, allowing each processing unit or processor core to share a unified virtual memory system.

[0039] The processing unit 12 is used to execute the instruction sequence (i.e., the program). The process of the processing unit 12 executing each instruction includes: fetching the instruction from the memory where the instructions are stored, decoding the fetched instruction, executing the decoded instruction, and keeping the instruction execution result, etc., and so on, until all the instructions in the instruction sequence are executed or a halt instruction is encountered.

[0040] To implement the above process, the processing unit 12 may include an instruction fetch unit 124, an instruction decoding unit 125, an instruction dispatch unit (not shown), an instruction execution unit 121, and a retirement unit 123, etc.

[0041] The instruction fetch unit 124 serves as the startup engine for the processing unit 12, used to move instructions from memory 14 to the instruction register (which may be...). Figure 2 The instruction is stored in one of the registers in the register file 126 shown, and the next fetch address is received or calculated according to the fetch algorithm, which can be an incrementing or decrementing address based on the instruction length.

[0042] After the instruction is fetched, the processing unit 12 enters the instruction decoding stage. The instruction decoding unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. The operand acquisition information may include pointers to immediate values, registers, or other software / hardware that can provide source operands.

[0043] The instruction dispatch unit, typically located within the high-performance processing unit 12, lies between the instruction decoding unit 125 and the instruction execution unit 121. It is used for instruction scheduling and control, efficiently allocating instructions to different instruction execution units 121, thus enabling parallel operation of multiple instructions. After an instruction is fetched, decoded, and scheduled to the corresponding instruction execution unit 121, the unit begins executing the instruction, performing the operation specified by the instruction, and thus fulfilling the corresponding function.

[0044] The retirement unit 123 (or instruction retirement unit or instruction write-back unit) is mainly used to write the execution results generated by the instruction execution unit 121 back to the corresponding storage location (e.g., a register inside the processing unit 12) so that subsequent instructions can quickly obtain the corresponding execution results from that storage location.

[0045] For different types of instructions, different instruction execution units 121 can be set up in the processing unit 12 accordingly. The instruction execution unit 121 can be an arithmetic unit (e.g., including an arithmetic logic unit, an integer processing unit, a vector arithmetic unit, etc., used to perform operations based on operands and output the operation results), a memory execution unit (e.g., used to access memory according to instructions to read data in memory or write specified data to memory, etc.), and a coprocessor, etc. In the processing unit 12, each instruction execution unit 121 can run in parallel and output the corresponding execution results.

[0046] When executing a certain type of instruction (such as a memory access instruction), the instruction execution unit 121 needs to access memory 14 to obtain information stored in memory 14 or to provide data that needs to be written to memory 14. It should be noted that the instruction execution unit 121 used to execute memory access instructions can also be simply referred to as a memory execution unit, which can be a load store unit (LSU) and / or other units used for memory access.

[0047] After the memory access instruction is fetched by the instruction fetch unit 124, the instruction decoding unit 125 can decode the memory access instruction, allowing the source operand of the memory access instruction to be fetched. The decoded memory access instruction is then provided to the corresponding instruction execution unit 121, which can perform corresponding operations on the source operand of the memory access instruction (e.g., the arithmetic logic unit performs operations on the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests based on the address information, such as address translation requests, write access requests, etc.

[0048] The source operand of a memory access instruction typically includes an address operand. The instruction execution unit 121 performs operations on this address operand to obtain the virtual or physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 121 is enabled, the corresponding instruction execution unit 121 initiates an address translation request based on the virtual address corresponding to the memory access instruction. This address translation request includes the virtual address corresponding to the address operand of the memory access instruction. The memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address based on the entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and / or memory 14 according to the translated physical address.

[0049] Depending on their function, memory access instructions can include load instructions and store instructions. The execution of a load instruction typically does not require modification of information in memory 14 or cache memory 18; the instruction execution unit 121 only needs to read data stored in memory 14, cache memory 18, or external storage devices based on the address operand of the load instruction. Unlike load instructions, the source operand of a store instruction includes not only address operands but also data information. The execution of a store instruction typically requires modification of information in memory 14 and / or cache memory 18. The data information in a store instruction can point to data to be written. The source of this written data can be the execution result of an arithmetic instruction, load instruction, or other instructions; data provided by registers or other storage units in the processing unit 12; or immediate values.

[0050] Processing unit 12 can predict program flow and branch direction through speculative execution, and execute subsequent instructions in the program flow in advance during idle time based on the prediction results. In the event of a speculative failure, processing unit 12 needs to perform pipeline flushing to clear speculative instructions located on incorrect paths and retain speculative instructions on correct paths to ensure the correctness of the overall execution behavior. When a speculative failure occurs, instruction execution unit 121 within the pipeline flushing range needs to perform pipeline flushing to clear speculative instructions located on incorrect paths and complete the execution effect of speculative instructions on correct paths.

[0051] The processing unit 12 may also include a retirement unit 123. When a speculation failure occurs, the retirement unit 123 can determine the pipeline flushing range based on the cause of the speculation failure, and then send a pipeline flushing request to the instruction execution unit 121 located within the pipeline flushing range. This causes the instruction execution unit 121 located within the pipeline flushing range to perform pipeline flushing, clearing speculative instructions on the wrong path and retaining speculative instructions on the correct path, thus ensuring the correctness of the overall execution behavior of the processing unit 12.

[0052] This application focuses on the pipeline flushing process of the instruction execution unit 121, and the pipeline flushing process will be described in detail later.

[0053] Instruction Execution Unit

[0054] When a pipeline failure occurs, the instruction execution unit within the pipeline flushing range needs to undergo pipeline flushing. During pipeline flushing, the preceding stage cannot send new instructions to the instruction execution unit, resulting in a large number of cavitation bubbles in the processing unit's execution, thus affecting the performance of the processing unit. Since pipeline flushing cannot be eliminated, reducing the time required for each pipeline flush becomes a feasible solution to improve the performance of the processing unit.

[0055] Currently, when the instruction execution unit performs pipeline flushing, it needs to determine the relative age of each instruction to the failed speculative instruction based on the pipeline depth. Then, based on this age relationship, it identifies speculative instructions on the wrong path and those on the correct path, clearing the speculative instructions on the wrong path and ensuring that the speculative instructions on the correct path complete their execution. However, determining the age relationship based on pipeline depth is only applicable to certain types of processing units. For example, in-order processing units can determine the age relationship based on pipeline depth, while out-of-order processing units need to wait for all instructions in the processor to complete their execution before speculative instructions on the wrong path can be prevented from having an effect. Therefore, pipeline flushing for out-of-order processing units is less efficient.

[0056] This application embodiment was developed to address the problem of low pipeline flushing efficiency in the out-of-order processing unit, and it is mainly implemented through the instruction execution unit 121. The internal structure of the instruction execution unit 121 and the implementation process of this application embodiment are discussed in detail below.

[0057] Figure 3 This is a schematic diagram of the internal structure of an instruction execution unit according to an embodiment of this application. Figure 3 As shown, the instruction execution unit 121 includes an acquisition subunit 1211 and a flushing subunit 1212. In the event of a speculation failure, the acquisition subunit 1211 can acquire a pipeline flushing request for its respective instruction execution unit 121. The flushing subunit 1212, in response to the pipeline flushing request acquired by the acquisition subunit 1211, can perform pipeline flushing on the instruction execution unit 121 through a first flushing mode and / or a second flushing mode, based on the execution delay and architecture of the instruction execution unit 121. Specifically, the first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having any execution effect.

[0058] When a speculation failure occurs, the retirement unit 123 in the processing unit 12 determines the pipeline flushing range based on the cause of the speculation failure and sends a pipeline flushing request to the instruction execution unit 121 located within the pipeline flushing range. The instruction execution unit 121 located within the pipeline flushing range can receive the pipeline flushing request.

[0059] The first flush mode clears speculative instructions on the erroneous path before the instruction is executed, so it does not need to wait for all instructions inside the instruction execution unit 121 to be executed before pipeline flushing can be performed, thereby shortening the time required for each pipeline flush. However, the first flush mode needs to determine the relationship between the old and new instructions before the instruction is executed. Therefore, the first flush mode has strict requirements on the architecture of the instruction execution unit 121. For example, the instruction execution unit 121 that processes instructions in order can perform pipeline flushing through the first flush mode, while the instruction execution unit 121 that processes instructions out of order cannot complete pipeline flushing simply through the first flush mode.

[0060] The second flushing mode prevents speculative instructions on the wrong path from having any effect. After all instructions in the instruction execution unit 121 have been executed, the relationship between old and new instructions can be determined based on the execution results. This makes it applicable to instruction execution units 121 of various architectures. However, the second flushing mode requires determining the relationship between old and new instructions after the instructions have been executed. If there are long-delay instructions in the instruction execution unit 121, it will take a long time for the instruction execution unit 121 to execute the long-delay instructions. It will take a long time to complete the pipeline flushing. During the pipeline flushing process, the preceding stage cannot send new instructions to the instruction execution unit 121, which causes the processing unit 12 to generate execution cavitation and affects the performance of the processing unit 12.

[0061] In this embodiment, when a speculative failure occurs, the acquisition subunit 1211 acquires a pipeline flushing request. The flushing subunit 1212 responds to the pipeline flushing request and, based on the execution delay and architecture of the instruction execution unit 121, performs pipeline flushing on the instruction execution unit 121 using a first flushing mode and / or a second flushing mode. Since the first flushing mode clears speculative instructions on the error path before the instruction is executed, the pipeline flushing speed is faster, but it is only applicable to instruction execution units of certain architecture types. The second flushing mode, however, prevents speculative instructions on the error path from having any execution effect and is applicable to instruction execution units of various architecture types. Therefore, the flushing subunit 1212 can perform pipeline flushing on the instruction execution unit 121 using the first flushing mode and / or the second flushing mode based on the execution delay and architecture of the instruction execution unit 121. This allows for pipeline flushing of instruction execution units with different architectures, thereby increasing the pipeline flushing speed and thus improving pipeline flushing efficiency.

[0062] In one possible implementation, when pipeline flushing the instruction execution unit 121 through the first flushing mode, the failed speculative instruction that caused the speculative failure is first identified. Then, based on the pipeline depth of the instruction execution unit 121, the relationship between the old and new speculative instructions and the failed speculative instructions in the instruction execution unit 121 is determined. Based on this relationship, the first speculative instruction located on the wrong path and the second speculative instruction located on the correct path in the instruction execution unit 121 can be identified. Then, the first speculative instruction is cleared, and the second speculative instruction is allowed to continue the instruction.

[0063] When the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the first flushing mode, the flushing subunit 121 can identify the speculative failure instruction that leads to speculative failure. Speculative failure occurs when there is a program flow prediction error or branch prediction error. Program flow prediction errors include interruptions, exceptions, etc. When the instruction execution unit 12 experiences an interruption or exception, if the currently executed instruction is a speculative instruction, it is identified as a speculative failure instruction; if the currently executed instruction is not a speculative instruction, the next speculative instruction to be executed is identified as a speculative failure instruction. When the instruction execution unit 12 experiences a branch prediction error, the speculative instruction at the program flow branch position is identified as a speculative failure instruction.

[0064] Optionally, the relationship between the old and new speculative instructions within the instruction execution unit 121 can be determined based on the instruction ID. When an instruction is issued, an ID is assigned to it, and the instruction IDs increment or decrement according to the order of issuance, thus determining the relationship between the old and new instructions based on their IDs.

[0065] Figure 4 This is a schematic diagram of an instruction sequence (program flow) according to an embodiment of this application. Figure 4 As shown, instruction execution unit 121 is currently executing instruction A. Through speculative execution, it executes instructions B, C, D, and E in advance. Therefore, instruction B is speculative instruction 1, instruction C is speculative instruction 2, instruction D is speculative instruction 3, and instruction E is speculative instruction 4. If instruction execution unit 121 experiences an interruption or exception while executing instruction A, instruction B (speculative instruction 1) is determined to be a failed speculative instruction. If instruction execution unit 121 experiences an interruption or exception while executing instruction C, instruction C (speculative instruction 2) is determined to be a failed speculative instruction.

[0066] For the instruction execution unit 121 that processes instructions in sequence, after the flushing subunit 1212 determines the speculation failure instruction, it can determine the age relationship of each speculation instruction in the instruction execution unit 121 relative to the speculation failure instruction based on the pipeline depth of the instruction execution unit 121. Then, the speculation instruction that is newer than the speculation failure instruction is determined as the first speculation instruction located on the wrong path, and the speculation instruction that is older than the speculation failure instruction is determined as the second speculation instruction located on the correct path.

[0067] It should be noted that the first speculative order may include multiple orders, not just one. Similarly, the second speculative order may also include multiple orders, not just one.

[0068] like Figure 4 As shown, if instruction B (speculative instruction 1) is determined to be a failed speculation instruction, then speculative instructions 2 (instruction C), 3 (instruction D), and 4 (instruction E), which are updated relative to instruction B (speculative instruction 1), are determined to be the first speculative instructions. If instruction C (speculative instruction 2) is determined to be a failed speculation instruction, then speculative instructions 3 (instruction D) and 4 (instruction E), which are updated relative to instruction C (speculative instruction 2), are determined to be the first speculative instructions, and speculative instruction 1 (instruction B), which is older than instruction C (speculative instruction 2), is determined to be the second speculative instruction.

[0069] In this embodiment, for the instruction execution unit 121, which can determine the relationship between the new and old instructions based on the pipeline depth, the flushing subunit 1212, after determining the failed speculative instruction, determines the relationship between each speculative instruction in the instruction execution unit 121 and the failed speculative instruction based on the pipeline depth of the instruction execution unit 121. The speculative instruction newer than the failed speculative instruction is identified as the first speculative instruction, and the speculative instruction older than the failed speculative instruction is identified as the second speculative instruction. The first speculative instruction is then cleared, and the second speculative instruction continues to be executed, completing the pipeline flushing. Because the first speculative instruction is cleared before the instruction is executed, pipeline flushing can be completed without waiting for all instructions in the instruction execution unit 121 to be executed, thereby improving the efficiency of pipeline flushing.

[0070] In one possible implementation, when the instruction execution unit 121 is pipelined through the second flushing mode, after all instructions in the instruction execution unit 121 have been executed, the flushing subunit 1212 determines the third speculative instruction located on the wrong path and the fourth speculative instruction located on the correct path in the instruction execution unit 121 according to the relationship between the old and new instructions, thereby preventing the third speculative instruction from having an execution effect and making the fourth speculative instruction have an execution effect.

[0071] When the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the second flushing mode, the flushing subunit 1212 waits for all instructions in the instruction execution unit 121 to be executed, determines the old and new relationships of each instruction based on the execution results, and then identifies the third speculative instruction located on the wrong path and the fourth speculative instruction located on the correct path based on the old and new relationships of each instruction. Since the flushing subunit 1212 determines the old and new relationships of each instruction based on the execution results, it is applicable to instruction execution units of various architecture types, such as instruction execution units that process instructions in sequence and instruction execution units that process instructions out of sequence, and both can be pipelined using the second flushing mode.

[0072] It should be understood that in the out-of-order processing unit, the instruction execution unit 121 executes instructions out of order. After the instructions are executed, a write operation is performed to reorder the instructions. Therefore, the relationship between the old and new instructions can be determined after the instructions are executed. In the in-order processing unit, the instruction execution unit 121 executes instructions sequentially. The executed instructions are still arranged in order. Therefore, the relationship between the old and new instructions can also be determined after the instructions are executed.

[0073] When pipeline flushing the instruction execution unit 121 using the second flushing mode, both the third speculative instruction on the wrong path and the fourth speculative instruction on the correct path are executed. However, the third speculative instruction can be made to have no execution effect, while the fourth speculative instruction can have a speculative effect, to ensure the correctness of the overall execution behavior. Both the third and fourth speculative instructions will complete execution, but the result of the third speculative instruction will not be written back or produce other execution effects, while the fourth speculative instruction will normally be written back or produce other execution effects.

[0074] like Figure 4 As shown, instruction C (speculative instruction 2) is a branch instruction. The speculative execution prediction program flow will flow to the branch formed by instructions D (speculative instruction 3) and E (speculative instruction 4). If instruction C (speculative instruction 2) mispredicts the branch, i.e., instruction F should be executed after instruction C completes, but the speculative execution prediction will execute instruction D, then instructions C, D, and E are identified as the third speculative instruction on the incorrect path, while instruction B is identified as the fourth speculative instruction on the correct path. Instructions B, C, D, and E will all complete execution, but the execution result of instruction B is written back normally, while the execution results of instructions C, D, and E are not written back, allowing instruction B to produce an execution effect, while instructions C, D, and E do not produce an execution effect.

[0075] In this embodiment, for instruction execution units 121 of various architecture types, the flushing subunit 1212 can determine the relationship between old and new instructions after each instruction is executed within the instruction execution unit 121. This allows for the identification of a third speculative instruction on an incorrect path and a fourth speculative instruction on the correct path. Consequently, the third speculative instruction is prevented from executing, while the fourth speculative instruction is executed, thus completing the pipeline flushing. Identifying speculative instructions on the correct path and those on the incorrect path after instruction execution is applicable to both in-order and out-of-order processing units, ensuring the applicability of pipeline flushing.

[0076] In one possible implementation, when the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through a first flushing mode and / or a second flushing mode based on the execution delay and architecture of the instruction execution unit 121, if the average execution delay of the instruction execution unit 121 is greater than a preset delay threshold, or if the instruction execution unit 121 is a sequential processing architecture, the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the first flushing mode.

[0077] Since the first flushing mode can determine the speculative instructions on the wrong path and the speculative instructions on the correct path before the instructions are executed, the pipeline flushing can be completed without waiting for all the instructions in the instruction execution unit 121 to be executed, thus shortening the time required for pipeline flushing. For instruction execution unit 121 with a large execution delay, the performance of instruction execution unit 121 can be improved.

[0078] For the instruction execution unit 121 of the sequential processing architecture, the relationship between the new and old instructions can be determined according to the pipeline depth of the instruction execution unit 121. There is no need to design a complex circuit structure to determine the relationship between the new and old instructions. Thus, while ensuring the pipeline flushing speed, the design complexity of the processing unit 12 can be avoided, and the processing unit 12 can have a lower cost and size.

[0079] For example, the instruction execution units 121 included in the processing unit 12 include vector processing units. The vector processing units have a relatively large and fixed latency. The flushing subunit 1212 performs pipeline flushing through a first flushing mode. During pipeline flushing, the instructions in the pipeline are judged, and speculative instructions on erroneous paths are cleared.

[0080] It should be understood that the average execution latency of instruction execution unit 121 can be determined based on the execution latency of the instructions executed by instruction execution unit 121. If the execution latency of a large proportion of the instructions executed by instruction execution unit 121 is greater than a latency threshold, then the average execution latency of instruction execution unit 121 is determined to be greater than the latency threshold. For example, if 90% of the instructions executed by instruction execution unit 121 have an execution latency greater than the latency threshold, and 10% of the instructions have an execution latency less than the latency threshold, then the average execution latency of instruction execution unit 121 is determined to be greater than the latency threshold.

[0081] In this embodiment of the application, when the average execution delay of the instruction execution unit 121 is greater than the delay threshold, or when the instruction execution unit 121 is a sequential processing architecture, the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the first flushing mode. While ensuring the pipeline flushing speed, the design complexity of the processing unit 12 can be reduced, thereby ensuring that the processing unit 12 has a lower cost and size.

[0082] In one possible implementation, when the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through a first flushing mode and / or a second flushing mode based on the execution delay and architecture of the instruction execution unit 121, if the average execution delay of the instruction execution unit 121 is less than or equal to a preset delay threshold, and the instruction execution unit 121 is an out-of-order processing architecture, the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the second flushing mode.

[0083] For the instruction execution unit 121 in the out-of-order processing architecture, if the execution latency of the instruction execution unit 121 is small, the pipeline flushing speed has little impact on the performance of the instruction execution unit 121. There is no need to design a complex circuit structure in order to improve the pipeline flushing speed. After each instruction in the instruction execution unit 121 is executed, the relationship between the old and new instructions is determined, so that speculative instructions on the wrong path do not produce an execution effect, while speculative executions on the correct path produce an execution effect, thus completing the pipeline flushing. This reduces the design complexity of the instruction execution unit 121 while ensuring its performance.

[0084] For example, the instruction execution units 121 included in the processing unit 12 include a shaping processing unit. The relative delay of the shaping processing unit is small and fixed. The flushing subunit 1212 performs pipeline flushing through the second flushing mode. After all instructions in the instruction execution unit 121 have been executed, the flushing subunit 1212 determines whether the speculative instruction is on the correct path, writes back the speculative instruction on the correct path to produce the execution effect, and clears the speculative instruction on the incorrect path.

[0085] In this embodiment of the application, for the out-of-order processing architecture instruction execution unit 121 with an average execution latency less than or equal to the latency threshold, the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through the second flushing mode. There is no need to design a circuit structure in the instruction execution unit 121 to determine the relationship between new and old instructions. While ensuring the pipeline flushing speed, the design complexity of the processing unit 12 can be reduced, thereby ensuring that the processing unit 12 has a lower cost and size.

[0086] It should be noted that when a speculation failure occurs, not only does the instruction execution unit 121 need to undergo pipeline flushing, but both the pre-stage and post-stage of the instruction execution unit 121 also need to undergo pipeline flushing. Moreover, there may be multiple instruction execution units 121 in the processing unit 12 that need to undergo pipeline flushing. During the pipeline flushing process of the processing unit 12, the pre-stage will not issue new instructions to the instruction execution unit 121. Therefore, simply improving the pipeline flushing efficiency of a certain instruction execution unit 121 may not improve the performance of the processing unit 12. Thus, when the execution latency of the instruction execution unit 121 is small, there is no need to design a complex circuit structure to perform pipeline flushing of the instruction execution unit 121 through the first flushing mode.

[0087] In one possible implementation, when the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 through a first flushing mode and / or a second flushing mode based on the execution delay and architecture of the instruction execution unit 121, if the execution delay of the instruction execution unit 121 dynamically changes around a delay threshold, the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 by combining the first flushing mode and the second flushing mode.

[0088] Specifically, for the N-stage pipeline included in the instruction execution unit 121, the pipeline stages after the checkpoint are flushed using a first flushing mode, and the pipeline stages before the checkpoint are flushed using a second flushing mode. Here, N is a positive integer greater than or equal to 3, the checkpoint is the M-th stage of the N-stage pipeline, and M is a positive integer greater than 1 and less than N, indicating that the instruction to be executed has passed through the checkpoint.

[0089] A checkpoint is set at one stage of the multi-stage pipeline included in the instruction execution unit 121. There is at least one pipeline stage before and after the checkpoint. When an instruction passes through the checkpoint, it can be determined whether the instruction needs to be executed. Non-speculsive instructions can pass through the checkpoint to the next pipeline stage without execution. Speculative instructions need to be executed first. Speculative instructions on the correct path can pass through the checkpoint, while speculative instructions on the wrong path cannot pass through the checkpoint. For each stage of the pipeline after the checkpoint, pipeline flushing is performed using a first flushing mode. For each stage of the pipeline before the checkpoint, pipeline flushing is performed using a second flushing mode.

[0090] For example, each instruction execution unit 121 included in the processing unit 12 includes a memory access unit. The memory access unit experiences uncertain execution delays when executing instructions. The flushing subunit 1212 performs pipeline flushing by combining a first flushing mode and a second flushing mode. Checkpoints are set in the instruction execution unit 121. An instruction is only allowed to pass through a checkpoint after it has been determined that the instruction is to be executed. During pipeline flushing, residual instructions are sequentially checked at checkpoints. If a instruction is determined to be speculative, it is canceled; otherwise, it passes through the checkpoint normally. Flushing is completed after all instructions have passed the checkpoint checks.

[0091] In this embodiment, checkpoints are set in the multi-stage pipeline included in the instruction execution unit 121. Instructions pass through the checkpoints to determine whether they need to be executed. Instructions that need to be executed can pass through the checkpoints, while instructions that do not need to be executed cannot pass through the checkpoints. Therefore, the pipeline can be continuously flushed without waiting for all instructions in the instruction execution unit 121 to be executed before determining speculative instructions on the correct path and speculative instructions on the wrong path, thereby improving the efficiency of pipeline flushing.

[0092] In one possible implementation, when the flushing subunit 1212 performs pipeline flushing using a combination of a first flushing mode and a second flushing mode, the speculative instruction located at the checkpoint when the acquisition subunit 1211 receives the pipeline flushing request can be identified as a failed speculative instruction. As speculative instructions in each stage of the pipeline before the checkpoint pass through the checkpoint sequentially, the flushing subunit 1212 determines the relationship between the older and younger speculative instructions passing through the checkpoint and the failed speculative instructions. If the speculative instruction passing through the checkpoint is older than the failed speculative instruction, then the speculative instruction passing through the checkpoint is executed; otherwise, the speculative instruction passing through the checkpoint is not executed.

[0093] In this embodiment, after a failed speculative instruction is identified, when a speculative instruction in each stage of the pipeline before the checkpoint passes the checkpoint, the flushing subunit 1212 determines the relationship between the old and new speculative instructions that pass the checkpoint and the failed speculative instructions, and determines the speculative instructions on the wrong path and the speculative instructions on the correct path. This ensures that the speculative instructions on the wrong path do not have an execution effect, while the speculative instructions on the correct path have an execution effect, thereby improving the flushing speed of the pipeline while ensuring the flushing effect of the pipeline.

[0094] It should be understood that the flushing subunit 1212 performs pipeline flushing on the instruction execution unit 121 by combining the first flushing mode and the second flushing mode. This mainly targets the instruction execution unit 121 that executes instructions out of order. Some or all of the instruction execution units 121 in the out-of-order processing unit 12 can execute instructions out of order.

[0095] Assembly line flushing method

[0096] Figure 5 This is a flowchart of a pipeline flushing method according to an embodiment of this application. This pipeline flushing method can be executed by the instruction execution unit 121 in the above embodiment. Figure 5 As shown, the flushing method for the production line includes the following steps:

[0097] Step 501: When a speculation failure occurs, obtain a pipeline flushing request for the instruction execution unit;

[0098] Step 502: In response to the pipeline flushing request, the instruction execution unit is pipeline flushed according to the execution delay and architecture of the instruction execution unit through a first flushing mode and / or a second flushing mode. The first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having any execution effect.

[0099] In this embodiment, when a speculative failure occurs, the instruction execution unit can be pipelined using a first flushing mode and / or a second flushing mode, based on the execution delay and architecture of the instruction execution unit. The first flushing mode can clear speculative instructions on the error path before the instruction is executed, resulting in a faster flushing speed. The second flushing mode can prevent speculative instructions on the error path from having any execution effect. By enabling pipeline flushing of instruction execution units with different architectures, the pipeline flushing speed can be increased, thereby improving pipeline flushing efficiency.

[0100] In one possible implementation, the first flushing mode includes: identifying the speculative failure instruction that caused the speculation failure; determining the relationship between each speculative instruction and the speculative failure instruction within the instruction execution unit based on the pipeline depth of the instruction execution unit; identifying the first speculative instruction on the wrong path and the second speculative instruction on the correct path within the instruction execution unit based on the relationship; clearing the first speculative instruction; and allowing the second speculative instruction to continue execution. The second flushing mode includes: after all instructions within the instruction execution unit have been executed, identifying the third speculative instruction on the wrong path and the fourth speculative instruction on the correct path within the instruction execution unit based on the relationship between the instructions; preventing the third speculative instruction from having any execution effect; and allowing the fourth speculative instruction to have an execution effect.

[0101] In one possible implementation, the instruction execution unit is pipelined through a first flushing mode and / or a second flushing mode, depending on the execution latency and architecture of the instruction execution unit. This includes: pipelined flushing of the instruction execution unit through the first flushing mode when the average execution latency of the instruction execution unit is greater than a preset latency threshold or when the instruction execution unit is a sequential processing architecture.

[0102] In one possible implementation, the instruction execution unit is pipelined using a first flushing mode and / or a second flushing mode, depending on the execution latency and architecture of the instruction execution unit. This includes: pipelined flushing of the instruction execution unit using the second flushing mode when the average execution latency of the instruction execution unit is less than or equal to a latency threshold and the instruction execution unit is an out-of-order processing architecture.

[0103] In one possible implementation, based on the execution delay and architecture of the instruction execution unit, pipeline flushing is performed on the instruction execution unit through a first flushing mode and / or a second flushing mode. This includes: when the execution delay of the instruction execution unit dynamically changes around a delay threshold, for the N-stage pipeline included in the instruction execution unit, pipeline flushing is performed on each stage of the pipeline after the checkpoint using the first flushing mode, and pipeline flushing is performed on each stage of the pipeline before the checkpoint using the second flushing mode, where N is a positive integer greater than or equal to 3, the checkpoint is the M-th stage of the N-stage pipeline, M is a positive integer greater than 1 and less than N, and the instruction to be executed is determined to pass through the checkpoint.

[0104] In one possible implementation, pipeline flushing is performed on each stage of the pipeline before the checkpoint using a second flushing mode, including: determining the speculative instruction at the checkpoint as a failed speculative instruction when the acquisition subunit receives the pipeline flushing request; when the speculative instructions in each stage of the pipeline before the checkpoint pass through the checkpoint sequentially, determining the relationship between the older and younger speculative instructions passing through the checkpoint and the failed speculative instructions; if the speculative instruction passing through the checkpoint is older than the failed speculative instruction, then the speculative instruction passing through the checkpoint is executed; if the speculative instruction passing through the checkpoint is newer than the failed speculative instruction, then the speculative instruction passing through the checkpoint is not executed.

[0105] It should be noted that the details of the pipeline flushing method have been described in detail in conjunction with the structural diagram in the instruction execution unit section of the above embodiment. For the specific process, please refer to the description in the aforementioned instruction execution unit embodiment, and it will not be repeated here.

[0106] Computer storage media

[0107] This application also provides a computer-readable storage medium storing instructions for causing a machine to perform the pipeline flushing method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0108] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this application.

[0109] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0110] Computer program products

[0111] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0112] The commercial value of the embodiments in this application

[0113] In addressing the adaptability issue of pipeline flushing, this application employs a dual-mode pipeline flushing acceleration mechanism. The first flushing mode directly flushes away all speculative instructions on erroneous paths in the instruction execution unit. The second flushing mode waits for all instructions in the instruction execution unit to complete execution before determining whether an instruction is on a correct or erroneous path, and then clears the execution results of speculative executions on erroneous paths. Depending on the characteristics of each instruction execution unit in the processing unit, the first flushing mode, the second flushing mode, or a combination of both can be selected for pipeline flushing. This allows for a balance between design complexity and pipeline flushing speed in the processing unit design, reducing performance loss during pipeline flushing and improving the overall performance of the processing unit.

[0114] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0115] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0116] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0117] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An instruction execution unit, comprising: A subunit is used to obtain a pipeline flushing request for the instruction execution unit when a speculation failure occurs. A flushing subunit is configured to respond to the pipeline flushing request and, based on the execution delay and architecture of the instruction execution unit, perform pipeline flushing on the instruction execution unit through a first flushing mode and / or a second flushing mode, wherein the first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having any execution effect. The flushing subunit, based on the execution latency and architecture of the instruction execution unit, performs pipeline flushing on the instruction execution unit through a first flushing mode and / or a second flushing mode, including: when the average execution latency of the instruction execution unit is greater than a preset latency threshold or the instruction execution unit is in-order processing architecture, performing pipeline flushing on the instruction execution unit through the first flushing mode; when the average execution latency of the instruction execution unit is less than or equal to the latency threshold, and the instruction execution unit is in out-of-order processing architecture, performing pipeline flushing on the instruction execution unit through the second flushing mode. The instruction execution unit performs pipeline flushing; when the execution delay of the instruction execution unit dynamically changes around the delay threshold, for the N-stage pipeline including the instruction execution unit, the pipelines after the checkpoint are flushed using the first flushing mode, and the pipelines before the checkpoint are flushed using the second flushing mode, where N is a positive integer greater than or equal to 3, the checkpoint is the M-th stage pipeline in the N-stage pipeline, M is a positive integer greater than 1 and less than N, and the instruction to be executed is determined to pass through the checkpoint.

2. The instruction execution unit according to claim 1, wherein, The first flushing mode includes: identifying the speculation failure instruction that caused the speculation failure; determining the relationship between each speculation instruction in the instruction execution unit and the speculation failure instruction based on the pipeline depth of the instruction execution unit; determining the first speculation instruction located on the wrong path and the second speculation instruction located on the correct path in the instruction execution unit based on the relationship; clearing the first speculation instruction and allowing the second speculation instruction to continue execution. The second flushing mode includes: after all instructions in the instruction execution unit have been executed, based on the relationship between the old and new instructions, determining the third speculative instruction located on the wrong path and the fourth speculative instruction located on the correct path in the instruction execution unit, so that the third speculative instruction does not produce an execution effect, and the fourth speculative instruction produces an execution effect.

3. The instruction execution unit according to claim 1, wherein, The flushing subunit is configured to determine the speculative instruction located at the checkpoint as a failed speculative instruction when the acquisition subunit receives the flushing request for the production line. When the speculative instructions in each stage of the production line before the checkpoint pass through the checkpoint in sequence, the subunit determines the relationship between the old and new speculative instructions passing through the checkpoint and the failed speculative instructions. If the speculative instruction passing through the checkpoint is older than the failed speculative instruction, the speculative instruction passing through the checkpoint is executed. If the speculative instruction passing through the checkpoint is newer than the failed speculative instruction, the speculative instruction passing through the checkpoint is not executed.

4. A processing unit, comprising: The instruction fetch unit is used to fetch the instruction to be executed. An instruction decoding unit is used to decode the instruction to be executed; The instruction issuing unit is used to send the decoded instruction to be executed to the instruction execution unit; At least one instruction execution unit according to any one of claims 1-3.

5. The processing unit of claim 4, wherein, The processing unit further includes: The retirement unit is used to determine the pipeline flushing range based on the cause of the speculation failure when a speculation failure occurs, and to send a pipeline flushing request to the instruction execution unit located within the pipeline flushing range.

6. A computing device, comprising: The processing unit according to claim 4 or 5; The memory, coupled to the processing unit, stores instructions to be executed.

7. A method for flushing a production line, comprising: In the event of a speculation failure, obtain a pipeline flushing request for the instruction execution unit; In response to the pipeline flushing request, the instruction execution unit is pipeline flushed according to the execution delay and architecture of the instruction execution unit through a first flushing mode and / or a second flushing mode, wherein the first flushing mode clears speculative instructions on the error path before the instruction is executed, and the second flushing mode prevents speculative instructions on the error path from having an execution effect. The step of pipeline flushing the instruction execution unit according to its execution latency and architecture using a first flushing mode and / or a second flushing mode includes: when the average execution latency of the instruction execution unit is greater than a preset latency threshold or the instruction execution unit is an in-order processing architecture, pipeline flushing the instruction execution unit using the first flushing mode; when the average execution latency of the instruction execution unit is less than or equal to the latency threshold and the instruction execution unit is an out-of-order processing architecture, pipeline flushing the instruction execution unit using the second flushing mode. The execution unit performs pipeline flushing; when the execution delay of the instruction execution unit dynamically changes around the delay threshold, for the N-stage pipelines included in the instruction execution unit, the pipelines after the checkpoint are flushed using the first flushing mode, and the pipelines before the checkpoint are flushed using the second flushing mode, where N is a positive integer greater than or equal to 3, the checkpoint is the M-th stage pipeline in the N-stage pipeline, M is a positive integer greater than 1 and less than N, and the instruction to be executed is determined to pass through the checkpoint.

8. The automated flushing method according to claim 7, wherein, The first flushing mode includes: identifying the speculation failure instruction that caused the speculation failure; determining the relationship between each speculation instruction in the instruction execution unit and the speculation failure instruction based on the pipeline depth of the instruction execution unit; determining the first speculation instruction located on the wrong path and the second speculation instruction located on the correct path in the instruction execution unit based on the relationship; clearing the first speculation instruction and allowing the second speculation instruction to continue execution. The second flushing mode includes: after all instructions in the instruction execution unit have been executed, based on the relationship between the old and new instructions, determining the third speculative instruction located on the wrong path and the fourth speculative instruction located on the correct path in the instruction execution unit, so that the third speculative instruction does not produce an execution effect, and the fourth speculative instruction produces an execution effect.

9. The pipeline flush method of claim 7, wherein, The process of flushing the production lines at each stage before the checkpoint using the second flushing mode includes: When the acquisition subunit receives the pipeline flushing request, the speculative instruction located at the checkpoint is determined as a speculative failure instruction. When speculative instructions in each stage of the pipeline before the checkpoint pass through the checkpoint in sequence, the relationship between the speculative instruction passing through the checkpoint and the speculative failure instruction is determined. If the speculative instruction passing through the checkpoint is older than the speculative failure instruction, the speculative instruction passing through the checkpoint is executed. If the speculative instruction passing through the checkpoint is newer than the speculative failure instruction, the speculative instruction passing through the checkpoint is not executed.

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