A super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof

Abstract

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, specifically to a superjunction LDMOS device with a high-resistivity substrate and TSV grounding, and its fabrication method. Background Technology

[0002] Superjunction structures exhibit superior performance in power semiconductor devices, breaking the limits of on-resistance and breakdown voltage in silicon. They are widely used and have achieved significant commercial success in vertical devices such as VDMOS / IGBT. However, their application in lateral devices, such as LDMOS, especially RF LDMOS, is less common. In fact, superjunction structures used in the drift region of RFLDMOS can also improve the device's Rdson and BV, and can achieve a more uniform lateral electric field distribution in the drift region, reducing the gate edge electric field strength, effectively suppressing HCI, and improving the reliability of RFLDMOS devices.

[0003] For LDMOS devices used in power applications, especially RF LDMOS devices, on-resistance Ron and output capacitance Coss are the main factors limiting device efficiency. Traditional LDMOS devices employ an epitaxial layer on a low-resistivity substrate, with the device designed on this layer. On-resistance is reduced by increasing the doping concentration in the drift region. However, directly increasing the doping concentration has the negative effect of increasing the difficulty of drift region depletion, leading to an uneven electric field in the drift region and a decrease in breakdown voltage. Adding a G-shield can enhance the RESURF effect, uniformizing the electric field in the drift region and mitigating the breakdown voltage decrease caused by increased doping concentration. However, the parasitic capacitance added by the G-shield increases Coss. In summary, the existing technology's device design is flawed, and on-resistance Ron and output capacitance Coss limit the device's efficiency and power density. Summary of the Invention

[0004] The main objective of this invention is to provide a superjunction LDMOS device with a high-resistivity substrate and TSV grounding, and a method for fabricating the same, in order to solve the aforementioned problems.

[0005] To achieve the aforementioned objectives, the present invention adopts the following technical solution:

[0006] One aspect of this invention provides a superjunction LDMOS device with a high-resistivity substrate and TSV ground, comprising:

[0007] A high-resistivity substrate has a first surface and a second surface, wherein the first surface and the second surface are disposed opposite to each other.

[0008] The bulk region and drift region are formed under the first surface of the high-resistivity substrate;

[0009] The body region contact region and source region formed in the body region;

[0010] A polysilicon gate formed on the first surface of the substrate above the bulk region;

[0011] The leak region formed in the drift region;

[0012] The drift region includes a first pillar region and a second pillar region, wherein the first pillar region and the second pillar region are spaced apart in the width direction of the gate and form a superjunction structure; wherein...

[0013] A first buffer layer is provided between the first column area and the drain area, and a second buffer layer is provided between the second column area and the drain area, with the first buffer layer and the second buffer layer surrounding the drain area.

[0014] Furthermore, the drain area, the first pillar area, and the first buffer layer are of a first conductivity type, the second pillar area is of a second conductivity type, and the second buffer layer is of either the first conductivity type or the second conductivity type.

[0015] Furthermore, the first conductivity type is N-type, the second conductivity type is P-type, and the superjunction LDMOS device is an N-type LDMOS device.

[0016] Furthermore, the first conductivity type is P-type, the second conductivity type is N-type, and the superjunction LDMOS device is a P-type LDMOS device.

[0017] Furthermore, the doping concentration of the first buffer layer is between the doping concentrations of the first pillar region and the drain region, and the doping concentration of the second buffer layer is between the doping concentrations of the second pillar region and the drain region.

[0018] Furthermore, the first buffer layer and the second buffer layer both form a gradually changing junction structure between the drain region and the first pillar region, and between the drain region and the second pillar region.

[0019] Furthermore, a second column area is provided on both sides of any first column area, and the width and spacing of the first column areas are both less than 0.5μm.

[0020] Furthermore, the aforementioned superjunction LDMOS device also includes: a first metal layer, a contact via, and a through-silicon via (TSV). The first metal layer covers the body region and is connected to the source region and the contact region of the body region through the contact via. The first metal layer is also connected to the second surface of the high-resistivity substrate through the through-silicon via (TSV).

[0021] Furthermore, a GND layer formed by a second metal layer is disposed on the second surface of the high-resistivity substrate, and the TSV passes through the high-resistivity substrate in the thickness direction of the high-resistivity substrate and is connected to the GND layer.

[0022] Furthermore, the resistivity of the high-resistivity substrate is greater than 3000 ohm*cm.

[0023] Another aspect of the present invention provides a method for fabricating the above-mentioned high-resistivity substrate TSV-grounded superjunction LDMOS device, which includes:

[0024] Provide a high-resistivity substrate;

[0025] A polysilicon gate is formed in a selected region on the high-resistivity substrate;

[0026] A bulk region and a drift region are formed in a selected area within the high-resistivity substrate;

[0027] The drift region is processed into a first column region and a second column region arranged at intervals in the gate width direction to form a superjunction structure;

[0028] A first buffer region and a second buffer region are formed by processing a selected area within the drift region;

[0029] A leak area is formed within the first buffer area and the second buffer area;

[0030] A source region and a contact region between the source region and the body region are formed in a selected area within the body region.

[0031] Furthermore, the above manufacturing method also includes: forming a first buffer layer between the first buffer area and the leak area, and forming a second buffer layer between the second buffer area and the leak area.

[0032] Furthermore, the above-mentioned manufacturing method also includes:

[0033] Processing the first metal layer, the second metal layer, contact vias, and through-silicon vias (TSVs);

[0034] The body region contact area and source region are connected to the first metal layer through contact vias;

[0035] The first metal layer is connected to the second metal layer on the second surface of the high-resistivity substrate through a through-silicon via (TSV).

[0036] Compared with the prior art, the superjunction LDMOS device with high-resistivity substrate TSV grounding and its fabrication method provided by the embodiments of the present invention have at least the following beneficial effects:

[0037] 1) By realizing a lateral superjunction structure on a high-resistivity substrate, the substrate-assisted effect is effectively suppressed, and the RESURF effect is enhanced by the superjunction structure, thus achieving the optimal design of device breakdown voltage and on-resistance.

[0038] 2) Based on the above superjunction structure, the shielding metal layer G-shield was removed, which reduced the parasitic capacitance generated by the shielding metal layer and lowered the output capacitance of the device.

[0039] 3) By setting a buffer layer between the superjunction structure and the drain, and by reducing the peak electric field of the device through the gradually changing junction formed by the buffer layer, the breakdown voltage of the device is improved. Attached Figure Description

[0040] To more clearly illustrate the technical solution of the present invention, the accompanying drawings will be briefly described below. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0041] Figure 1 This is a three-dimensional structural schematic diagram of a superjunction LDMOS device with a high-resistivity substrate TSV grounded according to an embodiment of the present invention;

[0042] Figure 2 This is a top view schematic diagram of a superjunction LDMOS device with a high-resistivity substrate TSV grounded according to an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures: 1. High-resistivity substrate, 10. Body region, 11. Drift region, 101. Body region contact region, 102. Source region, 103. Polysilicon gate, 104. First metal layer, 105. Contact via, 106. Through-silicon via (TSV), 111. Drain region, 112. First pillar region, 113. Second pillar region, 114. First buffer region, 115. Second buffer region. Detailed Implementation

[0044] In view of the shortcomings of the prior art, the inventors of this case, through long-term research and practice, have proposed the technical solution of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0045] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0047] Example 1

[0048] Please see Figure 1-2 This embodiment provides a high-resistivity substrate TSV-grounded superjunction NLDMOS device, which includes:

[0049] A high-resistivity substrate 1 has a first surface and a second surface, the first surface and the second surface being disposed opposite to each other, and the resistivity of the high-resistivity substrate is greater than 3000 ohm*cm.

[0050] A polysilicon gate 103 is formed on the first surface of the high-resistivity substrate 1;

[0051] A bulk region 10 and a drift region 11 are formed within a high-resistivity substrate 1;

[0052] The body region contact region 101 and the source region 102 are formed within the body region 10;

[0053] Leakage area 111 formed within drift region 11;

[0054] The drift region 11 includes an N-type doped first pillar region 112 and a P-type doped second pillar region 113. The first pillar region 112 and the second pillar region 113 are spaced apart in the width direction of the polysilicon gate 103 and form a superjunction structure.

[0055] A first buffer layer is provided between the first pillar region 112 and the drain region 111, and a second buffer layer is provided between the second pillar region 113 and the drain region 111. Both the first buffer layer and the second buffer layer surround the drain region 111, and the drain region 111, the first buffer layer and the second buffer layer are all N-type doped.

[0056] Furthermore, the superjunction NLDMOS device also includes: a first metal layer 104, a contact via 105, and a through-silicon via (TSV) 106. The first metal layer 104 covers the body region 10 and is electrically connected to the source region 102 and the body contact region 101 through the contact via 105. The first metal layer 104 is also electrically connected to the second surface of the high-resistivity substrate 1 through the through-silicon via (TSV) 106.

[0057] It should be noted that the drain area 111 is also electrically connected to the corresponding metal layer through the corresponding contact via 105.

[0058] Furthermore, a second metal layer, which is a GND layer, is disposed on the second surface of the high-resistivity substrate 1. The through-silicon via (TSV) 106 passes through the body region 10 in the thickness direction of the high-resistivity substrate 1 and is connected to the GND layer.

[0059] In operation, the NLDMOS device controls its on / off state via a polysilicon gate 103 and provides a potential to the body region 10 via a body contact region 101. When the polysilicon gate 103 reaches a certain potential, the device turns on, and charge carriers travel from the source region 102 through the channel below the polysilicon gate 103, enter the drift region 11, and reach the drain region 111. When the polysilicon gate 103 falls below a certain potential, the device turns off.

[0060] Furthermore, the doping concentration of the first buffer layer between the first pillar region 112 and the drain region 111 is between the doping concentrations of the first pillar region 112 and the drain region 111, and the doping concentration of the second buffer layer between the second pillar region 113 and the drain region 111 is between the doping concentrations of the second pillar region 113 and the drain region 111. Thus, a gradually changing junction structure is formed between the drain region 111 and the first pillar region 112, and between the drain region 111 and the second pillar region 113. This gradually changing junction can reduce the peak electric field of the device, thereby improving the breakdown voltage of the device.

[0061] Furthermore, a second column area 113 is provided on both sides of any of the first column areas 112, and the width and spacing of the first column areas 112 are both less than 0.5μm, that is, the width of the first column area 112 and the second column area 113 are both less than 0.5μm.

[0062] In one embodiment, the width of the first column region 112 may be between 0.5 μm and 5 μm, and the width of the second column region 113 may be between one-tenth and one-half of the width of the first column region 112.

[0063] Furthermore, this embodiment also provides a method for fabricating the above-mentioned superjunction NLDMOS device, which includes:

[0064] First, a high-resistivity substrate 1 is provided.

[0065] Furthermore, a polysilicon gate 103 is formed in a selected region on the first surface of the high-resistivity substrate 1.

[0066] Furthermore, a body region 10 and a drift region 11 are formed on the first surface of the high-resistivity substrate 1.

[0067] Furthermore, the drift region 11 is subjected to overall P-type ion doping to form a P-type region, and local N-type ion implantation with layout control is used to divide the P-type region into a first pillar region 112 and a second pillar region 113 arranged at intervals in the width direction of the polysilicon gate 103. The layout control here can use hard layout control, which can improve the processing accuracy of the photoresist.

[0068] In one embodiment, the drift region 11 can be entirely doped with N-type ions to form an N-type region, and then localized P-type ion implantation with layout control can be used to divide the N-type region into a first pillar region 112 and a second pillar region 113 arranged at intervals in the width direction of the polysilicon gate 103.

[0069] Furthermore, using layout-controlled local N-type ion implantation, a first buffer region 114 and a second buffer region 115 are formed in selected areas within the drift region 11 (which has now been processed into a first column region 112 and a second column region 113 arranged at intervals), wherein the implantation depth of the first buffer region 114 and the second buffer region 115 is less than the thickness of the drift region 11.

[0070] Furthermore, using layout-controlled local N-type ion implantation, a drain region 111 is formed in a selected area within the first buffer region 114 and the second buffer region 115, and a drain electrode is fabricated on the drain region 111.

[0071] At this time, a first buffer layer and a second buffer layer are formed in the first buffer area 114 and the second buffer area 115 between the first column area 112, the second column area 113 and the drain area 111, and both the first buffer layer and the second buffer layer are N-type.

[0072] Furthermore, a layout-controlled local P-type ion implantation is used to form a body contact region 101 in a selected area within the body region 10, and a layout-controlled local N-type ion implantation is used to form a source region 102 in a selected area within the body region 10, and a source electrode is fabricated on the source region 102.

[0073] Finally, a first metal layer 104 is formed above the first surface of the high-resistivity substrate 1, a second metal layer is formed below the second surface of the substrate 1, and contact vias 105 and through-silicon vias (TSVs) 106 are processed inside the high-resistivity substrate 1. The body contact region 101 and the source region 102 are connected to the first metal layer 104 through the contact vias 105, and the first metal layer 104 is connected to the second metal layer on the second surface of the high-resistivity substrate 1 through the through-silicon vias (TSVs) 106.

[0074] The ion implantation concentrations of the first column region 112 and the second column region 113 are lower than the ion implantation concentrations of their corresponding first buffer region 114 and second buffer region 115, and the ion implantation concentrations of the first buffer region 114 and the second buffer region 115 are lower than the ion implantation concentrations of the drain region 111.

[0075] Specifically, the ion implantation concentrations of the first column region 112 and the second column region 113 are both between 1E12 cm⁻³ and 1E13 cm⁻³, and the ion implantation concentration of the leak region 103 is between 1E14 cm⁻³ and 1E16 cm⁻³.

[0076] Example 2

[0077] This embodiment provides another superjunction NLDMOS device with a high-resistivity substrate TSV ground. The difference from Embodiment 1 is that the second buffer region 115, that is, the second buffer layer between the second pillar region 113 and the drain region 111, is a P-type buffer layer.

[0078] Example 3

[0079] This embodiment provides a superjunction PLDMOS device with a high-resistivity substrate and TSV grounding. The difference from Embodiment 1 is that the first pillar region 112 is P-type, the second pillar region 113 is N-type, and the drain region 111, the first buffer layer between the first pillar region 112 and the drain region 111, and the second buffer layer between the second pillar region 113 and the drain region 111 are all P-type. Alternatively, the first buffer layer between the drain region 111, the first pillar region 112 and the drain region 111 is P-type, while the second buffer layer between the second pillar region 113 and the drain region 111 is N-type.

[0080] This invention provides a superjunction NLDMOS device with a high-resistivity substrate and TSV ground. By realizing a lateral superjunction structure on a high-resistivity substrate, the substrate-assisted effect is effectively suppressed, and the RESURF effect is enhanced through this superjunction structure, achieving optimal design of the device's breakdown voltage BV and on-resistance Ron. Furthermore, based on the above superjunction structure, the shielding metal layer G-shield of traditional devices is removed, reducing the parasitic capacitance generated by G-shield and lowering the output capacitance Coss. In addition, by setting a buffer layer between the superjunction structure and the drain, the peak electric field of the device is reduced through the gradually changing junction formed by the buffer layer between the superjunction structure and the drain, thereby improving the device's breakdown voltage BV.

[0081] The present invention provides a superjunction NLDMOS device with a high-resistivity substrate TSV ground, which can reduce the on-resistance Ron by about 25% and the output capacitance by about 50% while meeting the breakdown voltage BV.

[0082] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any transformations or substitutions that can be conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of the present invention.

Claims

1. A high-resistance substrate TSV grounded super junction LDMOS device, characterized in that include: A high-resistivity substrate has a first surface and a second surface, wherein the first surface and the second surface are disposed opposite to each other. A polysilicon gate formed on the first surface of the substrate; The bulk region and drift region are formed under the first surface of the high-resistivity substrate; The body region contact region and source region formed in the body region; The leak region formed in the drift region; The drift region includes a first pillar region and a second pillar region, wherein the first pillar region and the second pillar region are spaced apart in the width direction of the gate and form a superjunction structure; wherein... A first buffer layer is disposed between the first pillar region and the drain region, and a second buffer layer is disposed between the second pillar region and the drain region. The first and second buffer layers surround the drain region. The doping concentration of the first buffer layer is between the doping concentrations of the first pillar region and the drain region, and the doping concentration of the second buffer layer is between the doping concentrations of the second pillar region and the drain region. The drain region, the first pillar region, and the first buffer layer are of a first conductivity type, the second pillar region is of a second conductivity type, and the second buffer layer is of either a first conductivity type or a second conductivity type. The first conductivity type is N-type, and the second conductivity type is P-type. The superjunction LDMOS device is an N-type LDMOS device. Alternatively, the first conductivity type is P-type, the second conductivity type is N-type, and the superjunction LDMOS device is a P-type LDMOS device.

2. The super junction LDMOS device of claim 1, wherein: A second column area is provided on both sides of any of the first column areas, and the width and spacing of the first column areas are both less than 0.5μm.

3. The super junction LDMOS device of claim 1, wherein, Also includes: A first metal layer, a contact via, and a through-silicon via are provided. The first metal layer covers the body region and is electrically connected to the source region and the contact region of the body region via the contact via. The first metal layer is also electrically connected to the second surface of the high-resistivity substrate via the through-silicon via.

4. The super junction LDMOS device of claim 3, wherein: A GND layer formed by a second metal layer is disposed on the second surface of the high-resistivity substrate, and the through silicon via passes through the high-resistivity substrate in the thickness direction of the high-resistivity substrate and is connected to the GND layer.

5. The super junction LDMOS device of claim 4, wherein: The resistivity of the high-resistivity substrate is greater than 3000 ohm*cm.

6. The method of fabricating a high-resistance substrate TSV grounded super junction LDMOS device according to any one of claims 1-5, wherein, include: Provide a high-resistivity substrate; A polysilicon gate is formed in a selected area on the first surface of the high-resistivity substrate; A bulk region and a drift region are formed in a selected area within the high-resistivity substrate; The drift region is processed into a first column region and a second column region arranged at intervals in the gate width direction to form a superjunction structure; A first buffer region and a second buffer region are formed by processing a selected area within the drift region; A drain region is formed in the first buffer region and the second buffer region. A first buffer layer is formed between the first buffer region and the drain region. A second buffer layer is formed between the second buffer region and the drain region. The doping concentration of the first buffer layer is between the doping concentration of the first pillar region and the drain region, and the doping concentration of the second buffer layer is between the doping concentration of the second pillar region and the drain region. A source region and a body region contact region are formed in a selected area within the body region; The first conductive type is N type, the second conductive type is P type, the super-junction LDMOS device is an N type LDMOS device, or the first conductive type is P type, the second conductive type is N type, and the super-junction LDMOS device is a P type LDMOS device.

7. The method of manufacturing a super junction LDMOS device according to claim 6, wherein, Further comprising: processing the first metal layer, the second metal layer, the contact via and the through-silicon via; connecting the body region contact region and the source region to the first metal layer through the contact via; connecting the first metal layer to the second metal layer on the second surface of the high-resistance substrate through the through-silicon via.

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