A processing method and system for high-speed storage data based on EEPROM
By classifying data by function in the EEPROM and using dual buffers to manage data writing, the problem of multiple data write conflicts in automobiles is solved, achieving accuracy and efficiency in data writing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN SOUTH SAGITTARIUS INTEGRATION CO LTD
- Filing Date
- 2022-07-31
- Publication Date
- 2026-06-12
AI Technical Summary
In automobiles, when multiple data are written to the EEPROM simultaneously, write conflicts are likely to occur, leading to inaccurate and inefficient data writing.
Data is categorized by function and stored in partitions. Two caches (first cache and second cache) are used to handle data writing. The writing order of cached data is managed by judging changes in EEPROM data, ensuring data accuracy and efficiency.
When multiple data are written simultaneously, the accuracy and efficiency of data storage are maximized, and data loss is avoided.
Smart Images
Figure CN115292212B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage, and more specifically to a processing method and system for high-speed data storage based on EEPORM. Background Technology
[0002] With the rapid development of the automotive industry, the functions supported by automobiles have become increasingly diverse, resulting in a greater variety and types of data that need to be stored. For example, the same instrument cluster can be compatible with multiple car models, thus requiring the storage of calibrations for various functions supported by that model, as well as calibrations for various ECU (Electronic Control Unit) models. Similarly, during vehicle operation, total mileage and various real-world vehicle data need to be continuously saved. To ensure that the data is not lost after power failure, it is typically stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory) chip.
[0003] While the primary factor influencing data write speed is the baud rate of the I2C bus (two-wire synchronous serial bus) in the driver layer—a higher baud rate theoretically results in faster transmission and write speeds—the write frequency at the application layer is determined by the business logic. Different functions may experience write conflicts during data storage. For example, while the main control chip is writing data A, data B, which needs to be saved, might change within the application layer and require storage; or data A might change again, requiring rewriting. Therefore, ensuring accuracy and efficiency in writing multiple data sets of the same or different types simultaneously is a pressing issue that needs to be addressed. Summary of the Invention
[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a processing method and system for high-speed data storage based on EEPORM, which can effectively ensure the accuracy and efficiency of data writing.
[0005] To achieve the above objectives, this invention provides a method for processing high-speed stored data based on EEPORM, specifically including the following steps:
[0006] The data is categorized based on its function, and the EEPROM is partitioned, with each partition storing a specific type of data.
[0007] For each type of data, two caches are created: the first cache and the second cache.
[0008] The data transmitted from the application layer is received and cached based on the first cache, and after the data is cached in the first cache, the cached data is written to the corresponding partition of the EEPROM.
[0009] When the first buffer writes data to the EEPROM, it determines whether the data being written to the EEPROM has changed:
[0010] If so, the data transmitted again by the application layer is written to the second buffer, and after the data previously in the first buffer is written to the EEPROM, the data in the second buffer is written to the first buffer.
[0011] If not, no action will be taken.
[0012] Based on the above technical solutions,
[0013] The EEPROM also includes partition information;
[0014] The partition information includes the current chip status, as well as the starting address and status of each partition.
[0015] Based on the above technical solutions, for EEPORM:
[0016] Create a first page of a preset size to store partition information;
[0017] After the first page of space, the space is divided into equal partitions according to the set size, and each partition corresponds to storing one type of data.
[0018] Based on the above technical solution, the specific steps of receiving and caching data transmitted from the application layer using a first cache, and writing all cached data to the corresponding partition of the EEPROM after caching is completed in the first cache, include:
[0019] The driver layer receives the data to be saved transmitted from the application layer, locks the first cache, and caches the received application layer data through the first cache.
[0020] After the first cache completes the data caching, the driver layer writes the data in the first cache to the corresponding partition of the EEPROM based on the I2C bus.
[0021] Based on the above technical solution, after writing the data transmitted again from the application layer into the second buffer, and after writing the previous data in the first buffer into the EEPROM, and then writing the data in the second buffer into the first buffer, the solution further includes:
[0022] The first buffer caches the data transmitted from the second buffer, and then writes the cached data into the corresponding partition of the EEPROM.
[0023] Based on the above technical solutions,
[0024] Both the first cache and the second cache include flag bits;
[0025] The flag in the first cache is used to determine whether there is a task that writes data to EEPORM.
[0026] The flag bit of the second cache is used to determine whether the data being written to the EEPROM has changed during the process of writing data to the EEPROM;
[0027] Based on the above technical solutions,
[0028] When there is no data being written to the EEPROM in the first cache, or when the previous data in the first cache has been written to the EEPROM and the data in the second cache has been written to the first cache, and then the data in the first cache is written to the EEPROM again, the flag of the first cache is set to 1.
[0029] When the flag of the first buffer is set to 1, when the application layer transmits data again, regardless of the value of the flag of the second buffer, the flag of the second buffer will be set to 1.
[0030] Based on the above technical solutions,
[0031] Once the data cached in the first cache has been written to the EEPROM, the flag of the first cache is set to 0.
[0032] After the data in the first cache is written to the EEPROM, and the data in the second cache is written to the first cache, the flag of the second cache is set to 0.
[0033] Based on the above technical solution, when different types of data need to be written to EEPROM continuously:
[0034] When the current type of data is being written to the EEPROM from the corresponding first cache, the next type of data to be written is cached in the second cache corresponding to that type of data;
[0035] Determine if there is still data to be written to EEPROM in the first cache corresponding to the current data type:
[0036] If not, the next type of data to be written will be written from the corresponding second cache to the corresponding first cache, and then written to the corresponding partition of the EEPROM;
[0037] If so, wait until all the data in the first cache corresponding to the current type of data is written to the EEPROM, and no more data is added to the first cache corresponding to the current type of data. Then, write the next type of data to be written from the corresponding second cache to the corresponding first cache, and then write it to the corresponding partition of the EEPROM.
[0038] This invention provides a high-speed data processing system based on EEPORM storage, comprising:
[0039] The classification module is used to classify data based on data functions and partition the EEPROM, with each partition corresponding to a type of data.
[0040] The module creates two caches for each type of data: a first cache and a second cache.
[0041] The write module is used to receive and cache data transmitted from the application layer based on the first cache, and after the data is cached in the first cache, write all the cached data into the corresponding partition of the EEPROM.
[0042] The judgment module is used to determine whether the data being written to the EEPROM has changed when the first buffer writes data to the EEPROM.
[0043] If so, the data transmitted again by the application layer is written to the second buffer, and after the data previously in the first buffer is written to the EEPROM, the data in the second buffer is written to the first buffer.
[0044] If not, no action will be taken.
[0045] Compared with the prior art, the advantages of the present invention are as follows: by creating a first cache and a second cache for each type of data, the first cache receives data transmitted from the application layer and writes it into the corresponding partition of the EEPROM. When the first cache writes data to the EEPROM, if the data being written to the EEPROM changes, the data transmitted again by the application layer is written to the second cache. After the previous data in the first cache is written to the EEPROM, the data in the second cache is written to the first cache and then written to the EEPROM. This ensures that when multiple data of the same or different types need to be written at the same time, the data storage work is maximized without losing the currently written data, thus guaranteeing the accuracy and efficiency of data writing. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 This is a flowchart of a high-speed data storage processing method based on EEPORM in an embodiment of the present invention. Detailed Implementation
[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0049] See Figure 1 As shown, this embodiment of the invention provides a high-speed data storage processing method based on EEPORM, which enables the maximization of data storage without losing currently written data when multiple data of the same or different types need to be written simultaneously, ensuring the accuracy and efficiency of data writing. The processing method specifically includes the following steps:
[0050] S1: Classify the data based on its function and partition the EEPROM, with each partition storing a specific type of data.
[0051] S2: Two caches are created for each type of data, namely the first cache and the second cache; the data writing is to adapt to the situation where multiple write instructions are received at the same time during the writing process of the driver layer, that is, instructions to write the same or different types of data are received at the same time. Two caches are set for each data type.
[0052] S3: Receive and cache data transmitted from the application layer based on the first cache, and write all cached data into the corresponding partition of EEPROM after the data caching in the first cache is completed;
[0053] S4: When the first buffer writes data to the EEPROM, determine whether the data being written to the EEPROM has changed. If yes, proceed to S5; otherwise, proceed to S6.
[0054] S5: Write the data transmitted again by the application layer into the second buffer, and after the data previously in the first buffer has been written into the EEPROM, write the data in the second buffer into the first buffer;
[0055] S6: No action taken.
[0056] The above process is illustrated with a specific example below. For instance, if multiple types of data need to be written, including data A, data B, and data C, then for data A: Data A transmitted from the application layer is received and cached in the first cache. Then, the cached data A in the first cache is written to the corresponding partition of the EEPROM. While data A is being written to the EEPROM, it is determined whether data A has changed. If not, no further processing is done, and the cached data A in the first cache is continued to be written to the corresponding partition of the EEPROM. If so, the modified data A transmitted from the application layer is written to the second cache. Then, after the previously cached data in the first cache is written to the EEPROM, the modified data A cached in the second cache is written to the first cache. Finally, the first cache writes the modified data A to the corresponding partition of the EEPROM. For data B and data C, the same processing logic is followed, operating based on the corresponding first and second caches to achieve data writing to the EEPROM.
[0057] In this embodiment of the invention, the EEPROM also includes partition information; the partition information includes the current chip state, and the start address and state of each partition. For EEPROM:
[0058] a: Create a first page of a preset size to store partition information;
[0059] b: After the first page of space, partition the space into equal-sized partitions according to the set size, and each partition corresponds to storing one type of data.
[0060] The data is first categorized by function, and then the first page of the EEPROM is used to store partition information, which is equivalent to the directory of the entire EEPROM. The addresses after the first page are partitioned into equal spaces according to the set size to store different types of data.
[0061] In one possible real-time approach, the first page space is 128 bytes in size, and the partition space used to store different types of data is 4 KB each.
[0062] In this embodiment of the invention, data transmitted from the application layer is received and cached based on a first cache, and after the data caching in the first cache is completed, the cached data is written to the corresponding partition of the EEPROM. Specific steps include:
[0063] S301: The driver layer receives the data to be saved transmitted from the application layer, locks the first buffer, and caches the received application layer data through the first buffer;
[0064] S302: After the first cache completes the data caching, the driver layer writes the data in the first cache to the corresponding partition of the EEPROM based on the I2C bus.
[0065] In this embodiment of the invention, after writing the data transmitted again by the application layer into the second buffer, and after the data previously in the first buffer has been written into the EEPROM, and then writing the data in the second buffer into the first buffer, the method further includes:
[0066] The first buffer caches the data transmitted from the second buffer, and then writes the cached data into the corresponding partition of the EEPROM.
[0067] In this invention, the first buffer is used by the driver layer to receive data that needs to be saved from the application layer. The driver layer uses the I2C bus to write the data in the first buffer to a specified address in the EEPROM. Once the driver layer receives the data from the application layer, it locks the first buffer to ensure that the data is not changed during the writing process. Otherwise, if the data in the first buffer changes after verification, the checksum of the data stored in the EEPROM will not match the stored data, which will cause the verification to fail when reading the data, thus making it impossible to ensure the accuracy of the data.
[0068] The function of the second buffer is as follows: After the first buffer receives data from the application layer, it is locked. If the data being written to the EEPROM changes at this time, and the application layer calls the driver layer's write interface again, it cannot save the data to the first buffer. In this case, the data sent by the application layer is saved to the second buffer. After all the data in the first buffer has been written, the data in the second buffer is copied to the first buffer. This ensures that when writing data from the first buffer to the EEPROM, no matter how many times the application layer calls the write command, the latest data will be saved to the second buffer.
[0069] In this embodiment of the invention, both the first cache and the second cache include flag bits. The flag bits of the first cache are used to determine whether there is currently a task writing data to the EEPROM. The flag bits of the second cache are used to determine whether the data being written to the EEPROM has changed during the data writing process. During the writing of the same type of data, each type of data corresponds to two flag bits used in combination.
[0070] When there is no data being written to the EEPROM in the first cache, or when the previous data in the first cache has been written to the EEPROM and the data in the second cache has been written to the first cache, and then the data in the first cache is written to the EEPROM again, the flag of the first cache is set to 1.
[0071] When the flag of the first buffer is set to 1, when the application layer transmits data again, regardless of the value of the flag of the second buffer, the flag of the second buffer will be set to 1.
[0072] Once the data cached in the first cache has been written to the EEPROM, the flag of the first cache is set to 0.
[0073] After the data in the first cache is written to the EEPROM, and the data in the second cache is written to the first cache, the flag of the second cache is set to 0.
[0074] In one possible implementation, when different types of data need to be written to the EEPROM continuously:
[0075] When the current type of data is being written to the EEPROM from the corresponding first cache, the next type of data to be written is cached in the second cache corresponding to that type of data;
[0076] Determine if there is still data to be written to EEPROM in the first cache corresponding to the current data type:
[0077] If not, the next type of data to be written will be written from the corresponding second cache to the corresponding first cache, and then written to the corresponding partition of the EEPROM;
[0078] If so, wait until all the data in the first cache corresponding to the current type of data is written to the EEPROM, and no more data is added to the first cache corresponding to the current type of data. Then, write the next type of data to be written from the corresponding second cache to the corresponding first cache, and then write it to the corresponding partition of the EEPROM.
[0079] For example, when writing data type X, if an instruction to write data Y is received, data Y is first stored in its corresponding second cache, and the first or second cache flag corresponding to data Y is set to 1, indicating that there is a task to be written. After writing data X, the system first checks whether the first cache flags of all data are cleared. If there are any items that are not cleared, the writing process for the corresponding data begins. Only when all the first cache flags are 0 will the system check whether there is a task to be written in the second cache.
[0080] The reason for prioritizing data types whose first cache flag is not cleared is that data is written at varying frequencies, giving less frequently written data a relatively higher priority. Prioritizing the second cache flag might cause data X to be continuously updated, resulting in data X and data Y receiving write commands at the same time having to wait for the more frequently updated data X to stop being updated before the less frequently written data Y begins to be written.
[0081] The process of this invention will be described in detail below:
[0082] A: Check if the first cache flag is set to 1. If yes, it means that there is a task writing the current type of data. Proceed to B. If no, it means that there is no task writing the current type of data. Proceed to C.
[0083] B: Regardless of the value of the second cache flag, set it to 1, then copy the latest data to the corresponding cache, and proceed to D;
[0084] C: Set the first cache flag to 1, then copy the written data to the corresponding cache, and proceed to D;
[0085] D: Start the timer; when the timer expires, enter the callback function and proceed to E.
[0086] E: Determine if there are any unfinished write tasks. If yes, proceed to F; otherwise, proceed to G.
[0087] F: Continue the process of completing the current write task and proceed to N;
[0088] G: Determine if there is a non-zero entry in the first cache flag for all data types. If yes, proceed to H; otherwise, proceed to I.
[0089] H: Begin the write process for the current data type, then proceed to N;
[0090] I: Determine if there are any non-zero entries in the second cache flag for all data types. If yes, go to J; otherwise, go to K.
[0091] J: Copy the corresponding data from the second cache to the first cache, clear the second cache flag to zero, set the first cache flag to 1, and move to N;
[0092] K: Determine whether an address offset occurred during the write process. If yes, proceed to L; otherwise, proceed to M.
[0093] L: Data writing complete, update directory, move to N;
[0094] M: End of write, which means the timer reloads the time parameters and the current loop ends.
[0095] N: Starts the timer and triggers a callback at regular intervals, then jumps to D. You can re-enter this callback function in two ways: 1. Start the timer after completing the IIC read / write operation; 2. Start the timer after completing verification or other steps.
[0096] The data processing method based on EEPROM high-speed storage in this invention creates a first cache and a second cache for each type of data. The first cache receives data transmitted from the application layer and writes it into the corresponding partition of the EEPROM. When the first cache writes data to the EEPROM, if the data being written to the EEPROM changes, the data transmitted again by the application layer is written to the second cache. After the data previously written to the EEPROM in the first cache is completed, the data in the second cache is written to the first cache, and then written to the EEPROM. This ensures that when multiple data of the same or different types need to be written at the same time, the data storage work is maximized without losing the currently written data, thus guaranteeing the accuracy and efficiency of data writing.
[0097] This invention provides a high-speed EEPROM-based data processing system, comprising a classification module, a creation module, a writing module, and a judgment module. The classification module classifies data based on its function and partitions the EEPROM, with each partition corresponding to a specific type of data. The creation module creates two caches for each type of data: a first cache and a second cache. The writing module receives and caches data transmitted from the application layer in the first cache, and writes the cached data into the corresponding partition of the EEPROM after the data in the first cache is cached. The judgment module determines whether the data being written to the EEPROM has changed when the first cache writes data to the EEPROM. If so, it writes the data transmitted again from the application layer into the second cache, and after the previous data in the first cache is written to the EEPROM, it writes the data in the second cache into the first cache; otherwise, it does not perform any processing.
[0098] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
Claims
1. A method for processing high-speed stored data based on EEPROM, characterized in that, Specifically, the following steps are included: The data is categorized based on its function, and the EEPROM is partitioned, with each partition storing a specific type of data. For each type of data, two caches are created: the first cache and the second cache. The data transmitted from the application layer is received and cached based on the first cache, and after the data is cached in the first cache, the cached data is written to the corresponding partition of the EEPROM. When the first buffer writes data to the EEPROM, it determines whether the data being written to the EEPROM has changed: If so, the data transmitted again by the application layer is written to the second buffer, and after the data previously in the first buffer is written to the EEPROM, the data in the second buffer is written to the first buffer. If not, no action will be taken.
2. The data processing method based on EEPORM high-speed storage as described in claim 1, characterized in that: The EEPROM also includes partition information; The partition information includes the current chip status, as well as the starting address and status of each partition.
3. The data processing method based on EEPORM high-speed storage as described in claim 2, characterized in that, For EEPORM: Create a first page of a preset size to store partition information; After the first page of space, the space is divided into equal partitions according to the set size, and each partition corresponds to storing one type of data.
4. The data processing method based on EEPORM high-speed storage as described in claim 1, characterized in that, The steps of receiving and caching data transmitted from the application layer based on the first cache, and writing all cached data to the corresponding partition of the EEPROM after the data caching in the first cache is completed, specifically include: The driver layer receives the data to be saved transmitted from the application layer, locks the first cache, and caches the received application layer data through the first cache. After the first cache completes the data caching, the driver layer writes the data in the first cache to the corresponding partition of the EEPROM based on the I2C bus.
5. The data processing method based on EEPORM high-speed storage as described in claim 1, characterized in that, After writing the data transmitted again from the application layer into the second buffer, and after the data previously in the first buffer has been written into the EEPROM, and after writing the data in the second buffer into the first buffer, the process also includes: The first buffer caches the data transmitted from the second buffer, and then writes the cached data into the corresponding partition of the EEPROM.
6. The data processing method based on EEPORM high-speed storage as described in claim 1, characterized in that, Both the first cache and the second cache include flag bits; The flag in the first cache is used to determine whether there is a task that writes data to EEPORM. The flag bit of the second cache is used to determine whether the data being written to the EEPROM has changed during the process of writing data to the EEPROM.
7. The data processing method based on EEPORM high-speed storage as described in claim 6, characterized in that: When there is no data being written to the EEPROM in the first cache, or when the previous data in the first cache has been written to the EEPROM and the data in the second cache has been written to the first cache, and then the data in the first cache is written to the EEPROM again, the flag of the first cache is set to 1. When the flag of the first buffer is set to 1, when the application layer transmits data again, regardless of the value of the flag of the second buffer, the flag of the second buffer will be set to 1.
8. The data processing method based on EEPORM high-speed storage as described in claim 7, characterized in that: Once the data cached in the first cache has been written to the EEPROM, the flag of the first cache is set to 0. After the data in the first cache is written to the EEPROM, and the data in the second cache is written to the first cache, the flag of the second cache is set to 0.
9. The data processing method based on EEPORM high-speed storage as described in claim 1, characterized in that, When different types of data need to be written to EEPROM continuously: When the current type of data is being written to the EEPROM from the corresponding first cache, the next type of data to be written is cached in the second cache corresponding to that type of data; Determine if there is still data to be written to EEPROM in the first cache corresponding to the current data type: If not, the next type of data to be written will be written from the corresponding second cache to the corresponding first cache, and then written to the corresponding partition of the EEPROM; If so, wait until all the data in the first cache corresponding to the current type of data is written to the EEPROM, and no more data is added to the first cache corresponding to the current type of data. Then, write the next type of data to be written from the corresponding second cache to the corresponding first cache, and then write it to the corresponding partition of the EEPROM.
10. A processing system for high-speed data storage based on EEPROM, characterized in that, include: The classification module is used to classify data based on data functions and partition the EEPROM, with each partition corresponding to a type of data. The module creates two caches for each type of data: a first cache and a second cache. The write module is used to receive and cache data transmitted from the application layer based on the first cache, and after the data is cached in the first cache, write all the cached data into the corresponding partition of the EEPROM. The judgment module is used to determine whether the data being written to the EEPROM has changed when the first buffer writes data to the EEPROM. If so, the data transmitted again by the application layer is written to the second buffer, and after the data previously in the first buffer is written to the EEPROM, the data in the second buffer is written to the first buffer. If not, no action will be taken.