Cache operation method and apparatus, and electronic device
By transferring missed or unlocked cache page data between the first-level cache and the second-level cache space and utilizing persistent memory, the problems of low cache hit rate and data loss are solved, achieving more efficient cache management and faster recovery.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- CHINA TELECOM CLOUD TECH CO LTD
- Filing Date
- 2025-11-20
- Publication Date
- 2026-06-11
AI Technical Summary
Existing caching mechanisms lack caches residing outside of physical memory, resulting in low cache hit rates and data loss after power failure in persistent memory, affecting recovery speed.
A combination of first-level and second-level cache spaces is used. Through a linked list management mechanism, cached pages that are missed or unlocked are transferred from the first-level cache to the second-level cache. Data is retained in persistent memory, and cache space usage is optimized by combining locking flags and data compaction threads.
It improved cache hit rate, expanded system cache space, maintained data integrity after power failure, and improved application recovery efficiency.
Smart Images
Figure CN2025136449_11062026_PF_FP_ABST
Abstract
Description
A cache operation method, apparatus, and electronic device
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411773112.0, filed on December 4, 2024, entitled "A method, apparatus and electronic device for caching operations", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of data storage technology, and in particular to a caching operation method, apparatus, and electronic device. Background Technology
[0004] Caching is a technique to improve data retrieval efficiency. For a long time, various caching mechanisms have processed data in memory. The emergence of persistent memory has changed the inherent memory architecture. Persistent memory has the characteristics of large capacity, persistence, byte addressing, low latency and high bandwidth. It allows data to be modified using regular read and write instructions, effectively absorbing the advantages of traditional memory and hard disks.
[0005] Due to memory space limitations, current caching mechanisms lack a cache residing outside physical memory, limiting the potential for further improvements in cache hit rate. Furthermore, the lack of memory page locking functionality means current caching algorithms cannot effectively select when to clear specific memory pages from the cache. This can lead to the replacement of critical or frequently accessed data, resulting in a lower cache hit rate and inefficient memory utilization. Finally, data is lost when memory is lost due to power failure, and application recovery still requires reading data from the hard drive upon power-up, slowing down recovery speed. Summary of the Invention
[0006] In view of the above problems, embodiments of this application provide a caching operation method, apparatus, and electronic device to overcome or at least partially solve the above problems.
[0007] In a first aspect, embodiments of this application provide a caching operation method applied to an electronic device, the electronic device including a primary cache space and a secondary cache space, the secondary cache space being persistent memory, the method including:
[0008] In response to a target read instruction, the target data corresponding to the target read instruction is queried in the first-level cache and the second-level cache.
[0009] If the target data is not present in either the Level 1 or Level 2 cache, the last page in the Least Recently Used cache page list of the Level 1 cache, which is not locked, is moved to the Level 2 cache. Similarly, the last page in the Least Recently Used cache page list of the Level 1 cache, which is not locked, is moved to the Level 2 cache. The cache pages in the Least Recently Used cache page list are ordered from shortest to longest cache miss duration, while the cache pages in the Least Frequently Used cache page list are ordered from highest to lowest read frequency.
[0010] Based on the target read instruction, the target data is read from the target external memory space corresponding to the first-level cache space into the first-level cache space.
[0011] In some embodiments of this application, the method further includes:
[0012] In response to the target locking instruction, a locking flag is added to the third cache page data corresponding to the target locking instruction in the least recently used cache page list and / or least frequently used cache page list to lock the third cache page data and obtain the locked third cache page data.
[0013] Upon receiving a target clear instruction corresponding to the locked third cache page data, the locked third cache page data is cleared from the first-level cache space in response to the target clear instruction.
[0014] In some embodiments of this application, the method further includes:
[0015] If the duration of the missing data of the locked third cache page is greater than or equal to the first preset duration, and the locked third cache page exists in the least recently used cache page list, the lock mark of the locked third cache page is deleted to unlock the locked third cache page and obtain the third cache page.
[0016] Within a second preset time period, if the access rate of the locked third cache page is less than the first threshold, and the locked third cache page data exists in the least frequently used cache page list, the locking flag of the locked third cache page data is deleted to unlock the locked third cache page data and obtain the third cache page data.
[0017] In some embodiments of this application, transferring the last-most-octaged first cache page data that does not contain a lock tag from the least recently used cache page list in the first-level cache space to the second-level cache space includes:
[0018] If the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to the first threshold, a cache data defragmentation thread and a write operation processing thread are created.
[0019] Based on the cache data cleanup thread, the data of the first cache page is transferred to multiple data block storage spaces, each 64 megabytes in size;
[0020] Based on the write operation processing thread, the data of the first cache page in the data block storage space is transferred to the second cache space.
[0021] In some embodiments of this application, the method further includes:
[0022] If the target data is contained in the first-level cache space, determine the first linked list where the target data is located;
[0023] If the first linked list is the least recently used cached page linked list, adjust the target data to the first position of the least recently used cached page linked list.
[0024] In some embodiments of this application, the method further includes:
[0025] If the first linked list is the least frequently used cache page linked list, increment the read frequency of the target data by one to update the read frequency of the target data and obtain the updated read frequency.
[0026] Based on the updated read frequency, the position of the target data in the least frequently used cache page list is redefined.
[0027] In some embodiments of this application, the method further includes:
[0028] Determine the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list;
[0029] If the first hit rate is greater than the second hit rate, the length of the least recently used cache page list is increased by a preset ratio.
[0030] If the first hit rate is less than the second hit rate, the length of the least frequently used cache page list is increased by a preset ratio.
[0031] If the first hit rate equals the second hit rate, the lengths of the least recently used cache page list and the least frequently used cache page list remain unchanged.
[0032] In some embodiments of this application, a portion of the memory space in the secondary cache is in application direct access mode, and the remaining memory space in the secondary cache is in memory mode. The method further includes:
[0033] Copy the data of the fourth cache page in the least frequently used cache page list, whose reading frequency is greater than or equal to the preset frequency, to the part of the memory space in the second-level cache space that is in the application's direct access mode.
[0034] After a power outage and subsequent power restoration in the secondary cache space, application recovery is performed based on the data in the fourth cache page of the memory space in the application direct access mode within the secondary cache space.
[0035] Secondly, embodiments of this application provide a caching operation apparatus applied to an electronic device. The electronic device includes a primary cache space and a secondary cache space, wherein the secondary cache space is persistent memory. The apparatus includes:
[0036] The query module is used to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction.
[0037] The transfer module is used to transfer the last cache page (without a lock tag) from the least recently used cache page list in the first-level cache space to the second-level cache space when the target data is not found in either the first-level or second-level cache space. Similarly, it transfers the last cache page (without a lock tag) from the least recently used cache page list in the first-level cache space to the second-level cache space. The cache pages in the least recently used cache page list are arranged in ascending order of cache miss duration, while the cache pages in the least frequently used cache page list are arranged in descending order of read frequency.
[0038] The read module is used to read target data from the target external storage space corresponding to the first-level cache space into the first-level cache space based on the target read instruction.
[0039] In some embodiments of this application, the apparatus further includes:
[0040] The locking module is used to add a locking flag to the third cache page data corresponding to the target locking command in the least recently used cache page list and / or least frequently used cache page list in response to the target locking command, so as to lock the third cache page data and obtain the locked third cache page data.
[0041] The clearing module is used to clear the locked third cache page data from the first-level cache space in response to the target clearing instruction received when a target clearing instruction is received for the locked third cache page data.
[0042] In some embodiments of this application, the apparatus further includes:
[0043] The first unlocking module is used to remove the lock flag of the locked third cache page data when the duration of the missed hit of the locked third cache page data is greater than or equal to the first preset duration, and the locked third cache page data exists in the least recently used cache page list, so as to unlock the locked third cache page data and obtain the third cache page data.
[0044] The second unlocking module is used to, within a second preset time period, if the access rate of the locked third cache page is less than a first threshold and the locked third cache page data exists in the least frequently used cache page list, delete the lock mark of the locked third cache page data to unlock the locked third cache page data and obtain the third cache page data.
[0045] In some embodiments of this application, the transfer module includes:
[0046] Create a submodule to create a cache data compaction thread and a write operation processing thread when the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to a first threshold.
[0047] The first transfer submodule is used to transfer the data of the first cache page to multiple data block storage spaces of 64 megabytes each, based on the cache data sorting thread;
[0048] The second transfer submodule is used to transfer the data of the first cache page in the data block storage space to the second cache space based on the write operation processing thread.
[0049] In some embodiments of this application, the apparatus further includes:
[0050] The first determining module is used to determine the first linked list where the target data is located when the target data is contained in the first-level cache space.
[0051] The adjustment module is used to adjust the target data to the head of the least recently used cached page list when the first list is the least recently used cached page list.
[0052] In some embodiments of this application, the apparatus further includes:
[0053] The frequency update module is used to increment the read frequency of the target data by one when the first linked list is the least frequently used cache page linked list, so as to update the read frequency of the target data and obtain the updated read frequency.
[0054] The second determination module is used to redetermine the position of the target data in the least frequently used cache page list based on the updated read frequency.
[0055] In some embodiments of this application, the apparatus further includes:
[0056] The third determination module is used to determine the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list;
[0057] The first addition module is used to increase the length of the least recently used cache page linked list by a preset ratio when the first hit rate is greater than the second hit rate.
[0058] The second addition module is used to increase the length of the least frequently used cache page list according to a preset ratio when the first hit rate is less than the second hit rate.
[0059] The maintenance module is used to keep the lengths of the least recently used cache page list and the least frequently used cache page list unchanged when the first hit rate equals the second hit rate.
[0060] In some embodiments of this application, a portion of the memory space in the secondary cache is in application direct access mode, and the remaining memory space in the secondary cache is in memory mode. The apparatus further includes:
[0061] The copy module is used to copy the data of the fourth cache page in the least frequently used cache page list, whose read frequency is greater than or equal to a preset frequency, to the part of the memory space in the second-level cache space that is in the application's direct access mode.
[0062] The recovery module is used to perform application recovery based on the fourth cache page data in the part of the memory space in the application direct access mode after the secondary cache space is powered off and then powered on again.
[0063] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement any of the above-mentioned caching operation methods.
[0064] The specific beneficial effects are as follows:
[0065] In this embodiment, in response to a target read instruction, the target data corresponding to the target read instruction is queried in both the first-level cache space and the second-level cache space. If neither the first-level cache space nor the second-level cache space contains the target data, the last page in the least recently used cache page list of the first-level cache space that does not contain a locking flag is transferred to the second-level cache space. Similarly, the last page in the least recently used cache page list of the first-level cache space that does not contain a locking flag is transferred to the second-level cache space. The cache page data in the least recently used cache page list is arranged in ascending order of cache miss duration, while the cache page data in the least frequently used cache page list is arranged in descending order of read frequency. Based on the target read instruction, the data is retrieved from the first-level cache space... In the target external storage space, the target data is read into the L1 cache space. Even if neither the L1 nor L2 cache space contains the target data to be read, the data of the first cache page (the last element of the least recently used cache page list without a lock tag) or the data of the second cache page (the last element of the least frequently used cache page list without a lock tag) can be moved from the L1 cache space to the L2 cache space. This greatly expands the system cache space and ensures that locked cache page data is not moved or evicted. This makes the data stored in the L1 and L2 cache spaces more in line with the actual needs of users, thereby improving the cache hit rate of the system cache. In addition, since the L2 cache space is persistent memory, the data in it still exists after power failure, which can improve the efficiency of application recovery. Attached Figure Description
[0066] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0067] Figure 1 is a flowchart illustrating a caching operation method provided in an embodiment of this application;
[0068] Figure 2 is a flowchart illustrating another caching operation method provided in an embodiment of this application;
[0069] Figure 3 is a flowchart illustrating a method for dynamically adjusting the length of the least recently used cache page list and the least frequently used cache page list according to an embodiment of this application.
[0070] Figure 4 is a logic block diagram of a cache operation device provided in an embodiment of this application;
[0071] Figure 5 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0072] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0073] Referring to Figure 1, which is a flowchart illustrating a caching operation method according to an embodiment of this application, applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, wherein the secondary cache space is persistent memory, and the method may include:
[0074] Step 101: In response to the target read instruction, query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space.
[0075] In the embodiments of this application, caching is a storage technology designed to improve data retrieval speed. It reduces data processing latency by providing a fast intermediate storage layer between the Central Processing Unit (CPU) and memory. The existence of caching greatly improves the performance of computer systems, especially in scenarios involving large amounts of data or complex computational tasks. The concept of caching is not limited to the hardware level; it also has wide applications at the software level, such as web browser caching and database query caching. The working principle of caching is based on a "space-for-time" strategy, that is, using faster but more expensive storage media such as Static Random-Access Memory (SRAM) to temporarily store data, thereby speeding up data access. When the CPU needs to read data, it will first try to retrieve it from the cache. If the required data exists in the cache (called a cache hit), it is read directly; if it does not exist (called a cache miss), the data needs to be read from slower main memory or other storage devices and loaded into the cache for later use.
[0076] In the embodiments of this application, if the current system receives a target read instruction initiated by a user, the system can respond to the instruction by querying the target data corresponding to the target read instruction in the system's first-level cache space and second-level cache space. The first-level cache space and the second-level cache space can together constitute the system cache of the system.
[0077] Step 102: If the target data is not present in either the Level 1 cache space or the Level 2 cache space, move the last-placed first cache page data (without a lock tag) from the Least Recently Used cache page list in the Level 1 cache space to the Level 2 cache space. Similarly, move the last-placed second cache page data (without a lock tag) from the Least Frequently Used cache page list in the Level 1 cache space to the Level 2 cache space. The cache pages in the Least Recently Used cache page list are arranged in ascending order of cache miss duration, while the cache pages in the Least Frequently Used cache page list are arranged in descending order of read frequency.
[0078] In the embodiments of this application, data in the cache can be stored in the cache in the form of data pages, referred to as cache pages. A linked list is a non-contiguous storage data structure composed of a series of nodes. Each node contains two parts: an element that stores data and a pointer to the next node. If the first-level cache space does not contain the target data, the cache page data in the first-level cache space needs to be updated so that the target data outside the first-level cache space can be read into the first-level cache space. The first-level cache space can include a least recently used cache page linked list and a least frequently used cache page linked list. The least recently used cache page linked list can include multiple cache page data, which can be arranged in ascending order of the duration of the cache miss. The least frequently used cache page linked list can include multiple cache page data, which can be arranged in descending order of the access frequency. The first-level cache space can be connected to a persistent memory space as a second-level cache space. This second-level cache space can be used to receive data evicted from the first-level cache space and can be directly read and accessed by the CPU. Therefore, the first-level cache space and the second-level cache space can together constitute the system cache. The first cache page data, which is at the end of the least recently used cache page list and does not contain a locking tag, can be moved to the second-level cache space corresponding to the first-level cache space. Similarly, the second cache page data, which is at the end of the least frequently used cache page list and does not contain a locking tag, can be moved to the second-level cache space corresponding to the first-level cache space. The source of the moved cache page data can be determined by the cache eviction algorithm of the first-level cache space. The locking tag is a method of locking cache page data; once a cache page has this locking tag added, it will remain stored in the first-level cache space and will not participate in the cache page data eviction process. In this way, the first-level cache space has a cache space to store the target data. Cache page data can be stored as pointers in the two linked lists mentioned above. When moving the first and second cache page data, the first and second cache page data can be located according to the pointers, and the first and second cache page data, along with their corresponding pointers, can be removed together. The pointers mentioned here refer to the elements storing data in the linked list, not pointers to the linked list itself used to point to other nodes. After the first and second cache page data are moved to the second-level cache space, they can be stored in the mirror least recently used cache page list and the mirror least frequently used cache page list in the second-level cache space. The mirror least recently used cache page list corresponds to the least recently used cache page list and is used to store cache page data that has been evicted from the least recently used cache page list. The mirror least frequently used cache page list corresponds to the least frequently used cache page list and is used to store cache page data that has been evicted from the least frequently used cache page list.
[0079] Step 103: Based on the target read instruction, read the target data from the target external storage space corresponding to the first-level cache space into the first-level cache space.
[0080] In the embodiments of this application, target data can be read from the target external storage space corresponding to the first-level cache space into the first-level cache space according to the target read instruction. After the target data is read into the first-level cache space, it can be stored in the form of data pages.
[0081] In the embodiments of this application, in response to a target read instruction, the target data corresponding to the target read instruction is queried in the first-level cache space and the second-level cache space. If the target data is not found in either the first-level cache space or the second-level cache space, the first cache page data that is at the end of the least recently used cache page list in the first-level cache space and does not contain a locking mark is transferred to the second-level cache space. Similarly, the second cache page data that is at the end of the least recently used cache page list in the first-level cache space and does not contain a locking mark is transferred to the second-level cache space. The cache page data in the least recently used cache page list are arranged in ascending order of cache miss duration; the cache page data in the least frequently used cache page list are arranged in descending order of read frequency. Based on the target read instruction, the target data is retrieved from the first-level cache space... In the corresponding target external storage space, the target data is read into the first-level cache space. Even if neither the first-level nor the second-level cache space contains the target data to be read, the data of the first cache page (the last element of the least recently used cache page list that does not contain a lock tag) or the data of the second cache page (the last element of the least frequently used cache page list that does not contain a lock tag) can be moved from the first-level cache space to the second-level cache space. This greatly expands the system cache space and ensures that locked cache page data is not moved or evicted. This makes the data stored in the first-level and second-level cache spaces more in line with the actual needs of users, thereby improving the cache hit rate of the system cache. In addition, since the second-level cache space is persistent memory, the data in it still exists after power failure, which can improve the efficiency of application recovery.
[0082] Referring to Figure 2, which is a flowchart illustrating another caching operation method provided in an embodiment of this application, applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, wherein the secondary cache space is persistent memory, and the method may include:
[0083] Step 201: In response to the target read instruction, query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space.
[0084] In the embodiments of this application, the implementation of this step can be referred to the embodiment of step 101, and will not be repeated here.
[0085] Step 202: If the target data is not present in either the Level 1 cache space or the Level 2 cache space, move the last-placed first cache page data without a lock tag from the Least Recently Used cache page list in the Level 1 cache space to the Level 2 cache space; or move the last-placed second cache page data without a lock tag from the Least Frequently Used cache page list in the Level 1 cache space to the Level 2 cache space. The cache page data in the Least Recently Used cache page list are arranged in ascending order of cache miss duration; the cache page data in the Least Frequently Used cache page list are arranged in descending order of read frequency.
[0086] In the embodiments of this application, the implementation of this step can be referred to the embodiment of step 102, and will not be repeated here.
[0087] In some embodiments of this application, step 202 may include the following sub-steps:
[0088] Sub-step 2021: If the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to the first threshold, create a cache data organization thread and a write operation processing thread.
[0089] In the embodiments of this application, a sequential read instruction can refer to a continuous data reading operation performed sequentially on a data storage device, where the initial storage addresses of these data are contiguous. If the target read instruction is a sequential read instruction, and the amount of data in the first cache page is greater than or equal to a first threshold, a cache data defragmentation thread and a write operation processing thread can be created to quickly write the data in the first cache page into the secondary cache space.
[0090] Sub-step 2022 involves transferring the data from the first cache page to multiple data block storage spaces, each 64 megabytes in size, based on the cache data reorganization thread.
[0091] In the embodiments of this application, the cache data defragmentation thread can first create multiple data block storage spaces of 64 megabytes (MB) in the first-level cache space. Then, according to the cache data defragmentation thread, the first cache page data can be transferred to the above-mentioned data block storage space. If the first data block storage space is full, the remaining part of the first cache page data can be stored in the second data block storage space, and so on.
[0092] Sub-step 2023, based on the write operation processing thread, transfers the data of the first cache page in the data block storage space to the second-level cache space.
[0093] In the embodiments of this application, the first cache page data stored in the data block storage space of the first-level cache space can be transferred to the second-level cache space according to the write operation processing thread.
[0094] In the embodiments of this application, when the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to a first threshold, a cache data defragmentation thread and a write operation processing thread are created. Based on the cache data defragmentation thread, the data in the first cache page is transferred to multiple data block storage spaces of 64 megabytes each. Based on the write operation processing thread, the data in the first cache page in the data block storage space is transferred to the second-level cache space. The cache data defragmentation thread and the write operation processing thread can be used to handle data transfer tasks with large amounts of data, which improves the efficiency of cache data transfer to a certain extent.
[0095] Step 203: Based on the target read instruction, read the target data from the target external storage space corresponding to the first-level cache space into the first-level cache space.
[0096] In the embodiments of this application, the implementation of this step can be referred to the embodiment of step 104, and will not be repeated here.
[0097] Step 204: If the target data is contained in the first-level cache space, determine the first linked list where the target data is located.
[0098] In the embodiments of this application, if the first-level cache space contains target data, the first linked list where the target data is located can be determined. The first linked list can be one of the most recently used cache page linked list, the least recently used cache page linked list, the most frequently used cache page linked list, and the least frequently used cache page linked list.
[0099] Step 205: If the first linked list is the least recently used cache page linked list, adjust the target data to the first position of the least recently used cache page linked list.
[0100] In the embodiments of this application, if the first linked list is the least recently used cache page linked list, the position of the target data can be adjusted to the first position in the least recently used cache page linked list.
[0101] In the embodiments of this application, when the target data is contained in the first-level cache space, the first linked list where the target data is located is determined. When the first linked list is the least recently used cache page linked list, the target data is adjusted to the first position of the least recently used cache page linked list. When the data in the least recently used cache page linked list is hit, the position of the hit target data in the least recently used cache page linked list can be changed, which can extend the time when the data is evicted, making the data in the system cache more in line with the actual usage needs of users, and improving the cache hit rate of the system cache to a certain extent.
[0102] Step 206: If the first linked list is the least frequently used cache page linked list, increment the read frequency of the target data by one to update the read frequency of the target data and obtain the updated read frequency.
[0103] In the embodiments of this application, if the first linked list is the least frequently used cache page linked list, the read frequency of the target data can be incremented by one to update the read frequency of the target data, thereby obtaining the updated read frequency of the target data.
[0104] In embodiments of this application, another method for updating the read frequency can exist: the read frequency of the target data can be calculated based on the time interval between the two most recent read times. This allows the data in the cache to be more closely aligned with the user's recent usage needs, which can improve the cache hit rate of the system cache to some extent.
[0105] Step 207: Based on the updated read frequency, redetermine the position of the target data in the least frequently used cache page list.
[0106] In the embodiments of this application, after obtaining the read frequency of the updated target data, the position of the target data in the least frequently used cache page list can be re-determined based on the updated read frequency.
[0107] In the embodiments of this application, when the first linked list is the least frequently used cache page linked list, the read frequency of the target data is incremented by one to update the read frequency of the target data, and the updated read frequency is obtained. Based on the updated read frequency, the position of the target data in the least frequently used cache page linked list is re-determined. This allows updating the position of the target data in the least recently used cache page linked list when the target data is already in the least recently used cache page linked list. This can extend the time before the most recently hit target data is cleared from the first-level cache space, thereby ensuring that the data in the cache matches the user's usage needs and improving the cache hit rate of the first-level cache space to some extent.
[0108] Step 208: In response to the target locking instruction, add a locking flag to the third cache page data corresponding to the target locking instruction in the least recently used cache page list and / or least frequently used cache page list to lock the third cache page data and obtain the locked third cache page data.
[0109] In the embodiments of this application, upon receiving a target locking instruction for cached page data, the system can, in response to the instruction, determine the third cached page data corresponding to the target locking instruction from the least recently used cached page list and / or the least frequently used cached page list. The third cached page data can be the cached page data that the target locking instruction wants to lock. After finding the third cached page data, it can be locked, thereby obtaining the locked third cached page data. The locked third cached page data can be actively cleared by the user and is not subject to cache data eviction algorithms. If the user does not actively clear it, the locked third cached page data can be stored in the first-level cache space for a long time. It should be noted that this step can be implemented regardless of whether the first-level or second-level cache space contains the target data, or whether neither the first-level nor second-level cache space contains the target data.
[0110] Step 209: Upon receiving a target clear instruction corresponding to the locked third cache page data, in response to the target clear instruction, the locked third cache page data is cleared from the first-level cache space.
[0111] In the embodiments of this application, upon receiving a target clear instruction corresponding to the locked third cache page data, the locked third cache page data can be cleared from the first-level cache space in response to the target clear instruction. After clearing, the first-level cache space no longer contains the locked third cache page data, nor does it contain any third cache page data. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0112] In the embodiments of this application, in response to a target locking instruction, a locking flag is added to the third cache page data corresponding to the target locking instruction in the least recently used cache page list and / or the least frequently used cache page list to lock the third cache page data, thus obtaining the locked third cache page data. Upon receiving a target clear instruction corresponding to the locked third cache page data, in response to the target clear instruction, the locked third cache page data is cleared from the first-level cache space. This can lock the cache page data in the least recently used cache page list and / or the least frequently used cache page list in the first-level cache space, thereby preventing the locked cache page data from being evicted by the eviction algorithm. At the same time, the locked cache page data can also be actively cleared through the target clear instruction, which can make the data in the first-level cache space more in line with the user's usage habits and improve the cache hit rate of the first-level cache space to a certain extent.
[0113] Step 210: If the duration of the missed cache page data is greater than or equal to the first preset duration, and the locked cache page data exists in the least recently used cache page list, unlock the locked cache page data to obtain the third cache page data.
[0114] In the embodiments of this application, if the duration of the missed cache entry for the locked third cache page data is greater than or equal to a first preset duration, the third cache page data can be unlocked, thereby obtaining the third cache page data. The duration of the missed cache entry for the locked third cache page data can either be the original missed cache entry duration of the third cache page data itself, or it can be recalculated when the locked third cache page data is obtained. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0115] Step 211: Within the second preset time period, if the access rate of the locked third cache page is less than the first threshold and the locked third cache page data exists in the least frequently used cache page list, the locked third cache page data is unlocked to obtain the third cache page data.
[0116] In the embodiments of this application, if the access rate of the locked third cache page data is less than the first threshold within the second preset time period, and the locked third cache page data exists in the least frequently used cache page list, then the locked third cache page data can be unlocked, thereby obtaining the third cache page data. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0117] In the embodiments of this application, if the duration of the missed cache page data is greater than or equal to a first preset duration and the locked third cache page data exists in the least recently used cache page list, the lock mark of the locked third cache page data is deleted to unlock the locked third cache page data and obtain the third cache page data. If, within a second preset duration, the access rate of the locked third cache page is less than a first threshold and the locked third cache page data exists in the least recently used cache page list, the lock mark of the locked third cache page data is deleted to unlock the locked third cache page data and obtain the third cache page data. The locked third cache page data can be unlocked when the preset conditions are met, so that the unlocked third cache page data can participate in the normal data eviction process of the cache space. To a certain extent, this can avoid users accidentally locking the cache, improve the activity of data in the system cache, and thus improve the cache hit rate of the system cache to a certain extent.
[0118] Step 212: Copy the data of the fourth cache page in the least frequently used cache page list, whose reading frequency is greater than or equal to the preset frequency, to the part of the memory space in the second-level cache space that is in the application direct access mode.
[0119] In the embodiments of this application, within the secondary cache space, a portion of the memory space can be set to application direct access mode, and the remaining memory space can be set to memory mode (e.g., 5% of the space is in application direct access mode, and 95% of the space is in memory mode). Cache page data from the least frequently used cache page list, whose read frequency is greater than or equal to a preset frequency, can be copied to the portion of the secondary cache space in application direct access mode. It should be noted that this step can be implemented regardless of whether the primary or secondary cache space contains the target data, or whether neither the primary nor secondary cache space contains the target data.
[0120] Step 213: After the secondary cache space is powered off and then powered on again, the application is restored based on the fourth cache page data in the part of the memory space in the application direct access mode of the secondary cache space.
[0121] In the embodiments of this application, data in the portion of memory space in application direct access mode can be directly read by the CPU, eliminating the need for pre-loading into the L1 cache. If the L2 cache experiences a power outage and subsequent power restoration, application recovery can be performed based on the fourth cache page data in the portion of memory space in application direct access mode within the L2 cache. The recovered application corresponds to the fourth cache page data. It should be noted that this step can be implemented regardless of whether the L1 or L2 cache contains the target data, or whether neither the L1 nor L2 cache contains the target data.
[0122] In the embodiments of this application, by copying cache page data with a read frequency greater than or equal to a preset frequency from the least frequently used cache page list to a portion of the memory space in the application direct access mode of the secondary cache space, after the secondary cache space is powered off and then powered on again, application recovery is performed based on the fourth cache page data in the portion of the memory space in the application direct access mode of the secondary cache space. This allows cache page data that meets the conditions to be copied to the memory space in the application direct access mode of the secondary cache space, so that users can quickly load the cache page data after a power outage and restart, which can improve the convenience and availability of the secondary cache space to a certain extent.
[0123] Based on the above embodiments, referring to Figure 3, which is a flowchart illustrating a method for dynamically adjusting the length of the least recently used cache page list and the least frequently used cache page list according to an embodiment of this application, after step 203, the method may further include:
[0124] Step 301: Determine the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list.
[0125] In the embodiments of this application, the ratio of the number of times data in the least recently used cache page list is hit to the total amount of data in that list can be used as the first hit rate for the least recently used cache page list. The ratio of the number of times data in the least frequently used cache page list is hit to the total amount of data in that list can be used as the second hit rate for the least frequently used cache page list. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0126] Step 302: If the first hit rate is greater than the second hit rate, increase the length of the least recently used cache page linked list according to a preset ratio.
[0127] In the embodiments of this application, a percentage increase in the linked list length can be set. If the first hit rate is greater than the second hit rate, the length of the least recently used cache page linked list can be increased by a preset percentage. For example, if the original length of the least recently used cache page linked list is 100, and the preset percentage is 10%, the length of the least recently used cache page linked list can be increased to 110. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0128] Step 303: If the first hit rate is less than the second hit rate, increase the length of the least frequently used cache page list according to a preset ratio.
[0129] In the embodiments of this application, if the first hit rate is less than the second hit rate, the length of the least frequently used cache page list can be increased by a preset ratio. For example, if the original length of the least frequently used cache page list is 100 and the preset ratio is 10%, the length of the least frequently used cache page list can be increased to 110. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether the target data is not contained in either the first-level cache space or the second-level cache space.
[0130] Step 304: If the first hit rate equals the second hit rate, keep the lengths of the least recently used cache page list and the least frequently used cache page list unchanged.
[0131] In the embodiments of this application, if the first hit rate equals the second hit rate, the lengths of the least recently used cache page list and the least frequently used cache page list can be kept unchanged. It should be noted that this step can be implemented regardless of whether the target data is contained in the first-level cache space or the second-level cache space, or whether neither the first-level cache space nor the second-level cache space contains the target data.
[0132] In the embodiments of this application, by determining the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list, if the first hit rate is greater than the second hit rate, the length of the least recently used cache page list is increased by a preset ratio; if the first hit rate is less than the second hit rate, the length of the least frequently used cache page list is increased by a preset ratio; if the first hit rate is equal to the second hit rate, the lengths of the least recently used cache page list and the least frequently used cache page list remain unchanged. This allows for dynamic adjustment of the length of the least recently used cache page list or the least frequently used cache page list when the first hit rate and the second hit rate are not equal. This makes the data in the first-level cache space more consistent with user habits, and to some extent, improves the cache hit rate and cache space utilization of the first-level cache space.
[0133] Referring to Figure 4, which is a logic block diagram of a caching operation device provided in an embodiment of this application, applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, the secondary cache space being persistent memory, and the device 400 may include:
[0134] The query module 401 is used to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction.
[0135] The transfer module 402 is used to transfer the last-placed first cache page data without a locking flag from the least recently used cache page list in the first-level cache space to the second-level cache space when neither the first-level cache space nor the second-level cache space contains the target data; or, to transfer the last-placed second cache page data without a locking flag from the least recently used cache page list in the first-level cache space. The cache page data in the least recently used cache page list are arranged in ascending order of cache miss duration; the cache page data in the least recently used cache page list are arranged in descending order of read frequency.
[0136] The read module 403 is used to read target data from the target external storage space corresponding to the first-level cache space into the first-level cache space based on the target read instruction.
[0137] In some embodiments of this application, the device 400 further includes:
[0138] The locking module is used to add a locking flag to the third cache page data corresponding to the target locking command in the least recently used cache page list and / or least frequently used cache page list in response to the target locking command, so as to lock the third cache page data and obtain the locked third cache page data.
[0139] The clearing module is used to clear the locked third cache page data from the first-level cache space in response to the target clearing instruction received when a target clearing instruction is received for the locked third cache page data.
[0140] In some embodiments of this application, the device 400 further includes:
[0141] The first unlocking module is used to remove the lock mark of the locked third cache page data when the duration of the missed hit of the locked third cache page data is greater than or equal to the first preset duration, so as to unlock the locked third cache page data and obtain the third cache page data.
[0142] The second unlocking module is used to remove the lock mark of the locked third cache page data within a second preset time period and when the access rate of the locked third cache page is less than a first threshold, so as to unlock the locked third cache page data and obtain the third cache page data.
[0143] In some embodiments of this application, the transfer module 402 includes:
[0144] Create a submodule to create a cache data compaction thread and a write operation processing thread when the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to a first threshold.
[0145] The first transfer submodule is used to transfer the data of the first cache page to multiple data block storage spaces of 64 megabytes each, based on the cache data sorting thread;
[0146] The second transfer submodule is used to transfer the data of the first cache page in the data block storage space to the second cache space based on the write operation processing thread.
[0147] In some embodiments of this application, the device 400 further includes:
[0148] The first determining module is used to determine the first linked list where the target data is located when the target data is contained in the first-level cache space.
[0149] The adjustment module is used to adjust the target data to the head of the least recently used cached page list when the first list is the least recently used cached page list.
[0150] In some embodiments of this application, the device 400 further includes:
[0151] The frequency update module is used to increment the read frequency of the target data by one when the first linked list is the least frequently used cache page linked list, so as to update the read frequency of the target data and obtain the updated read frequency.
[0152] The second determination module is used to redetermine the position of the target data in the least frequently used cache page list based on the updated read frequency.
[0153] In some embodiments of this application, the device 400 further includes:
[0154] The third determination module is used to determine the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list;
[0155] The first addition module is used to increase the length of the least recently used cache page linked list by a preset ratio when the first hit rate is greater than the second hit rate.
[0156] The second addition module is used to increase the length of the least frequently used cache page list according to a preset ratio when the first hit rate is less than the second hit rate.
[0157] The maintenance module is used to keep the lengths of the least recently used cache page list and the least frequently used cache page list unchanged when the first hit rate equals the second hit rate.
[0158] In some embodiments of this application, a portion of the memory space in the secondary cache is in application direct access mode, and the remaining memory space in the secondary cache is in memory mode. The device 400 further includes:
[0159] The copy module is used to copy the data of the fourth cache page in the least frequently used cache page list, whose read frequency is greater than or equal to a preset frequency, to the part of the memory space in the second-level cache space that is in the application's direct access mode.
[0160] The recovery module is used to perform application recovery based on the fourth cache page data in the part of the memory space in the application direct access mode after the secondary cache space is powered off and then powered on again.
[0161] The caching device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a GPUBOX (a high-performance computing device integrating multiple GPUs (Graphics Processing Units),) a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the specific type of device.
[0162] The caching device in this application embodiment can be a device with an operating system. This operating system can be Android, Linux, Windows, or other possible operating systems; this application embodiment does not specifically limit it.
[0163] The cache operation device provided in this application embodiment can implement the various processes implemented in the method embodiments of Figures 1 to 3. To avoid repetition, it will not be described again here.
[0164] This application provides an electronic device. Referring to FIG5, the electronic device 50 includes: a processor 501, a memory 502, and a computer program 5021 stored in the memory 502 and executable on the processor 501. When the processor 501 executes the program, it implements the cache operation method of the aforementioned embodiment.
[0165] This application also provides a computer program product that, when run on an electronic device, causes the processor to execute the steps in the cache operation method disclosed in this application.
[0166] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0167] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus, electronic devices, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal equipment to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal equipment, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.
[0168] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.
[0169] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable terminal equipment, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.
[0170] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0171] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.
[0172] The above provides a detailed description of a caching operation method provided by this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A caching operation method, characterized in that, Applied to an electronic device, the electronic device including a primary cache space and a secondary cache space, wherein the secondary cache space is persistent memory, the method includes: In response to a target read instruction, the target data corresponding to the target read instruction is queried in the first-level cache space and the second-level cache space; If the target data is not present in either the first-level cache space or the second-level cache space, the first cache page data, which is at the end of the least recently used cache page list in the first-level cache space and does not contain a locking flag, is transferred to the second-level cache space. Similarly, the second cache page data, which is at the end of the least frequently used cache page list in the first-level cache space and does not contain a locking flag, is transferred to the second-level cache space. The cache page data in the least recently used cache page list are arranged in ascending order of cache miss duration; the cache page data in the least frequently used cache page list are arranged in descending order of read frequency. Based on the target read instruction, the target data is read from the target external storage space corresponding to the first-level cache space into the first-level cache space.
2. The method according to claim 1, characterized in that, The method further includes: If the target data is contained in the first-level cache space, determine the first linked list where the target data is located; If the first linked list is the least recently used cache page linked list, the target data is adjusted to the first position of the least recently used cache page linked list.
3. The method according to claim 2, characterized in that, The method further includes: If the first linked list is the least frequently used cache page linked list, the read frequency of the target data is incremented by one to update the read frequency of the target data, and the updated read frequency is obtained. Based on the updated read frequency, the position of the target data in the least frequently used cache page list is re-determined.
4. The method according to claim 1 or 2, characterized in that, The method further includes: In response to the target locking instruction, a locking flag is added to the third cache page data corresponding to the target locking instruction in the least recently used cache page list and / or the least frequently used cache page list to lock the third cache page data, thereby obtaining the locked third cache page data; Upon receiving a target clear instruction corresponding to the locked third cache page data, the locked third cache page data is cleared from the first-level cache space in response to the target clear instruction.
5. The method according to claim 4, characterized in that, The method further includes: If the duration of the missed cache page data is greater than or equal to a first preset duration, and the locked cache page data exists in the least recently used cache page list, the locked cache page data is unlocked to obtain the third cache page data. If, within a second preset time period, the access rate of the locked third cache page data is less than a first threshold, and the locked third cache page data exists in the least frequently used cache page list, the locked third cache page data is unlocked to obtain the third cache page data.
6. The method according to claim 1, characterized in that, The step of transferring the last-most-octaged first cache page data (without a lock tag) from the least recently used cache page list in the first-level cache space to the second-level cache space includes: If the target read instruction is a sequential read instruction and the amount of data in the first cache page is greater than or equal to the first threshold, a cache data defragmentation thread and a write operation processing thread are created. Based on the cache data cleanup thread, the data of the first cache page is transferred to multiple data block storage spaces, each with a size of 64 megabytes. Based on the write operation processing thread, the data of the first cache page in the data block storage space is transferred to the second-level cache space.
7. The method according to claim 1 or 2, characterized in that, The method further includes: Determine the first hit rate of the least recently used cache page list and the second hit rate of the least frequently used cache page list; If the first hit rate is greater than the second hit rate, the length of the least recently used cache page list is increased by a preset ratio; If the first hit rate is less than the second hit rate, the length of the least frequently used cache page list is increased according to the preset ratio; If the first hit rate is equal to the second hit rate, the lengths of the least recently used cache page list and the least frequently used cache page list remain unchanged.
8. The method according to claim 1 or 2, characterized in that, The method further includes: a portion of the secondary cache memory is in application direct access mode, and the remaining memory space of the secondary cache is in memory mode. The data of the fourth cache page in the least frequently used cache page list, whose reading frequency is greater than or equal to a preset frequency, is copied to the second-level cache space, which is located in the memory space of the application's direct access mode. After the secondary cache space is powered off and then powered on again, application recovery is performed based on the fourth cache page data in the portion of memory space in the secondary cache space that is in the application direct access mode.
9. A cache operation device, characterized in that, Applied to an electronic device, the electronic device including a primary cache space and a secondary cache space, the secondary cache space being persistent memory, the device comprising: The query module is used to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction; The transfer module is configured to, when the target data is not present in either the first-level cache space or the second-level cache space, transfer the last-placed first cache page data (without a lock flag) from the least recently used cache page list of the first-level cache space to the second-level cache space, or transfer the last-placed second cache page data (without a lock flag) from the least frequently used cache page list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page list are arranged in ascending order of cache miss duration; and the cache page data in the least frequently used cache page list are arranged in descending order of read frequency. The read module is used to read the target data from the target external storage space corresponding to the first-level cache space into the first-level cache space based on the target read instruction.
10. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the cache operation method according to any one of claims 1 to 8.