Method for upgrading a jtag device and computing device

Abstract

The embodiment of the application provides a kind of JTAG equipment upgrade method and computing device, it is related to computing device technical field, can improve the generality of JTAG equipment upgrade scheme.The method comprises the following steps: the upper JTAG device sends JTAG channel switching information and first update information to the JTAG device of this level by communication bus;First update information is used to upgrade target secondary JTAG device;Target secondary JTAG device is one of one or more secondary JTAG devices;The JTAG channel connected by target JTAG bus between the target secondary JTAG device and the JTAG device of this level is enabled in response to JTAG channel switching information by the JTAG device of this level;The JTAG device of this level sends first update information to target secondary JTAG device by target JTAG bus, to upgrade target secondary JTAG device.The embodiment of the application can be used in the maintenance process of computing device.

Description

Technical Field

[0001] This application relates to the field of computing device technology, and in particular to a method for upgrading a JTAG device and a computing device. Background Technology

[0002] Typically, computing devices comprise multiple components, each equipped with a Joint Testing Group (JTAG) device (which can be a logic device). These multiple JTAG devices within a computing device require periodic upgrades. With the rapid iteration of computing devices, they are evolving towards modularity, with different motherboards, backplanes, daughter cards, and other components flexibly combined and interconnected. This has led to increasingly complex topologies for JTAG devices and longer links between them, posing challenges to JTAG device upgrades.

[0003] One design scheme for upgrading JTAG devices is to connect all JTAG devices to the complex programmable logic device (CPLD) on the motherboard, so that all JTAG devices form a daisy-chain topology through the CPLD on the motherboard. Based on this topology, the CPLD on the motherboard controls all JTAG devices to perform upgrades based on logic.

[0004] However, the above solution requires reserving a JTAG bus connector on the motherboard for each JTAG device, which increases the motherboard's design cost. More importantly, if the topology of the JTAG devices changes (e.g., when adding or removing JTAG devices), the control logic of the motherboard's CPLD needs to be modified or upgraded. Therefore, the above solution has low versatility and makes upgrading JTAG devices quite complex. Summary of the Invention

[0005] This application provides a method for upgrading a JTAG device and a computing device, which can improve the versatility of JTAG device upgrade solutions.

[0006] In a first aspect, embodiments of this application provide a method for upgrading a JTAG device, applied to a computing device, the computing device including a local JTAG device, a higher-level JTAG device, and one or more secondary JTAG devices; the higher-level JTAG device is connected to the local JTAG device via a communication bus and a JTAG bus; the local JTAG device is connected to each of the one or more secondary JTAG devices via a communication bus and a JTAG bus; the method includes: the higher-level JTAG device sending a JTAG upgrade message to the local JTAG device via the communication bus. The JTAG channel switching information and first update information are provided. The first update information is used to upgrade the target secondary JTAG device. The target secondary JTAG device is one of the one or more secondary JTAG devices. In response to the JTAG channel switching information, the local JTAG device enables the JTAG channel connected to the target secondary JTAG device via the target JTAG bus. The local JTAG device sends the first update information to the target secondary JTAG device via the target JTAG bus to upgrade the target secondary JTAG device.

[0007] The JTAG device upgrade method provided in this application embodiment allows the upper-level JTAG device of the computing device to send JTAG channel switching information to its own level JTAG device when an upgrade of a JTAG device (e.g., a target secondary JTAG device) is required. This enables the JTAG channel between the own level JTAG device and the target secondary JTAG device, connected via a target JTAG bus, allowing the own level JTAG device to upgrade the target secondary JTAG device through the target JTAG bus. The JTAG devices in this application embodiment present a multi-level master-slave structure, with each JTAG device connected to its superior JTAG device. Compared to existing computing methods, this eliminates the need for numerous connectors on the motherboard to connect each JTAG device, reducing motherboard design costs and ensuring the versatility of the JTAG device upgrade solution. Furthermore, this multi-level master-slave structure provides a clear topology, making topology updates easier. Only the topology on the changed branches needs modification, without affecting other branches, further improving the versatility of the JTAG device upgrade solution and reducing the difficulty of upgrading JTAG devices.

[0008] In one possible implementation, the local JTAG device is provided with a register, the register including a JTAG switching bit; the local JTAG device, in response to the JTAG channel switching information, enables a JTAG channel connected to the target secondary JTAG device via a target JTAG bus, including: based on the JTAG channel switching information, the local JTAG device modifies the JTAG switching bit to enable the JTAG channel connected to the target secondary JTAG device via a target JTAG bus.

[0009] In another possible implementation, the upper-level JTAG device is equipped with a register, which includes a communication channel switching bit. Before the upper-level JTAG device sends JTAG channel switching information and first update information to the local JTAG device via the communication bus, the method further includes: the upper-level JTAG device acquiring the communication channel switching information; and based on the communication channel switching information, the upper-level JTAG device modifying the communication bus switching bit to enable the communication channel between the upper-level JTAG device and the local JTAG device connected via the communication bus. It can be seen that the above register definition effectively displays the location information (level and channel) of a JTAG device in the JTAG topology diagram, facilitating location during the upgrade process. In addition, the register also includes an indicator bit for channel switching. Combined with the location information of the JTAG device in the JTAG topology diagram, the computing device can perform point-to-point upgrades of the JTAG device, ensuring the accuracy and stability of the JTAG upgrade scheme.

[0010] In another possible implementation, the register further includes: a channel indicator bit, a hierarchy indicator bit, and a downstream device indicator bit; the channel indicator bit is used to indicate the channel between a JTAG device and its parent JTAG device; the channel includes a communication channel and / or a JTAG channel; the hierarchy indicator bit is used to indicate the hierarchy of a JTAG device in the JTAG topology; the JTAG topology is used to indicate the connection relationship between the parent JTAG device, the current JTAG device, and the one or more secondary JTAG devices; the downstream device indicator bit is used to indicate the number of downstream JTAG devices of a JTAG device.

[0011] In another possible implementation, the computing device further includes: a main control unit; when the upper-level JTAG device is at the first level in the JTAG topology, the main control unit and the upper-level JTAG device are connected via a communication bus and a JTAG bus; the method further includes: the main control unit sending the communication channel switching information to the upper-level JTAG device via the communication bus based on the JTAG topology; and sending the JTAG channel switching information and the first update information to the upper-level JTAG device via the communication bus.

[0012] In another possible implementation, the method further includes: when the JTAG device in the computing device changes, the main control unit updates the JTAG topology map according to the channel indicator bit, hierarchy indicator bit, and downstream device indicator bit in the register of the JTAG device in the computing device. It is understood that JTAG links may change in real-world scenarios, such as the addition or deletion of JTAG devices. To ensure the normal operation and upgrade of JTAG links, this embodiment of the application can achieve autonomous updating of the JTAG topology map without excessive manual intervention.

[0013] In another possible implementation, the method further includes: the master control unit sending second update information to the upper-level JTAG device via the JTAG bus; the second update information is used to upgrade the upper-level JTAG device.

[0014] In another possible implementation, the main control unit is a central processing unit (CPU) or a baseboard management controller (BMC).

[0015] In another possible implementation, the communication bus is an I2C bus.

[0016] Secondly, embodiments of this application provide a computing device, which includes a processor and a memory; the memory stores instructions executable by the processor; when the processor is configured to execute the instructions, the computing device implements the method described in the first aspect.

[0017] Thirdly, embodiments of this application provide a computer-readable storage medium comprising: computer software instructions; when the computer software instructions are executed in a computing device, they cause the computing device to implement the method described in the first aspect.

[0018] Fourthly, embodiments of this application provide a computer program product that, when run on a computer, causes the computer to execute the steps of the related method described in the first aspect above, so as to implement the method of the first aspect above.

[0019] The beneficial effects of the second to fourth aspects mentioned above can be referred to the corresponding description of the first aspect, and will not be repeated here. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the composition of a computing device provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram illustrating the composition of a component provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram illustrating the composition of another computing device provided in an embodiment of this application;

[0023] Figure 4 A flowchart illustrating a method for upgrading a JTAG device provided in an embodiment of this application;

[0024] Figure 5 A flowchart illustrating another method for upgrading a JTAG device provided in this application embodiment;

[0025] Figure 6 A flowchart illustrating another method for upgrading a JTAG device provided in this application embodiment;

[0026] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] It should be noted that in the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0029] To facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish the same or similar items with essentially the same function and effect. Those skilled in the art can understand that the terms "first" and "second" are not intended to limit the quantity or execution order.

[0030] First, some background information related to the embodiments of this application will be explained.

[0031] JTAG is an international standard testing protocol. Computing devices equipped with JTAG interfaces can be called JTAG devices if they can connect to the JTAG bus via these interfaces. A JTAG link refers to connecting different JTAG devices (such as motherboard CPLDs, backplane CPLDs, etc.) within a computing device using the JTAG bus. This facilitates testing of JTAG devices and their peripheral circuits, thereby improving the controllability and observability of components within the computing device. With the rapid iteration of computing device products, computing devices are becoming increasingly modular, with different motherboards, backplanes, daughter cards, and other components being flexibly combined and interconnected. This makes the topology of JTAG links in computing devices increasingly complex and the links increasingly long. Upgrading the firmware of numerous JTAG devices while ensuring the stability of the upgrades presents a significant challenge.

[0032] Currently, there is a scheme that uses discrete switching devices to daisy-chain JTAG devices for upgrades. Specifically, JTAG devices of the same type are grouped into sets, and then discrete switching devices are used to daisy-chain different types of sets together, converging at a master control device. The master control device controls the switching states of the discrete switching devices, allowing them to switch to different JTAG devices, thus establishing connections between the master control device and different JTAG devices for upgrades. This scheme has the following drawbacks: when there are many JTAG devices, there are also many link branches between the master control device and the JTAG devices, resulting in excessively long links that affect signal transmission quality and cannot guarantee upgrade stability. Furthermore, the use of numerous discrete switching devices increases costs. Additionally, the need for additional discrete switching devices places high demands on the design of the circuit boards housing the JTAG devices, leading to poor versatility of this scheme.

[0033] To reduce the cost of using discrete switching devices, a solution using a CPLD (Content-Based Logic Controller) exists. Specifically, all JTAG devices are aggregated onto the motherboard CPLD via a JTAG bus, forming a daisy-chain topology. Based on this topology, the motherboard CPLD uses logic to upgrade all JTAG devices. While this solution reduces the use of discrete switching devices, it has several drawbacks: all JTAG devices must connect to the motherboard CPLD via the JTAG bus, requiring more connectors on the motherboard, increasing layout requirements and design costs. Furthermore, since the daisy-chaining of different JTAG devices is implemented through the motherboard CPLD's logic, information such as the number, type, and topology of JTAG devices needs to be extracted and written to the CPLD. If the JTAG link changes, such as adding or removing JTAG devices, the motherboard CPLD logic must be modified and upgraded, resulting in poor versatility and complex JTAG device upgrades.

[0034] In conclusion, there is an urgent need for a highly versatile upgrade solution for JTAG devices.

[0035] Against this background, embodiments of this application provide a method for upgrading a JTAG device. The computing device used in this method includes a local JTAG device, a higher-level JTAG device, and one or more secondary JTAG devices. The higher-level JTAG device is connected to the local JTAG device via a communication bus and a JTAG bus. The local JTAG device is connected to each of the one or more secondary JTAG devices via a communication bus and a JTAG bus. When an upgrade is required for a JTAG device (e.g., referred to as the target secondary JTAG device), the parent JTAG device sends JTAG channel switching information and first update information to the local JTAG device via the communication bus. The first update information is used to upgrade the target secondary JTAG device. The target secondary JTAG device is one of one or more secondary JTAG devices. In response to the JTAG channel switching information, the local JTAG device enables the JTAG channel connected to the target secondary JTAG device via the target JTAG bus. The local JTAG device sends the first update information to the target secondary JTAG device via the target JTAG bus to upgrade the target secondary JTAG device.

[0036] It should be noted that the terms "upper-level," "current-level," and "secondary-level" are relative concepts. From the perspective of any JTAG device in the computing device, this JTAG device can be called the current-level JTAG device. In terms of connection, a JTAG device directly connected to the side of the current-level JTAG device closest to the controller can be called the upper-level JTAG device. Any one of one or more JTAG devices directly connected to the side of the current-level JTAG device furthest from the controller can be called the secondary-level JTAG device. It should be understood that in some cases, depending on the referenced JTAG device, a JTAG device can be called an upper-level JTAG device, a current-level JTAG device, or a secondary-level JTAG device. The controller can be a BMC or a CPU.

[0037] Compared to the aforementioned solutions using discrete switching devices, the method provided in this application does not require discrete switching devices. It achieves channel switching by issuing JTAG channel switching information to the current-level JTAG device, enabling point-to-point upgrades of different secondary JTAG devices and improving the versatility of the JTAG upgrade solution. Compared to the aforementioned solutions using a motherboard CPLD instead of discrete components, the JTAG devices provided in this application present a multi-level tree topology. Each JTAG device connects to the previous level's JTAG device, eliminating the need for numerous connectors on the motherboard to connect each device and reducing motherboard design costs. Furthermore, updating and modifying the topology relationships in the tree topology is easy; only the corresponding branch needs modification without affecting other branches, further improving the versatility of the JTAG device upgrade solution and reducing the difficulty of upgrading JTAG devices.

[0038] The JTAG device upgrade method provided in this application embodiment can be applied to a computing device. This computing device includes multiple JTAG devices. Specifically, as shown... Figure 1 As shown, the computing device includes a local JTAG device, a higher-level JTAG device, and one or more secondary JTAG devices (the figure illustrates three secondary JTAG devices as an example, one of which is the target secondary JTAG device to be upgraded). The local JTAG device is connected to the higher-level JTAG device via a bus, and each local JTAG device is connected to one or more secondary JTAG devices via a bus. The bus includes a communication bus and a JTAG bus. This embodiment uses an I2C bus as an example for illustration.

[0039] The JTAG device in the computing device can be a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA) mounted on a component, or other JTAG devices with data processing capabilities. This embodiment of the application uses a CPLD as an example of a JTAG device. The component can be a motherboard, backplane, or fan board in the computing device.

[0040] Figure 2 This is a schematic diagram of the composition of a component provided in an embodiment of this application, such as... Figure 2 As shown, the component is equipped with a JTAG device. Among them, Figure 2 One end of the JTAG device in the configuration provides both a communication bus and a JTAG bus for connecting to a higher-level JTAG device. The other end also provides both a communication bus and a JTAG bus for connecting to a lower-level JTAG device. It should be noted that there can be multiple sets of communication buses and JTAG buses used to connect to lower-level JTAG devices. Figure 2 Only one group is shown as an example.

[0041] The main functions of a JTAG device are: 1. To be upgraded by a higher-level JTAG device. 2. To upgrade lower-level JTAG devices connected to it. 3. To report its own register information (topology information) to a higher-level JTAG device. 4. To record the topology information of lower-level JTAG devices connected to it.

[0042] Combination Figure 1 and Figure 2 It can be seen that, Figure 1 Each JTAG device corresponds to a set of communication buses and JTAG buses. In this embodiment, the JTAG bus is used for loading or upgrading the JTAG device, and the communication bus is used for transmitting out-of-band management signals and upgrade packages for the JTAG device.

[0043] Figure 3 This is a schematic diagram illustrating the composition of another computing device provided in an embodiment of this application, such as... Figure 3 As shown, the computing device includes five JTAG devices, designated JTAG devices 1-5. JTAG device 1 is mounted on the motherboard, JTAG devices 2-4 are mounted on backplanes 1-3 respectively, and JTAG device 5 is mounted on the fan plate. JTAG device 1 connects to three downstream JTAG devices, namely JTAG devices 2-4. JTAG device 2 connects to one downstream JTAG device, JTAG device 5. It can be seen that... Figure 3The JTAG devices in the middle present a tree-like topology. When JTAG device 2 is the local JTAG device, the parent JTAG device is JTAG device 1, and the secondary JTAG device is JTAG device 5.

[0044] In some embodiments, each JTAG device in the computing device defines a set of registers that enable channel switching between JTAG devices and the recording of JTAG device topology information.

[0045] The register includes a communication channel switching bit and a JTAG switching bit. The communication channel switching bit enables a communication channel between a JTAG device and its next-level JTAG device via a communication bus. The JTAG switching bit enables a JTAG channel between a JTAG device and its next-level JTAG device via a JTAG bus. For example, for... Figure 3 For JTAG device 1, the communication channel switching bit in the register can be used to enable the communication channel corresponding to the I2C2 bus, I2C3 bus, or I2C4 bus, and the JTAG switching bit can be used to enable the JTAG channel corresponding to JTAG2, JTAG3, or JTAG4. It can be seen that the communication channel switching bit and the JTAG switching bit allow the JTAG device to perform targeted upgrades to a specific next-level JTAG device without affecting the normal use of other next-level JTAG devices.

[0046] In addition, the register also includes: channel indicator bit, hierarchy indicator bit, and downstream device indicator bit.

[0047] The channel indicator bit is used to indicate the channel between a JTAG device and its parent JTAG device, which includes a communication channel and / or a JTAG channel. For example, Figure 3 The channel indicator bit in the register of JTAG device 2 indicates that JTAG device 2 is located on the first group of channels of JTAG device 1, which corresponds to I2C2 and / or JTAG2. The channel indicator bit in the register of JTAG device 3 indicates that JTAG device 3 is located on the second group of channels of JTAG device 1, which corresponds to I2C3 and / or JTAG3.

[0048] The hierarchy indicator bit is used to indicate the hierarchy of a JTAG device in the JTAG topology diagram. The JTAG topology diagram is used to indicate the connection relationships between parent JTAG devices, the current JTAG device, and one or more secondary JTAG devices. It can be seen that... Figure 3The JTAG topology graph presents a tree-like topology. If JTAG device 1 is the root node of the tree topology, then the level indicator bit in the register of JTAG device 1 indicates that JTAG device 1 is located at the first level of the JTAG topology graph. JTAG devices 2, 3, and 4 are the next level after JTAG device 1, then the level indicator bits in the registers of JTAG devices 2, 3, and 4 indicate that they are located at the second level of the JTAG topology graph. JTAG device 5 is the next level after JTAG device 2 in the second level, then the level indicator bit in the register of JTAG device 5 indicates that it is located at the third level of the JTAG topology graph.

[0049] The downstream device indicator bit is used to indicate the number of downstream JTAG devices of a given JTAG device. The value of the downstream device indicator bit can be determined by the number of downstream JTAG devices present when the JTAG device acquires their presence signals. For example, Figure 3 If JTAG device 1 has JTAG device 2, JTAG device 3, and JTAG device 4 connected to it, then the connected device indicator bit in the register of JTAG device 1 indicates that the number of connected devices of JTAG device 1 is 3.

[0050] In some embodiments, the register further includes a self-presentation indicator bit. The self-presentation indicator bit is used to indicate whether the JTAG device itself is present, and is determined by the parent JTAG device. For example, for... Figure 3 For JTAG device 2, after its upstream JTAG device (i.e., JTAG device 1) obtains the presence signal, it can determine that JTAG device 2 is in place and instruct JTAG device 2 to modify the self-presentation bit in its own register to indicate that JTAG device 2 has been powered on and is in place.

[0051] The definition format of a register provided in this application is shown in Table 1 below:

[0052] Table 1

[0053]

[0054] As shown in Table 1, this register is illustrated using 16 bits. Bits [15:13] represent the JTAG channel to be switched; a value of 000 indicates the default state, using the default channel (preset channel). Bit 12 indicates the device itself, read from the previous level, and is set to 1; a value of 0 indicates the device is at level 1. Bits [11:9] represent the I2C channel to be switched; a value of 000 indicates the default state, using the default channel (preset channel). Bits [8:6] represent the level of the JTAG topology of this component, bits [5:3] indicate the JTAG channel between this component and its parent component, and bits [2:0] represent the number of secondary devices.

[0055] It is understood that the device indication bit in Table 1 occupies 3 bits, which means that the maximum number of devices that can be connected to a JTAG device is 7. If more devices need to be connected to a JTAG device in a real scenario, the number of bits in the register can be increased. This application does not make specific limitations on this.

[0056] As can be seen, the above register definition effectively displays the location information of a JTAG device in the JTAG topology (its level and channel), facilitating location during the upgrade process. Furthermore, the register also includes an indicator bit for channel switching. Combined with the JTAG device's location information in the JTAG topology, the computing device can perform point-to-point upgrades of the JTAG device, ensuring the accuracy and stability of the JTAG upgrade scheme.

[0057] Figure 4 This is a flowchart illustrating a method for upgrading a JTAG device according to an embodiment of this application. Exemplarily, the method for upgrading a JTAG device provided in this embodiment can be applied to... Figure 1 In the computing device shown.

[0058] S401, The upper-level JTAG device sends JTAG channel switching information and first update information to the local JTAG device through the communication bus.

[0059] The first update information is used to upgrade the target secondary JTAG device, which is one of one or more secondary JTAG devices.

[0060] In some embodiments, when an upgrade is required for a secondary JTAG device (target secondary JTAG device) in a computing device, the higher-level JTAG device can send JTAG channel switching information and first update information to the lower-level JTAG device via the communication bus connected to it. The JTAG channel switching information enables the lower-level JTAG device to switch the JTAG channel connected to the target secondary JTAG device via the target JTAG bus.

[0061] S402. In response to the JTAG channel switching information, the local JTAG device enables the JTAG channel connected to the target secondary JTAG device via the target JTAG bus.

[0062] In some embodiments, after receiving JTAG channel switching information from the upper-level JTAG device, the local JTAG device can enable the JTAG channel connected to the target secondary JTAG device via the target JTAG bus based on the JTAG channel switching information, thereby realizing directional switching of the JTAG channel between the local JTAG device and the secondary JTAG device and achieving point-to-point upgrade.

[0063] Specifically, the registers of the local JTAG device include a JTAG switch bit. After receiving JTAG channel switching information, the local JTAG device can modify the JTAG switch bit based on the JTAG channel switching information to enable the JTAG channel connected to the target secondary JTAG device via the target JTAG bus.

[0064] For example, combining Figure 3 This will be explained. The JTAG device at this level will be used as an example. Figure 3 Taking JTAG device 2 as an example, the parent JTAG device is Figure 3 JTAG device 1 in the middle, the target secondary JTAG device is Figure 3 JTAG device 5 is located on the first channel of JTAG device 2. Therefore, after receiving the channel switching information from JTAG device 1, JTAG device 2 modifies bits [15:13] in its register from 000 to 001, enabling the JTAG channel between JTAG device 2 and JTAG device 5 connected via the JTAG5 bus.

[0065] S403. The local JTAG device sends the first update information to the target secondary JTAG device through the target JTAG bus to upgrade the target secondary JTAG device.

[0066] In some embodiments, the local JTAG device can receive first update information sent by the upper-level JTAG device, and send the first update information to the target secondary JTAG device through the enabled target JTAG bus, thereby realizing the targeted upgrade of the target secondary JTAG device.

[0067] For example, as previously described, the communication bus can be used to transmit upgrade packages for JTAG devices. Continuing with... Figure 3 To explain, after receiving the upgrade packet transmitted by JTAG device 1 via the I2C2 bus, JTAG device 2 can parse the upgrade packet to obtain the first update information, and then send the first update information to JTAG device 5 via the JTAG5 bus (target JTAG bus) to perform a targeted upgrade of JTAG device 5.

[0068] In some embodiments, such as Figure 5 As shown, prior to S401, the JTAG device upgrade method provided in this application embodiment further includes the following S400a and S400b.

[0069] S400a, the upstream JTAG device obtains communication channel switching information.

[0070] Among them, the communication channel switching information is used to instruct the upper-level JTAG device to switch the communication channel connected to the local JTAG device via the communication bus.

[0071] S400b: Based on the communication channel switching information, the upper-level JTAG device modifies the communication bus switching bit to enable the communication channel between the upper-level JTAG device and the local JTAG device via the communication bus.

[0072] Continue to combine Figure 3 Let's explain. Taking JTAG device 1 as the superior JTAG device, JTAG device 1 has three JTAG devices connected to it. Among them, JTAG device 2 is located on the first channel of JTAG device 1. If JTAG device 2 wants to send the first update information and JTAG channel switching information to JTAG device 2, the communication channel between JTAG device 1 and JTAG device 2 connected via the I2C2 bus needs to be enabled. Therefore, after JTAG device 1 obtains the communication channel switching information, it changes the value of bits [11:9] in its own register from 000 to 001, enabling the I2C2 bus between JTAG device 1 and JTAG device 2.

[0073] In some embodiments, the computing device further includes a main control unit. This main control unit can be a logic device with data processing capabilities, such as a CPU or BMC. When the upper-level JTAG device is at the first level in the JTAG topology, the main control unit is connected to the upper-level JTAG device via a communication bus and a JTAG bus. For example, in... Figure 3 In this configuration, the main control unit is located on the motherboard and is connected to JTAG device 1 via the I2C1 bus and JTAG1 bus.

[0074] In this embodiment, the main functions of the main control unit are: 1. To obtain the register information of the JTAG device through the communication bus, and to generate the topology of the JTAG device based on the register information. 2. To upgrade the JTAG device. 3. To display the JTAG topology diagram of the JTAG device in the computing device to the user.

[0075] In one possible implementation, if the main control unit is a CPU, the main control unit needs to further report the parsing results of the register information to the BMC, which then displays them to the user through the BMC management system.

[0076] In another possible implementation, if the master control unit is a BMC, the master control unit can directly display the parsing results to the user through the BMC management system.

[0077] In this embodiment, the main control unit is used to modify and configure the values ​​of the registers of the JTAG device. Combined with... Figure 3 The process of configuring the registers of JTAG devices, as described in Table 1 above, will be explained in detail. After the computing device is powered on, the master control unit will poll each JTAG device in the computing device and rewrite the register information of the JTAG devices to indicate the topology information of the JTAG devices in the JTAG topology diagram.

[0078] For JTAG device 5, since there is no device at the next level, register bits [2:0] = 3'b000. After polling all JTAG devices, the master control unit determines that JTAG device 5 is present and sets its register bit 12 to 1. When the master control unit polls JTAG device 5, it passes through 3 levels (JTAG device 1 - JTAG device 2 - JTAG device 5), so the master control unit rewrites register bits [8:6] = 3'b011. The I2C5 bus and JTAG5 bus between JTAG device 2 and JTAG device 5 are the first group of channels for JTAG device 2, so the master control unit rewrites register bits [5:3] = 3'b001. In summary, after the main control unit completes power-on polling, register 5 of the JTAG device can be represented as [15:0] = 16'b0001 0000 11001000, indicating that the second-level JTAG device is in the third level of the JTAG topology, in the first channel position, without any downstream devices, and is a leaf node of the tree topology.

[0079] For JTAG device 3, since there is no device at the next level, register bits [2:0] = 3'b000. After polling all JTAG devices, the master control unit determines that JTAG device 3 is present and sets its register bit 12 to 1. The master control unit polls and finds that JTAG device 3 has passed through 2 levels, so the master control unit rewrites register bits [8:6] = 3'b010; the I2C3 bus and JTAG3 bus are the second group of channels for JTAG device 1, so the master control unit rewrites register bits [5:3] = 3'b010. After the master control unit finishes powering on and polling, the value of JTAG device 3's register can be represented as [15:0] = 16'b0001 0000 10010000, indicating that JTAG device 3 is in the second level of the JTAG topology, the second channel position, with no downstream devices, and is a leaf node in the tree topology.

[0080] Similarly, Figure 3 The value of the register of JTAG device 4 can be represented as [15:0] = 16'b0001 0000 10100000, indicating that JTAG device 4 is located at the second level and third channel of the JTAG topology, and has no subordinate devices, making it a leaf node in the tree topology.

[0081] Figure 3 The value of the register of JTAG device 2 can be represented as [15:0] = 16'b0001 0000 0100 1001, indicating that JTAG device 1 is in the second level of the JTAG topology, in the first channel position, with one device attached below it, and is an intermediate node in the tree topology. Figure 3The value of the register of JTAG device 1 can be represented as [15:0] = 16'b0001 0000 01001011, indicating that JTAG device 1 is in the first level of the JTAG topology, the first channel position, with three devices connected below it, and is the root node of the tree topology.

[0082] As can be seen, the above register definition method demonstrates the inheritance and correlation between various JTAG devices, which facilitates the master control unit to adaptively perform out-of-band management and improves the stability and versatility of the JTAG link.

[0083] Figure 6 This is a flowchart illustrating another method for upgrading a JTAG device provided in an embodiment of this application.

[0084] S601, the main control unit, based on the JTAG topology diagram, sends communication channel switching information to the upper-level JTAG device via the communication bus; and sends JTAG channel switching information and first update information to the upper-level JTAG device via the communication bus.

[0085] Combination Figure 3 As can be seen from the explanation, the target secondary JTAG device (JTAG device 5) is the next level after JTAG device 2, and JTAG device 2 is the next level after JTAG device 1. Therefore, when an upgrade of JTAG device 5 is required, the master control unit, based on the JTAG topology, sends communication channel switching information to JTAG device 1 via the I2C0 bus. This allows JTAG device 1 to modify the communication channel switching bit in its register, enabling the I2C1 bus, so that JTAG device 1 can transmit data to JTAG device 2 via the I2C1 bus. In addition, the master control unit also sends JTAG channel switching information and first update information to JTAG device 1 via the I2C0 bus, allowing JTAG device 1 to further send the JTAG channel switching information and first update information to JTAG device 2, thus achieving a targeted upgrade of JTAG device 5 by JTAG device 2.

[0086] It can be seen that the above embodiments upgrade the secondary JTAG device; in other embodiments, the main control unit can also upgrade the primary JTAG device. Combined with... Figure 4 ,like Figure 6 As shown, the upgrade method for JTAG devices also includes S602.

[0087] S602. The main control unit sends the second update information to the upper-level JTAG device via the JTAG bus.

[0088] The second update information is used to upgrade the upstream JTAG device.

[0089] It can be seen that, Figure 3 The master control unit is directly connected to the upper-level JTAG device (JTAG device 1) via the JTAG bus (JTAG0 bus). Therefore, the master control unit can parse the second update information obtained from the upgrade package and send the second update information to the master JTAG device via the JTAG0 bus to upgrade the master JTAG device.

[0090] In some scenarios, JTAG links may change, such as the addition or deletion of JTAG devices. To ensure the normal operation and upgrades of JTAG links, the JTAG device upgrade method provided in this application can also update the JTAG link topology in a timely manner. For example... Figure 6 As shown, it also includes the following S603.

[0091] S603. When the JTAG device in the computing device changes, the master control unit updates the JTAG topology map according to the channel indicator bit, hierarchy indicator bit and downstream device indicator bit in the register of the JTAG device in the computing device.

[0092] As mentioned earlier, the registers defined in a JTAG device include channel indicator bits, hierarchy indicator bits, and downstream device indicator bits. This register information can reflect the topology information of any JTAG device and the relevant information of its secondary devices. For example, the master control unit can periodically poll each JTAG device to obtain its register information, parse it to obtain the latest JTAG link status, and update the topology map. Alternatively, each JTAG device in the JTAG link can automatically report its own register information, enabling the master control unit to update the topology map. For example... Figure 3 In the above, JTAG device 3 has added a next-level JTAG device 6. Therefore, the downstream device indicator bit in the register of JTAG device 3 indicates that JTAG device 3 has a downstream device. Furthermore, based on the register of JTAG device 6, the master control unit determines that JTAG device 6 is located in the third level, on the first group of channels of JTAG device 3. Therefore, the master control unit can update the JTAG topology, adding a third-level node under JTAG device 3 in the second level.

[0093] It is understandable that during subsequent upgrades of JTAG devices, the main control unit will upgrade based on the updated JTAG topology.

[0094] In addition, the embodiments of this application provide for Figure 6 The execution order of S601-S603 is not restricted. The diagram is only an example and does not constitute a specific limitation.

[0095] It should be noted that the foregoing embodiments are illustrated using the example of a master control unit connecting to a single first-level JTAG device. In other embodiments, the master control unit can connect to multiple first-level JTAG devices, meaning one master control unit can manage multiple JTAG links, with each first-level JTAG device serving as the root node in a tree-like topology of a JTAG link. The master control unit can manage and upgrade different JTAG links by switching between the communication bus and the JTAG bus. For details, please refer to the descriptions in the foregoing embodiments; they will not be repeated here.

[0096] The technical solutions provided in the above embodiments bring at least the following beneficial effects. The JTAG device upgrade method provided in this application allows the upper-level JTAG device of the computing device to send JTAG channel switching information to the local JTAG device when an upgrade is needed (e.g., a target secondary JTAG device). This enables the JTAG channel between the local JTAG device and the target secondary JTAG device, connected via a target JTAG bus, thereby allowing the local JTAG device to upgrade the target secondary JTAG device through the target JTAG bus. The JTAG devices provided in this application present a multi-level master-slave structure, with each JTAG device connected to the upper-level JTAG device. Compared to existing computing solutions, this eliminates the need for the motherboard to provide numerous connectors to connect each JTAG device, reducing motherboard design costs and ensuring the versatility of the JTAG device upgrade solution. In addition, this multi-level master-slave structure has a clear topology, and the topology is easy to update. Only the topology on the branch that has changed needs to be modified, without affecting other branches. This can further improve the universality of JTAG device upgrade solutions and reduce the difficulty of upgrading JTAG devices.

[0097] Furthermore, the method provided in this application embodiment does not require the use of discrete switching devices. It achieves channel switching by sending JTAG channel switching information to JTAG devices to connect different JTAG devices for point-to-point upgrades, thereby improving the versatility of the JTAG upgrade solution and reducing costs.

[0098] Furthermore, this application provides a novel register definition scheme that enables flexible switching of channels between JTAG devices, ensuring the accuracy of point-to-point upgrades. Additionally, this register definition scheme allows computing devices to adaptively identify the topology of the JTAG link without requiring extensive manual intervention. This reduces human resource costs while further ensuring the flexibility and versatility of JTAG link design, making it widely applicable in most scenarios.

[0099] As can be seen, the above mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the embodiments of this application provide corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] This application provides a schematic diagram of the structure of a computing device. For example... Figure 7 As shown, the computing device 700 includes: a processor 702, a communication interface 703, and a bus 704. Optionally, the computing device may also include a memory 701.

[0101] Processor 702 may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 702 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 702 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0102] The communication interface 703 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0103] The memory 701 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0104] As one possible implementation, the memory 701 can exist independently of the processor 702. The memory 701 can be connected to the processor 702 via a bus 704 and is used to store instructions or program code. When the processor 702 calls and executes the instructions or program code stored in the memory 701, it can implement the JTAG device upgrade method provided in this application embodiment.

[0105] In another possible implementation, the memory 701 can also be integrated with the processor 702.

[0106] The 704 bus can be an extended industry standard architecture (EISA) bus, etc. The 704 bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0107] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computing device can be divided into different functional modules to complete all or part of the functions described above.

[0108] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be executed by computer instructions instructing related hardware. The program can be stored in the computer-readable storage medium, and when executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be any of the foregoing embodiments or memory. The computer-readable storage medium can also be an external storage device of the computing device, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computing device. Further, the computer-readable storage medium can include both internal storage units and external storage devices of the computing device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computing device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0109] This application also provides a computer program product comprising a computer program that, when run on a computer, causes the computer to execute any of the JTAG device upgrade methods provided in the above embodiments.

[0110] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0111] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for upgrading a JTAG device used by a joint test team, characterized in that, This is applied to computing devices, which include a local JTAG device, a higher-level JTAG device, and one or more secondary JTAG devices; the higher-level JTAG device is connected to the local JTAG device via a communication bus and a JTAG bus. The primary JTAG device is connected to each of the one or more secondary JTAG devices via a communication bus and a JTAG bus; the method includes: The upper-level JTAG device sends JTAG channel switching information and first update information to the local JTAG device via a communication bus; the first update information is used to upgrade the target secondary JTAG device; the target secondary JTAG device is one of the one or more secondary JTAG devices; the local JTAG device is provided with a register, the register including: JTAG switching bit; Based on the JTAG channel switching information, the local JTAG device modifies the JTAG switching bit to enable the JTAG channel connected to the target secondary JTAG device via the target JTAG bus. The local JTAG device sends the first update information to the target secondary JTAG device through the target JTAG bus to upgrade the target secondary JTAG device.

2. The method according to claim 1, characterized in that, The upper-level JTAG device is equipped with a register, which includes a communication channel switching bit; Before the upstream JTAG device sends JTAG channel switching information and first update information to the local JTAG device via the communication bus, the method further includes: The upstream JTAG device acquires communication channel switching information; Based on the communication channel switching information, the upper-level JTAG device modifies the communication bus switching bit to enable the communication channel between the upper-level JTAG device and the local JTAG device connected via the communication bus.

3. The method according to claim 2, characterized in that, The register also includes: a channel indicator bit, a hierarchy indicator bit, and a downstream device indicator bit; The channel indicator bit is used to indicate a channel between a JTAG device and its parent JTAG device; the channel includes a communication channel and / or a JTAG channel. The hierarchy indicator bit is used to indicate the hierarchy of a JTAG device in the JTAG topology graph; the JTAG topology graph is used to indicate the connection relationship between the parent JTAG device, the current JTAG device, and the one or more secondary JTAG devices; The downstream device indicator bit is used to indicate the number of downstream JTAG devices of a JTAG device.

4. The method according to claim 3, characterized in that, The computing device further includes: a main control unit; when the upper-level JTAG device is at the first level in the JTAG topology, the main control unit and the upper-level JTAG device are connected via a communication bus and a JTAG bus; the method further includes: Based on the JTAG topology, the main control unit sends the communication channel switching information to the upper-level JTAG device via the communication bus; and sends the JTAG channel switching information and the first update information to the upper-level JTAG device via the communication bus.

5. The method according to claim 4, characterized in that, The method further includes: When the JTAG device in the computing device changes, the master control unit updates the JTAG topology map according to the channel indicator bit, hierarchy indicator bit, and downstream device indicator bit in the register of the JTAG device in the computing device.

6. The method according to claim 4, characterized in that, The method further includes: The main control unit sends a second update message to the upper-level JTAG device via the JTAG bus; the second update message is used to upgrade the upper-level JTAG device.

7. The method according to any one of claims 4-6, characterized in that, The main control unit is a central processing unit (CPU) or a baseboard management controller (BMC).

8. The method according to claim 1, characterized in that, The communication bus is an I2C bus.

9. A computing device, characterized in that, The computing device includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to enable the computing device to implement the JTAG device upgrade method as described in any one of claims 1 to 8.

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