Memory control method, memory controller and electronic device

Abstract

The present disclosure provides a memory control method, a memory controller and an electronic device. The memory control method is executed by programmable circuitry for controlling a target memory, and includes: detecting, by the programmable circuitry, a plurality of target events in real time; when a type and a number of the detected target events satisfy a trigger condition of any one of a plurality of preset states, selecting to run an action execution circuit module corresponding to the preset state, the trigger condition including a logical combination of one target event or a plurality of target events; and executing, by the action execution circuit module corresponding to the preset state, one or more actions corresponding to the preset state, at least one of the one or more actions being used for controlling the target memory. The embodiments of the present disclosure can flexibly configure a memory control scheme and improve the efficiency of sending control signals to the memory.

Description

Technical Field

[0001] This disclosure relates to the field of memory control technology, and more specifically, to a memory control method, a memory controller, and an electronic device. Background Technology

[0002] The controller of a Solid State Drive (SSD) is primarily controlled passively by the host to enter and exit low-power modes. During this process, the controller needs to be able to exit and handle asynchronous events. Different hosts and different buses (such as PCIe, Peripheral Component Interconnect Express) have slightly different timing and asynchronous events during low-power mode entry and exit. Since the host needs to be shut down during low-power mode entry and exit, the SSD controller becomes the primary entity responsible for handling these asynchronous events.

[0003] In related technologies, SSD controllers are typically configured with fixed timing for entering and exiting low-power modes. This approach offers low control latency and high efficiency, but it struggles to handle asynchronous events under varying hardware connectivity environments and adjusts the low-power mode entry / exit strategy based on different scenarios. Another technique integrates a small processor into the power management unit of the controller, allowing real-time editing of the low-power mode entry / exit timing via running program code. However, this method suffers from longer code execution times, resulting in significant latency for entering and exiting low-power modes. Furthermore, it cannot modify the strategy for controlling the SSD's entry and exit from low-power modes, nor can it drastically alter the timing.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a memory control method, a memory controller, and an electronic device to at least partially solve the problems of insufficient flexibility in control strategies and control timing, and high control latency during the control of memory entering and exiting low-power modes.

[0006] According to a first aspect of the present disclosure, a memory control method is provided, implemented by a programmable circuit. The programmable circuit is used to control a target memory. The memory control method includes: the programmable circuit detecting multiple target events in real time; when the type and number of the detected target events satisfy the triggering condition of any one of multiple preset states, selecting and running an action execution circuit module corresponding to the preset state, the triggering condition including one target event or a logical combination of multiple target events; the action execution circuit module corresponding to the preset state executing one or more actions corresponding to the preset state, at least one of the one or more actions being used to control the target memory.

[0007] In one exemplary embodiment of this disclosure, one of the one or more actions is used to control the programmable circuit to stop running the action execution circuit module corresponding to the preset state.

[0008] In one exemplary embodiment of this disclosure, the programmable circuit has multiple preset states, and the multiple preset states are sequential. The module for controlling the programmable circuit to stop running the action execution circuit corresponding to the preset state includes:

[0009] The programmable circuit can be controlled to run the action execution circuit module corresponding to the previous preset state of the current preset state, or to run the action execution circuit module corresponding to the next preset state of the current preset state, or to re-run the action execution circuit module corresponding to the current preset state.

[0010] In one exemplary embodiment of this disclosure, the programmable circuit has multiple preset states, one of which is a default state, and controlling the programmable circuit to stop operating in the preset state includes:

[0011] The programmable circuit is controlled to run the action execution circuit module corresponding to the default state.

[0012] In one exemplary embodiment of this disclosure, one of the one or more actions is used to generate one or more of the target events.

[0013] In one exemplary embodiment of this disclosure, one of the one or more actions is used to control the duration for which the programmable circuit runs the action execution circuit module corresponding to the preset state.

[0014] In one exemplary embodiment of this disclosure, the target memory is a solid-state drive, and the plurality of target events include at least:

[0015] The value of the built-in timer has reached a preset threshold;

[0016] The target memory is triggered to enter a low-power mode;

[0017] The target memory triggers the exit from low-power mode;

[0018] The high-speed bus for interconnecting peripheral components is in a preset state;

[0019] The request clock for the Peripheral Component Interconnect High-Speed ​​Bus is in a preset state or the Peripheral Component Interconnect High-Speed ​​Bus has a preset level;

[0020] The specified input / output interface is equal to the set value.

[0021] In one exemplary embodiment of this disclosure, the one or more actions corresponding to the preset state include at least one of the following:

[0022] Configure the target memory to enter or exit the reboot state;

[0023] Enable or disable the clock of the target memory;

[0024] Enable or disable isolation control for the target memory;

[0025] Enable the retention trigger save function or retention trigger restore function of the target memory;

[0026] Turn the internal power switch of the target memory on or off;

[0027] Turn the external power switch of the target memory on or off.

[0028] According to a second aspect of this disclosure, a memory controller is provided, characterized in that it is connected to a target memory, the memory controller including a programmable circuit connected to the target memory, the programmable circuit being configured to perform the method described in any of the preceding claims, the programmable circuit including: a target event monitoring module, the target event monitoring module being configured to monitor a plurality of target events, the plurality of target events being configurable events;

[0029] The preset state selection module is connected to the target event monitoring module and is configured with triggering conditions for multiple preset states. When any one of the multiple target events meets the triggering condition, the module controls the action execution circuit module corresponding to the preset state to run.

[0030] Multiple action execution circuit modules are provided, each of which corresponds to a preset state. The action execution circuit modules are connected to the preset state selection module. The action execution circuit modules are configured to execute one or more actions corresponding to the preset state. At least one of the one or more actions is used to control the target memory.

[0031] According to a third aspect of this disclosure, an electronic device is provided, including a memory and a memory controller as described above, the memory controller being used to implement the memory control method as described in any of the preceding claims.

[0032] This embodiment of the invention uses a programmable circuit to implement a memory controller. When the trigger condition of any preset state of the programmable circuit is met, the preset state is run and one or more actions corresponding to the preset state are executed to control the target memory. The high output efficiency of the programmable circuit can be used to effectively reduce the control latency of the target memory. Furthermore, the programmable state trigger conditions and actions of the programmable circuit can be used to flexibly set the memory control strategy. By setting the conditions for the programmable circuit to run different preset states, the timing of the control signals of each action can be adjusted, thereby achieving a dual improvement in the control efficiency and the flexibility of the control strategy for the memory.

[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0035] Figure 1 This is a schematic diagram of the memory controller in an embodiment of this disclosure.

[0036] Figure 2 This is a schematic diagram of the logic function of programmable circuit 11 in one embodiment of the present disclosure.

[0037] Figure 3 This is a flowchart of a memory control method in an exemplary embodiment of this disclosure.

[0038] Figure 4 This is a relationship diagram of multiple preset states in one embodiment of this disclosure.

[0039] Figure 5This is a block diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0041] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0042] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of the memory controller in an embodiment of this disclosure.

[0044] refer to Figure 1 The memory controller 1 is connected to the target memory 2. The memory controller 1 includes a programmable circuit 11, which is used to execute the memory control method of any of the embodiments below to control the target memory 2.

[0045] In one embodiment of this disclosure, the target memory 2 is, for example, a solid-state drive (SSD), and the memory controller 1 is, for example, an SSD controller. In other embodiments of this disclosure, the target memory 2 may also be other types of memory, such as a hard disk drive, a magnetic disk, a cache, RAM, etc. In this case, the memory controller 1 may be a dedicated controller corresponding to the memory, a central processing unit (CPU), or other processor capable of programmable circuitry. This disclosure is not limited to the types of target memory 2 and memory controller 1.

[0046] In addition, the memory controller 1 can be set up independently from the target memory 2 and connected via signal lines or buses, or it can be located in the same hardware package as the target memory 2.

[0047] The programmable circuit 11 can be part of the memory controller 1 or the main body for implementing all the functions of the memory controller 1. Those skilled in the art can configure it according to actual needs. In one embodiment, the programmable circuit 11 can be used to implement the functions of the power management unit (PMU) in the memory controller 1.

[0048] Programmable circuits can be implemented using various circuits. Depending on the specific function and control objective, various digital and analog circuits can be used. This disclosure does not limit the specific circuit used in the programmable circuit, but only its functionality. However, regardless of the specific circuit used to implement the programmable circuit, it must possess... Figure 2 The logic module shown.

[0049] Figure 2 This is a schematic diagram of the logic function of programmable circuit 11 in one embodiment of the present disclosure.

[0050] refer to Figure 2 In one embodiment, the programmable circuit 11 may include:

[0051] The target event monitoring module 111 is configured to monitor multiple target events, all of which are configurable events.

[0052] The preset state selection module 112 is connected to the target event monitoring module 111. It is configured with trigger conditions for multiple preset states and controls the action execution circuit module corresponding to the preset state to run when any one of the multiple target events meets the trigger condition.

[0053] Multiple action execution circuit modules 113, each action execution circuit module 113 corresponds to a preset state, the action execution circuit module 113 is connected to the preset state selection module 112, the action execution circuit module 113 is configured to execute one or more actions corresponding to the preset state, and at least one of the one or more actions is used to control the target memory 2.

[0054] exist Figure 2In the illustrated embodiment, the target event monitoring module 111 can, for example, pre-configure multiple circuits corresponding to the target events that can be monitored. Before running the programmable circuit 11, the circuits corresponding to the target events to be monitored can be configured through the program. For example, the circuit corresponding to a target event can be enabled or disabled by inputting an enable signal or a disable signal to different circuits. Taking a specific circuit as an example, if the circuit corresponding to the high-level input event of the signal INX is a NAND gate, the first input terminal of the NAND gate is used to connect to the signal INX, the second input terminal of the NAND gate is used to connect to the enable signal, and the output terminal of the NAND gate is used to output the monitoring result of the event, then the NAND gate can be enabled or disabled by pre-setting a normal enable signal or disable signal to the second input terminal of the NAND gate, thereby selecting whether to monitor the high-level input event of the signal INX.

[0055] The circuits described above are merely examples. Depending on the type of target event that the programmable circuit 11 can monitor, the target event monitoring module 111 may include different forms of configurable monitoring circuits. This disclosure does not impose any special limitations on this.

[0056] The preset state selection module 112 can also be implemented using configurable digital or analog circuits. When configuring the preset state selection module 112, specific trigger conditions can be configured for each preset state, and the action execution module 113 corresponding to that preset state can be controlled to run when any trigger condition is met. For example, the output of a monitoring circuit for multiple target events (these target events correspond to the same trigger condition) can be connected to the input of a logic gate circuit, and the operation of the action execution module 113 corresponding to that preset state can be controlled based on the output signal of the logic gate circuit. In this case, the logic gate circuit is a sub-circuit of the preset state selection module 112. The preset state selection module 112 can have multiple sub-circuits to output control signals for controlling multiple action execution modules 113. In one embodiment, the preset state selection module 112 can also be implemented using a single integrated circuit, which can be configured by those skilled in the art according to specific application scenarios.

[0057] It should be noted that regardless of the circuit through which the preset state selection module 112 is implemented, the number and type of its corresponding preset states can be configured, and the triggering conditions of each preset state are also configurable (for example, the input signal of the logic gate circuit in the above example must be configurable).

[0058] Each action execution module 113 may include sub-circuits for performing one or more actions. The actions performed by these sub-circuits are configurable, and the type and number of sub-circuits corresponding to each action execution module 113 are also configurable. In one embodiment, the sub-circuits corresponding to different action execution modules 113 may overlap. For example, an OR gate circuit may be connected to the output terminals of multiple sub-circuits simultaneously. These multiple sub-circuits may belong to different action execution modules. If any sub-circuit outputs a high level, the OR gate circuit can be used as the next sub-circuit in the action execution module 113 where that sub-circuit is located, and output a high level.

[0059] The circuit described above is just an example; there can be many different specific circuit configurations.

[0060] The configuration of the programmable circuit 11 can be performed before its application. When a brand-new, unedited memory controller 1 is applied to a new device, the modules in the programmable circuit 11 can be configured according to the hardware environment of the memory controller 1 (PCIE parameters, CPU parameters, etc.) and application requirements. This includes configuring the target events to be monitored, configuring the trigger conditions for each preset state, and configuring the actions to be performed by the action execution module 113 corresponding to each preset state. The configuration process can be a one-time process, such as through fuse burning, or it can be erasable and rewritable, such as through code burning. However, regardless of the configuration, the programmable circuit 11, once configured, has a defined state and can automatically run according to the transmission of electrical signals until its configuration is modified.

[0061] By using the programmable circuit 11 to execute the memory control method of the present disclosure embodiment, the control logic of the memory can be flexibly adjusted and the control latency of the memory can be shortened by utilizing the efficient processing of the hardware circuit.

[0062] Figure 3 This is a flowchart of a memory control method in an exemplary embodiment of this disclosure.

[0063] refer to Figure 3 The memory control method 300 may include:

[0064] Step S1: The programmable circuit detects multiple target events in real time;

[0065] Step S2: When the type and number of the detected target events meet the triggering condition of any one of the multiple preset states, select and run the action execution circuit module corresponding to the preset state. The triggering condition includes one target event or a logical combination of multiple target events.

[0066] Step S3: The action execution circuit module corresponding to the preset state executes one or more actions corresponding to the preset state, and at least one of the one or more actions is used to control the target memory.

[0067] This embodiment of the invention uses a programmable circuit to implement a memory controller. When the trigger condition of any preset state of the programmable circuit is met, the preset state is run and one or more actions corresponding to the preset state are executed to control the target memory. The high output efficiency of the programmable circuit can be used to effectively reduce the control latency of the target memory. Furthermore, the programmable state trigger conditions and actions of the programmable circuit can be used to flexibly set the memory control strategy. By setting the conditions for the programmable circuit to run different preset states, the timing of the control signals of each action can be adjusted, thereby achieving a dual improvement in the control efficiency and the flexibility of the control strategy for the memory.

[0068] The steps of the memory control method 200 will now be described in detail.

[0069] In step S1, the programmable circuit detects multiple target events in real time.

[0070] In this embodiment of the disclosure, the target event is, for example, a parameter of the target memory 2 or the memory controller 1 being at a preset value, or a parameter value changing, or an event indicating a change in an indicator value (e.g., the occurrence of a rising edge of a clock signal), or other detectable events related to the operation of the target memory 2 or the memory controller 1.

[0071] The detection of multiple target events is independent. For example, if a parameter has only two values, 0 and 1, then a parameter equal to 0 can be considered target event 1, and a parameter equal to 1 can be considered target event 2. When this parameter is detected, first check if the parameter's value matches target event 1, then check if the parameter's value matches target event 2. If the parameter's value is 0, then target event 1 is detected, and target event 2 is not detected; if the parameter's value is 1, then target event 2 is detected, and target event 1 is not detected. And so on.

[0072] The detection results of multiple target events can be latched using a latch.

[0073] In one embodiment of this disclosure, the target memory 2 is a solid-state drive (SSD), and the memory control method 200 is mainly used to control the target memory 2 to enter and exit a low-power mode. At this time, multiple target events may include at least the value of the built-in timer reaching a preset threshold, the target memory triggering to enter a low-power mode, the target memory triggering to exit a low-power mode, the peripheral component interconnect high-speed bus being in a preset state, the request clock of the peripheral component interconnect high-speed bus being in a preset state or the peripheral component interconnect high-speed bus exhibiting a preset level, and the specified input / output interface being equal to a set value.

[0074] For example, multiple target events can be set as follows:

[0075] (1) The built-in timer reaches the set threshold;

[0076] (2) Timeout event in low-power mode (timeout period reached);

[0077] (3) Firmware triggers entry into low-power mode;

[0078] (4) Firmware triggers exit from low power mode;

[0079] (5) The PCIe (Peripheral Component Interconnect High-Speed ​​Bus) is in the L1.2 idle state;

[0080] (6) PCIe is in L1.2 exit state;

[0081] (7) The PCIe SLEEP Domain is powered on;

[0082] (8) The PCIe SLEEP Domain is powered off;

[0083] (9) A request clock (clkreq) rising edge and high level event occurs on PCIe, or a request clock (clkreq) rising edge and high level event with a programmable delay generated based on the original request clock (clkreq) rising edge and high level.

[0084] (10) A request clock (clkreq) falling edge and low level event occurs on PCIe, or a request clock (clkreq) falling edge and low level event with a programmable delay generated based on the original clkreq falling edge and low level.

[0085] (11) The specified GPIO (General Purpose Input / Output) = 0 event;

[0086] (12) The specified GPIO=1 event;

[0087] (13) PCIe Perstn (Host's reset command for PCIe device) = 0 event;

[0088] (14) PCIe Perstn = 1 event.

[0089] The target events to be detected in the embodiments of this disclosure can be set according to actual needs, and this disclosure does not impose any special restrictions on them.

[0090] In step S2, when the type and number of the detected target events meet the triggering condition of any one of the multiple preset states, the action execution circuit module corresponding to the preset state is selected to run. The triggering condition includes one target event or a logical combination of multiple target events.

[0091] In this embodiment, the programmable circuit 11 can have multiple preset states, each of which can be configured with a trigger condition. This trigger condition is either one of the multiple target events in step S1, or a logical combination of multiple target events. For example, if the programmable circuit has four preset states A, B, C, and D, and the multiple target events are numbered 1 to 10 respectively, then the trigger condition for preset state A can be the occurrence of target event 2; the trigger condition for preset state B can be the simultaneous occurrence of target events 1 and 3, expressed as (target event 1 AND target event 3); the trigger condition for preset state C can be a logical combination of three preset events 5, 6, and 7, expressed as (target event 5 AND (target event 6 OR target event 7)), and so on. The above logical combinations as trigger conditions can be implemented by setting one or more logic gates, and the connection relationship between the logic gates is configurable.

[0092] In some embodiments, trigger conditions may not be set for one or more preset states. For example, preset state D may be set to have no trigger conditions, but actions to jump to preset state D may be set in both preset state A and preset state B, allowing jumps from other preset states to preset state D. In this case, the operation of the action execution circuit module corresponding to preset state D is controlled by the output signals of other action execution circuit modules.

[0093] In other embodiments, one of a plurality of preset states may be set as the default state, and step S1 may be set to be performed in the default state.

[0094] The preset state settings of the programmable circuit 11 when applied to the memory controller 1 can be adjusted according to the control requirements of the programmable circuit 11, and this disclosure does not impose any special restrictions on this.

[0095] When the target event detected by the target event monitoring module 111 of the programmable circuit 11 meets the triggering condition of a certain preset state, the programmable circuit 11 runs the action execution circuit module 113 corresponding to the preset state. It should be noted that the programmable circuit 11 can only run one action execution circuit module 113 corresponding to a preset state at a time. Therefore, the triggering conditions of each preset state need to be set to be independent of each other, that is, to ensure that there is no target event state that meets the triggering conditions of two preset states at the same time.

[0096] It should also be noted that the "preset state" in this embodiment refers to the state corresponding to the programmable circuit 11, rather than the standard state of the target memory 2 (e.g., low-power state). The actions corresponding to one or more preset states can control the target memory 2 to enter various standard states. The preset states and the actions corresponding to the preset states are configured automatically according to the control strategy and can be flexibly modified.

[0097] In step S3, the action execution circuit module corresponding to the preset state executes one or more actions corresponding to the preset state, and at least one of the one or more actions is used to control the target memory.

[0098] Each preset state can correspond to one or more actions. Each action may be, for example, calling an executable instruction or assigning a value to a parameter. The number and type of actions corresponding to different preset states are different. These one or more actions can be executed by the action execution circuit module 113 corresponding to the preset state.

[0099] Because the execution time of a preset state is fixed, but the time to complete an action within that preset state is uncertain, if multiple actions are executed sequentially or in parallel within a preset state, it cannot be guaranteed that the start time of each action will be the ideal time. In other words, the timing of actions other than the first action within the preset state cannot be accurately controlled. Therefore, when a preset state corresponds to multiple actions, the timing requirements for actions other than the first action cannot be too high.

[0100] In one embodiment of this disclosure, each preset state can be set to correspond to only one action. Furthermore, the order of each action can be adjusted by adjusting the triggering conditions of the preset state corresponding to each action, thereby precisely controlling the timing between each action and other actions.

[0101] In one embodiment, the action corresponding to the preset state may further include an action for controlling the duration of the programmable circuit in the preset state. By controlling the duration of the programmable circuit 11 in the current preset state, the execution duration of the action corresponding to the current preset state can be controlled. For example, if the first action of a preset state A is to set a parameter x = 1, and the second action is to set timer = 10s, it means that in the current preset state, x = 1 must be set and held for 10s before the execution circuit modules for other preset states can be run.

[0102] Thus, the duration of the action corresponding to the preset state can be accurately controlled, and the control timing of the target memory 2 can be accurately controlled.

[0103] In another embodiment, the action corresponding to the preset state may further include actions for generating one or more target events. For example, in the above embodiment, when the target event includes a specified GPIO=1, one of the actions corresponding to a certain preset state can be set to control the GPIO=1, so that after the operation of the current preset state ends, the programmable circuit 11 can detect the occurrence of the event and determine the next preset state corresponding to the action execution circuit module to be run.

[0104] Among the multiple actions corresponding to a preset state, there can be actions for controlling the target memory 2, as well as actions for controlling the programmable circuit 11 to switch between the action execution circuit modules corresponding to the multiple preset states (i.e., jump out of the current preset state).

[0105] In one embodiment, one of the one or more actions is used to control the programmable circuit to stop running the action execution circuit module corresponding to the preset state.

[0106] Figure 4 This is a relationship diagram of multiple preset states in one embodiment of this disclosure.

[0107] refer to Figure 4 When the programmable circuit 11 has multiple preset states, these multiple preset states can be sequential, that is, each preset state can have a fixed next preset state or a fixed previous preset state. In some cases, a preset state can have both a fixed next preset state and a fixed previous preset state at the same time.

[0108] There can be multiple previous preset states for a preset state, which can be jumped to according to different conditions; there can also be multiple next preset states for a preset state, which can also be jumped to according to different conditions.

[0109] exist Figure 4In the illustrated embodiment, preset state A has two fixed next preset states, namely preset state B and preset state C; preset state B has one fixed previous preset state (preset state A) and two fixed next preset states (preset state C and preset state D); preset state D has one fixed previous preset state (preset state B) and one fixed next preset state (preset state C); preset state C has three fixed previous preset states (preset state A, preset state B, and preset state D).

[0110] Among them, preset state A has only one action (action 1), preset state B has three actions (action 2, action 3, and action 4 in execution order), preset state C has two actions (action 5 and action 3 in execution order), and preset state D has one action (action 5).

[0111] exist Figure 4 In the embodiment shown, the actions corresponding to different preset states can be the same. For example, both preset states B and preset states C have action 3.

[0112] Stopping the execution of the action execution circuit module corresponding to the preset state not only refers to running the action execution circuit modules corresponding to other preset states, but also to re-running the action execution circuit module corresponding to the preset state. For example, in preset state B, after executing action 2, an action 3 can be set after action 2 to determine whether it is necessary to re-run the action execution circuit module corresponding to preset state B. If so, action 4 after action 3 can control the state flag of programmable circuit 11 to be reset to the current preset state, and then stop the execution of the action execution circuit module corresponding to the current preset state. Thus, when the execution of the action execution circuit module corresponding to the current preset state is stopped, the action execution circuit module corresponding to the current preset state is re-run according to the state flag of programmable circuit 11, and action 2 is executed again.

[0113] In this embodiment of the disclosure, when the target memory 2 is an SSD, it can also be set in preset state B, where there are only two situations in which the action execution circuit module corresponding to preset state B stops running: one is to run the action execution circuit module corresponding to the next preset state (preset state D), and the other is to return to the action execution circuit module corresponding to the previous preset state (preset state A).

[0114] In another embodiment, a default state (e.g., a start state) may also exist among multiple preset states. The action execution circuit module corresponding to one or more preset states can stop running, which can be used to control the programmable circuit 11 to run in the default state. If no triggering condition matching other preset states is detected, the circuit can remain in the default state.

[0115] When the target memory 2 is an SSD and the memory controller 1 is an SSD controller, the types of actions corresponding to the multiple preset states may include, for example, setting the target memory to run or exit restart state, enabling or disabling the clock of the target memory, enabling or disabling the isolation control of the target memory, enabling the retention trigger save function or retention trigger restore function of the target memory, turning the internal power switch of the target memory on or off, and turning the external power switch of the target memory on or off.

[0116] For example, a preset state can be set to correspond to one or more of the following actions:

[0117] a.Set Reset = 0 (Sets the target storage to exit the restart state);

[0118] b. Set Reset = 1 (Sets the target storage to restart state);

[0119] c. Disable Clock (Disables the clock of the target memory);

[0120] d. Enable clock (Enable the clock of the target memory);

[0121] e. Enable Isolation Control;

[0122] f. Disable Isolation Control;

[0123] g. Enable Retention Flipflop Save (Enables the retention flip-flop save function of the target memory);

[0124] h. Enable Retention Flipflop Restore (Enables the retention flip-flop recovery function of the target memory);

[0125] i. Turn on the internal power switch of the target memory;

[0126] j. Turn off the internal power switch of the target memory;

[0127] k. Turn on the external power switch.

[0128] l. Turn off the external power switch.

[0129] The above actions are merely examples; those skilled in the art can set them up according to their actual circumstances.

[0130] By performing one or more of the above actions, the SSD can be controlled to run in low-power mode or exit low-power mode. The order, trigger time, time interval, and duration of each action can be accurately adjusted, and the low-power strategy of the SSD can be flexibly adjusted.

[0131] Since step S1 is executed through an independent circuit (target event monitoring module 111), and actions corresponding to multiple preset states are executed in parallel, the action execution circuit module 113 is constantly affected by the target event monitoring module 111 while it is running, enabling rapid response to asynchronous events. Furthermore, the programmable circuit 11 can quickly switch between action execution circuit modules corresponding to multiple preset states. Once a target event corresponding to the trigger condition of a preset state occurs, each action can also be executed rapidly, resulting in low latency in both SSD operation and shutdown in low-power mode.

[0132] In summary, the embodiments disclosed herein can realize a safe, reliable, flexible, and high-performance SSD low-power mode control scheme, taking into account safety, reliability, flexibility, and low latency.

[0133] Corresponding to the above method embodiments, this disclosure also provides a memory control device (virtual device) that can be used to execute the above method embodiments.

[0134] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0135] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0136] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0137] The following reference Figure 5 To describe an electronic device 500 according to this embodiment of the present invention. Figure 5 The electronic device 500 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0138] like Figure 5 As shown, the electronic device 500 is manifested in the form of a general-purpose computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including storage unit 520 and processing unit 510), and a memory controller 540.

[0139] The storage unit stores program code that can be executed by the processing unit 510, causing the processing unit 510 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 510 can perform the method shown in the embodiments of this disclosure.

[0140] Storage unit 520 may include readable media in the form of volatile storage units, such as random access memory (RAM) 5201 and / or cache storage unit 5202, and may further include read-only memory (ROM) or solid-state drive (SSD) 5203.

[0141] Storage unit 520 may also include a program / utility 5204 having a set (at least one) program module 5205, such program module 5205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0142] Bus 530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0143] The memory controller 540, for example, is memory controller 1, used to implement the method of any of the above embodiments to control the memory unit 520.

[0144] Electronic device 500 can also communicate with one or more external devices 600 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 500, and / or with any device that enables electronic device 500 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 560. As shown, network adapter 560 communicates with other modules of electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0145] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0146] In exemplary embodiments of this disclosure, an electronic device is also provided, which stores a program product capable of implementing the methods described above. In some possible implementations, various aspects of the invention can also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the invention.

[0147] The program product for implementing the above-described method according to embodiments of the present invention may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0148] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0149] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0150] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0151] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0152] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0153] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A memory control method, characterized in that, Executed via a programmable circuit, the programmable circuit including an action execution circuit module, the programmable circuit being used to control a target memory via the action execution circuit module, the memory control method including: The programmable circuit detects multiple target events in real time. When the type and number of the detected target events meet the triggering condition of any one of the multiple preset states, the action execution circuit module corresponding to the preset state is selected to run. The triggering condition includes one target event or a logical combination of multiple target events. The action execution circuit module corresponding to the preset state executes one or more actions corresponding to the preset state. At least one of the one or more actions is used to control the target memory. The programmable circuit has multiple preset states, and there is a sequence among the multiple preset states. One of the one or more actions is used to control the duration for which the programmable circuit runs the action execution circuit module corresponding to the preset state.

2. The memory control method as described in claim 1, characterized in that, One of the one or more actions is used to control the programmable circuit to stop running the action execution circuit module corresponding to the preset state.

3. The memory control method as described in claim 2, characterized in that, The module for controlling the programmable circuit to stop operating the action execution circuit corresponding to the preset state includes: The programmable circuit can be controlled to run the action execution circuit module corresponding to the previous preset state of the current preset state, or to run the action execution circuit module corresponding to the next preset state of the current preset state, or to re-run the action execution circuit module corresponding to the current preset state.

4. The memory control method as described in claim 2, characterized in that, The programmable circuit has multiple preset states, one of which is a default state. Controlling the programmable circuit to stop operating in the preset state includes: The programmable circuit is controlled to run the action execution circuit module corresponding to the default state.

5. The memory control method as described in claim 1, characterized in that, One of the one or more actions is used to generate one or more of the target events.

6. The memory control method as described in claim 1, characterized in that, The target storage is a solid-state drive, and the plurality of target events include at least: The value of the built-in timer has reached a preset threshold; The target memory is triggered to enter a low-power mode; The target memory triggers the exit from low-power mode; The high-speed bus for interconnecting peripheral components is in a preset state; The request clock for the Peripheral Component Interconnect High-Speed ​​Bus is in a preset state or the Peripheral Component Interconnect High-Speed ​​Bus has a preset level; The specified input / output interface is equal to the set value.

7. The memory control method as described in claim 6, characterized in that, The preset state corresponds to one or more actions, including at least one of the following: Configure the target memory to enter or exit the reboot state; Enable or disable the clock of the target memory; Enable or disable isolation control for the target memory; Enable the retention trigger save function or retention trigger restore function of the target memory; Turn the internal power switch of the target memory on or off; Turn the external power switch of the target memory on or off.

8. A memory controller, characterized in that, A target memory is connected, the memory controller includes a programmable circuit, the programmable circuit is connected to the target memory, the programmable circuit is configured to perform the method according to any one of claims 1 to 7, the programmable circuit comprising: A target event monitoring module, which is configured to monitor multiple target events, all of which are configurable events; The preset state selection module is connected to the target event monitoring module and is configured with triggering conditions for multiple preset states. When any one of the multiple target events meets the triggering condition, the module controls the action execution circuit module corresponding to the preset state to run. Multiple action execution circuit modules are provided, each of which corresponds to a preset state. The action execution circuit modules are connected to the preset state selection module. The action execution circuit modules are configured to execute one or more actions corresponding to the preset state. At least one of the one or more actions is used to control the target memory.

9. An electronic device, comprising a memory and a memory controller as claimed in claim 8, the memory controller being configured to implement the memory control method as claimed in any one of claims 1-7.

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