A dynamic memory management device and method for high-level synthesis

Abstract

This invention relates to a dynamic memory management device and method for high-level synthesis. The device includes at least several search cache modules and several modification write-back modules. The search cache modules are connected to DRAM storage modules and BRAM cache modules, respectively. The modification write-back modules are also connected to DRAM storage modules and BRAM cache modules, respectively. The BRAM cache modules cache node information on the search path and temporarily store modification information for nodes. The search cache modules read node data from the DRAM storage modules and write it to the BRAM cache modules based on received operators and node addresses. The modification write-back modules read node data from the BRAM cache modules and write it back to the DRAM storage modules. Addressing the low execution efficiency of directly porting traditional operating systems to FPGAs, this invention leverages the large capacity of DRAM on FPGAs to achieve efficient dynamic memory allocation and reclamation, improving the ease of use and code reusability for high-level synthesis.

Description

Technical Field

[0001] This invention relates to the field of computer hardware customization technology, and in particular to a dynamic memory management device and method for high-level integration. Background Technology

[0002] Custom hardware, represented by FPGAs, excels in improving computing performance, offering performance gains several orders of magnitude greater than CPUs. Despite FPGAs' performance advantages and mature commercial ecosystem, FPGA applications are developed using RTL languages ​​(Representational Languages) for hardware logic, resulting in lengthy development cycles. High-level synthesis (HLS) is a language developed to accelerate FPGA development. HLS uses higher-level abstraction software code, such as C / C++, to develop hardware, freeing developers from the tedious RTL language and allowing programmers without hardware development experience to participate in hardware development. While HLS performance approaches that of hand-written RTL languages ​​in many aspects, it does not support some common software code practices, such as dynamic memory management (malloc / free). Although this part of the code appears infrequently, it is a critical part of the code logic. The lack of mapping for this part forces developers to perform extensive code refactoring to replace dynamic memory management with static memory management. Besides causing extensive code refactoring, static memory allocation forces programmers to allocate memory according to the maximum memory usage, leading to low memory utilization and high hardware resource overhead. Therefore, dynamic memory management is essential.

[0003] Memory management is one of the most important tasks of an operating system, and many mature solutions exist, such as Sequential Fits, Buddy Systems, and Bitmapped Fits. However, there is no universal operating system for FPGA platforms. Directly porting traditional operating system software methods to FPGAs is not very efficient. For example, the Buddy System approach has become the mainstream management method on operating systems due to its advantages such as speed and simplicity. However, directly porting it to the FPGA hardware platform will result in long latency due to memory bandwidth limitations.

[0004] Currently, dynamic memory management on FPGA platforms primarily employs three allocation methods: Fixed Size, Bitmap, and Buddy System. None of these methods are suitable for managing gigabyte-scale DRAM memory. The Fixed Size method can only allocate memory blocks of fixed length, resulting in poor flexibility and causing significant memory fragmentation and low memory utilization. The Bitmap method uses each bit in a vector to correspond to a fixed-length address block, allocating and reclaiming memory by reversing the corresponding number of bits in the vector. This method is unsuitable for gigabyte-scale DRAM memory management because gigabyte-scale memory spaces result in very long vectors, and in the worst case, each allocation would traverse the entire vector, leading to very low allocation efficiency. The Buddy System method uses a tree structure to accelerate Bitmap lookups, but as the tree height increases, the clock frequency drops significantly, making it unsuitable for managing large DRAMs as well.

[0005] Chinese patent CN109324904A discloses a dynamic memory management method and apparatus. The method includes: S10 determining the required memory management type; S21, if it is determined that a data object needs to be stored in a TypedArray, further determining whether there is unstored space in the TypedArray, and that the TypedArray has pre-allocated storage units of a first preset length; if so, proceeding to step S31; S31, according to the current data length in the TypedArray, storing the data object into a storage unit in storage order, and incrementing the current data length by 1. This method manages JavaScript dynamic memory through TypedArray, significantly reducing the frequency of JavaScript engine memory allocation / garbage collection and improving JavaScript performance. However, this invention is not suitable for GB-level DRAM memory management.

[0006] Chinese patent CN103377134A discloses a dynamic memory management system based on the Harvard architecture, which includes a Harvard architecture processor, a program bus, a data bus, a program memory, a data memory, a dynamic memory management unit, and dynamic memory controlled by the memory management unit. Depending on the application needs of the system, the dynamic memory management unit can be configured by a program in the program memory, enabling the dynamic memory to be accessed by the program bus or the data bus, realizing the dynamic allocation of program storage space and data storage space, thereby maximizing system performance. However, this invention is not suitable for managing gigabyte-level DRAM memory.

[0007] As stated above, none of the published patents address the shortcomings identified in this invention. This invention aims to provide a dynamic memory management device and method for high-level synthesis.

[0008] Furthermore, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making this invention, but due to space limitations, not all details and contents were listed in detail. However, this does not mean that the present invention does not possess the features of these prior art. On the contrary, the present invention already possesses all the features of the prior art, and the applicant reserves the right to add relevant prior art to the background art. Summary of the Invention

[0009] Existing FPGA platforms employ three main dynamic memory management methods: Fixed Size, Bitmap, and Buddy System. None of these methods are suitable for managing DRAM memory. The Fixed Size method can only allocate fixed-length memory blocks, resulting in poor flexibility and causing significant memory fragmentation and low memory utilization. The Bitmap method uses each bit in a vector to correspond to a fixed-length address block, allocating and reclaiming memory by reversing the corresponding number of bits in the vector. This method is unsuitable for managing gigabyte-scale DRAM memory because gigabyte-scale memory spaces result in very long vectors, and in the worst case, each allocation would traverse the entire vector, leading to very low allocation efficiency. The Buddy System method uses a tree structure to accelerate Bitmap lookups, but as the tree height increases, the clock frequency drops significantly, making it unsuitable for managing large DRAMs as well.

[0010] To address the shortcomings of existing technologies, this invention provides a dynamic memory management device for high-level synthesis. The device includes at least several search cache modules and several modification write-back modules. The search cache modules are connected to both a DRAM storage module and a BRAM cache module. The modification write-back modules are also connected to both the DRAM storage module and the BRAM cache module. The BRAM cache module caches node information along the search path and temporarily stores modification information for nodes. The search cache module reads node data from the DRAM storage module and writes it to the BRAM cache module based on received operators and node addresses. The modification write-back modules read node data from the BRAM cache module and write it back to the DRAM storage module. This invention supports the dynamic memory management requirements in high-level synthesis, reduces coding workload, and improves memory utilization.

[0011] Preferably, the DRAM storage module is at least divided into a static storage area, a dynamic storage area, and a multi-way search tree storage area. The static storage area is used to store information that will not be released after being written, and the dynamic storage area is a dynamically managed memory region. The multi-way search tree storage area is used to store search tree structure information, wherein the search tree structure information is managed at the node level based on a free node linked list. When extracting a node, the multi-way search tree storage area extracts the next node from the head of the free node linked list, and when releasing a node, the empty node is reinserted into the head of the free node linked list. This invention uses a search tree structure to manage free memory blocks and designs corresponding memory allocation and reclamation algorithms and a bidirectional pipeline. Memory block allocation and reclamation can be completed within high-order memory reads and writes of the tree, while avoiding backtracking traversal of the search tree.

[0012] Preferably, the search cache modules are configured in a multi-layer structure with the same number of layers as the search tree. After one of the search cache modules analyzes the operator and the node data, the search cache module will pass the corresponding operator and the node address to be read to another adjacent search cache module.

[0013] Preferably, the modification write-back modules are configured in a multi-layer structure with the same number of layers as the search tree. The modification write-back module modifies the nodes in the BRAM cache module according to the received operator and writes the node data back to the multi-way search tree storage area in the DRAM storage module. After one of the modification write-back modules analyzes the operator and the read node, the modification write-back module passes the corresponding operator to the adjacent modification write-back module.

[0014] Preferably, the hierarchical transmission order of data in the plurality of search cache modules is the reverse of the hierarchical transmission order of data in the plurality of modification write-back modules.

[0015] Preferably, the memory management method of the multi-way search tree storage area is configured as follows: managing free memory blocks in memory based on the search tree structure; wherein, the free memory block is the smallest unit of memory, and the free memory block is represented by its starting address and length.

[0016] This invention manages memory in the form of free memory blocks, using the starting address and length of a memory block to represent a free memory block. It can manage not only tens of MB of BRAM, but also supports the management of 16GB of DRAM. The BRAM utilization rate is very low, avoiding resource crowding of computing units.

[0017] Preferably, the device further includes a switching module, which is connected to the search cache module and the modification write-back module located at the bottom layer, respectively. When the search cache module at the bottom layer passes the operator for releasing the memory block to the switching module, the switching module switches the passing order of the operator to the reverse order and passes the operator to the modification write-back module connected to it.

[0018] Preferably, the device further includes a request queue module, which is connected to several of the search cache modules. The request queue module is used to cache memory allocation requests and memory release requests sent by the computing unit. Failed allocation requests due to insufficient memory are cached in the queue, and dequeued allocation requests are added to the pipeline for computation.

[0019] The present invention also provides a dynamic memory management method for high-level synthesis, the method comprising at least: setting a plurality of search cache modules into a multi-layer structure with the same number of layers as the search tree; setting a plurality of modification write-back modules into a multi-layer structure with the same number of layers as the search tree; wherein the search cache modules read node data from the DRAM storage module and write it into the BRAM cache module according to the operator and node address passed from the previous layer; the BRAM cache module caches node information on the search path and temporarily stores modification information of the nodes; and the modification write-back modules read node data from the BRAM cache module and write it back to the DRAM storage module.

[0020] Preferably, the method further includes: the DRAM storage module is at least divided into a static storage area, a dynamic storage area, and a multi-way search tree storage area; the static storage area is used to store information that will not be released after being written, and the dynamic storage area is a dynamically managed memory area; the multi-way search tree storage area is used to store search tree structure information, and the multi-way search tree storage area is configured to manage free memory blocks in memory based on the search tree structure; wherein, the free memory block is the smallest unit of memory.

[0021] The method of this invention uses a search tree structure to manage free memory blocks, and designs corresponding memory allocation and reclamation algorithms and bidirectional pipelines. The allocation and reclamation of memory blocks can be completed within the high-order memory read and write operations of the tree, while avoiding backtracking traversal of the search tree, which significantly improves the efficiency of memory management. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the preferred hardware structure of the high-level integrated dynamic memory management device of the present invention;

[0023] Figure 2This is a schematic diagram of a preferred free memory block mapping according to the present invention;

[0024] Figure 3 This is a schematic diagram of the preferred multi-way search tree logic structure of the present invention;

[0025] Figure 4 This is a schematic diagram of the preferred storage structure of the multi-way search tree of the present invention.

[0026] List of reference numerals

[0027] 1: Static storage area; 2: Dynamic storage area; 3: Multi-way search tree storage area; 4: DRAM storage module; 5: Request queue module; 6: Search cache module; 7: BRAM cache module; 8: Modification write-back module; 9: Switching module. Detailed Implementation

[0028] The following is a detailed explanation with reference to the accompanying drawings.

[0029] To address the shortcomings of existing technologies, which are currently unsuitable for managing GB-level DRAM memory, resulting in poor flexibility, low memory utilization, long memory space leading to long vectors, low allocation efficiency, and severe clock frequency drops, this invention provides a dynamic memory management device and method for high-level integration, aiming to enable dynamic management of DRAM-level memory.

[0030] The dynamic memory management device for high-level synthesis of the present invention has the following hardware structure: Figure 1 As shown.

[0031] A dynamic memory management device for high-level integration includes a request queue module 5, several search cache modules 6, a BRAM cache module 7, a modify write-back module 8, and a switching module 9.

[0032] The request queue module 5 can be a dedicated integrated chip, processor (CPU), logic processing module, etc. The request queue module 5 is used to encode the specific method steps for executing the request queue.

[0033] Search caching module 6 is a cache that executes the search caching steps of the present invention according to a preset program code.

[0034] BRAM cache module 7 is a cache that executes the caching steps of the present invention according to a preset program code.

[0035] Modification / write-back module 8 can be a dedicated integrated chip, processor (CPU), logic processing module, etc. Modification / write-back module 8 can execute the program code for modification / write-back steps.

[0036] The switching module 9 can be a dedicated integrated chip, a processor (CPU), a logic processing module, etc. The switching module 9 is capable of executing the program code for the switching operation of this invention.

[0037] The request queue module 5 is connected to the device's receive port, thereby receiving and caching memory allocation and deallocation requests input from the receive port. Failed allocation requests due to insufficient memory are also cached in the queue, while dequeued requests are added to the pipeline for computation. For example, the arithmetic unit PE communicates with the allocation unit via the AXI bus, sending memory allocation and deallocation request information to the receive port, and receiving the memory address and deallocation result. The request queue module 5 stores a request for three memory units and a deallocation request for a three-block memory block starting at memory unit 5.

[0038] DRAM storage module 4 is a DRAM dynamic random access memory. DRAM storage module 4 is at least divided into a static storage area 1, a dynamic storage area 2, and a multi-way search tree storage area 3. Static storage area 1 is used to store information that will not be released after being written. Specifically, static storage area 1 is used to store information that will not be released after being written, such as various calculation parameters. Dynamic storage area 2 is a dynamically managed memory area. Multi-way search tree storage area 3 is used to store search tree structure information. Specifically, multi-way search tree storage area 3 manages the search tree structure information at the node level based on a free node linked list. When retrieving a node, multi-way search tree storage area 3 retrieves the next node from the head of the free node linked list; when releasing a node, the empty node is reinserted into the head of the free node linked list.

[0039] The request queue module 5 establishes a connection with each search cache module 6. Preferably, the search cache modules 6 are configured as a multi-level structure with the same number of levels as the search tree, such as... Figure 1 As shown. After one of the search cache modules 6 analyzes the operator and node data, it passes the corresponding operator and the address of the node to be read to the adjacent search cache module 6 in a preset order. For example... Figure 1 As shown, the hierarchical number of search cache module 6 is calculated from top to bottom according to the direction of the arrows in the diagram. Operators and node data are passed from the search cache module 6 of the previous level to the search cache module 6 of the next level.

[0040] Each search cache module 6 establishes a connection with the BRAM cache module 7. Each search cache module 6 also establishes a connection with the DRAM storage module 4. The search cache module 6 reads node data from the DRAM storage module 4 based on the operator and node address passed from the previous search cache module and writes it to the BRAM cache module 7. The BRAM cache module 7 is used to cache node information on the search path and temporarily store modification information for the nodes.

[0041] Preferably, the modification write-back modules 8 are configured in a multi-layer structure with the same number of layers as the search tree. The BRAM cache module 7 is connected to each modification write-back module 8. Each modification write-back module 8 is connected to the DRAM storage module 4.

[0042] The modification write-back module 8 modifies the nodes in the BRAM cache module 7 according to the received operators, and writes the node data back to the multi-way search tree storage area 3 in the DRAM storage module 4.

[0043] The underlying search cache module 6 and the underlying modify-write-back module 8 are connected to the switching module 9. When the underlying search cache module 6 passes the memory block release operator to the switching module 9, the switching module 9 reverses the order of the operator passing and passes the operator to the modified-write-back module 8 connected to it.

[0044] In this invention, Figure 1 For example, if the search tree structure has 3 levels, then the search cache module 6 has 3 levels, and the write-back module 8 also has 3 levels. The levels are labeled 1, 2, and 3 from top to bottom. The hierarchical passing order of operators and node data in the search cache module 6 is 1→2→3. The hierarchical passing order of operators in the write-back module 8 is 3→2→1.

[0045] Modification write-back module 8 reads node data from BRAM cache module 7 and writes it back to DRAM storage module 4. After analyzing the operator and the read node, one of the modification write-back modules 8 passes the corresponding operator to the adjacent modification write-back module. Figure 1 Taking the transmission order shown as an example, if we follow the direction of the arrows in the diagram, the hierarchical number of the modification write-back module 8 is calculated from top to bottom. The operator passes the information from the bottom-level modification write-back module 8 to the next higher-level modification write-back module 8.

[0046] like Figure 1 As shown, the hierarchical transfer order of data in the search cache modules 6 is the reverse of the hierarchical transfer order of data in the modification write-back modules 8. In this invention... Figure 1 The hierarchical passing order is merely an example and not the only implementation method.

[0047] Preferably, the memory management method of the multi-way search tree storage area 3 is configured as follows: managing free memory blocks in memory based on the search tree structure.

[0048] A free memory block is the smallest unit of memory, and it is represented by its starting address and length. For example... Figure 2As shown, a memory block with a starting address of 22 and a length of 7 can be represented as (22, 7), and other memory blocks are represented similarly.

[0049] like Figure 3 As shown, each node in the search tree stores multiple free memory blocks. The number of free memory blocks in all tree nodes shares a common upper and lower bound. When the number of free memory blocks exceeds the upper bound, the tree node splits; when the number of free memory blocks is less than the lower bound, the tree nodes merge, ensuring that the number of free memory blocks in each tree node once again satisfies the upper and lower bound constraints.

[0050] When a tree node splits, a free memory block is inserted into its parent node. When a tree node is merged, a free memory block is deleted from its parent node.

[0051] A multi-way search tree is an ordered search tree where free memory blocks within each node are arranged in order of their starting addresses. The starting addresses of all free memory blocks between tree nodes are arranged in inorder chronological order. For example... Figure 3 As shown, the search tree is set with an upper bound of 2 and a lower bound of 1, and the free address blocks (1, 1) and (10, 3) within node 3d are arranged in order of their starting address size. The nodes 3a-3g also satisfy the inorder retrieval order.

[0052] The data item configuration of a multi-way search tree is as follows: Figure 4 As shown, it includes: the total number of valid free memory blocks in the tree node, the index of the free tree node linked list, the array of free memory blocks, the array of child node pointers, the array of the maximum memory block length of the child node, the maximum memory block length of the current node, the index of the maximum free memory block of the current node, the index of the maximum memory block of the child node, and the maximum memory block length of the child node.

[0053] A search tree structure is used to manage free memory blocks. Corresponding memory allocation and reclamation operation algorithms and bidirectional pipelines are designed. Both memory block allocation and reclamation can be completed within the high-order memory read and write operations of the tree, while avoiding backtracking traversal of the search tree.

[0054] In this invention, a memory allocation operation is used to delete at least one memory block via a bidirectional pipeline. A memory reclamation operation is used to insert at least one memory block via a bidirectional pipeline.

[0055] The present invention calculates the search tree in a bidirectional pipeline manner, and the specific steps are as follows.

[0056] S1: Search cache, executed by search cache module 6.

[0057] Search cache module 6 performs different types of searches on the search tree according to instructions, and the cache needs to modify the data used by write-back module 8 into BRAM cache module 7.

[0058] The search cache module 6 executes the search from the root of the search tree towards the leaves. The data to be cached includes at least: node, node address, sibling node address, search path, parent node's memory block, and search direction. The data that the search cache module 6 needs to pass to the next-level search cache module 6 includes: operator, address of the freed memory block, length of the freed memory block, address of the next-level node being searched, address of the next-level node's sibling node, and the free memory block to be passed to the next-level node.

[0059] Specifically, the search caching method is as follows.

[0060] The memory block release operation searches the search tree by address size, finding a downward search path and determining if the released memory block can be merged with adjacent memory blocks within the same node. If it can be merged with the two memory blocks to its left and right, the merge is performed, and a suitable successor memory block is searched downwards. If it can only be merged with one memory block, the successor or predecessor is searched downwards. If merging is not possible, the memory block release instruction is passed down. If the memory block overlaps with other memory blocks, a release failure operation is passed.

[0061] For memory allocation operations, the system checks if the largest memory block within the node can be allocated based on its index. If it is larger than the requested size, the allocation is completed, and the success message is passed down the node. If the largest memory block in the current node equals the requested size, the system searches for a successor memory block to replace it. If the largest memory block in the current node cannot meet the allocation requirement, the system searches for the largest memory block in the child nodes.

[0062] The same operations are passed down the search direction for finding the predecessor, finding the successor, finding the replacement memory block, allocation failure, and deallocation failure.

[0063] The search tree supports both worst-fits (allocating the largest memory block first) and first-fits (allocating the first memory block that meets the requirement) approaches. Furthermore, the representation method based on free memory blocks avoids internal fragmentation, thus improving memory utilization.

[0064] For example, taking the reclamation of memory block (3, 4) as an example, the search cache module 6 first caches node 3a, compares the starting address to obtain the node 3b that needs to be loaded in the next layer, and since memory block (3, 4) cannot be merged with memory block (30, 2), the same search operation is passed to the next layer search cache module 6. Subsequently, the search cache module reads in nodes 3b and 3d and performs the same operation.

[0065] S2: Operation switching, executed by operation switching module 9. This converts the downward search cache operation order to an upward modify-write-back operation order. This step does not involve specific nodes or memory accesses.

[0066] The memory block release operation is passed to the operation switching module 9, and is switched to an insertion operation to continue to the next level.

[0067] Specifically, the operation switching method is as follows.

[0068] The memory release operation is passed to the upper-level modification write-back module 8 for insertion operation. The released memory block is converted into the memory block inserted to the upper level, and the release success operation is passed up.

[0069] The process involves finding the predecessor and successor. If the parent free memory block is neither a predecessor nor a successor, the release success operation is passed up the hierarchy. If the parent free memory block is a predecessor or a successor, the delete free memory block operation is passed up the hierarchy.

[0070] Other operations are converted into corresponding failure operations and passed up to the next level.

[0071] S3: Modify and write back, executed by Modify and Write Back module 8.

[0072] The modification made to the next-level node is passed to the upper-level modification write-back module 8 and written back, and the data cached in the BRAM cache module 7 is written back to the DRAM. The execution direction is the opposite of step S1, and the path is the same as step S1.

[0073] The data passed to the upper-level modification write-back module 8 includes: operators, allocated addresses, addresses of nodes and sibling nodes, addresses of split nodes, memory blocks used for merging or replacement, memory blocks inserted upwards, and the maximum memory blocks of nodes and sibling nodes.

[0074] Specifically, the method for modifying and writing back is as follows.

[0075] The memory block replacement operation swaps the memory blocks uploaded by the child nodes with the corresponding memory blocks of the node, and then updates the maximum memory block length and the maximum memory block index of the node.

[0076] The memory block deletion operation removes the corresponding memory block from the node. If the number of memory blocks in the node is less than the lower bound after deletion, the corresponding memory block is inserted from the parent node. Sibling nodes upload a memory block to the parent node, and the memory block replacement operation is passed upwards. If the sibling node does not have enough memory blocks, the two nodes are merged, and the memory block is inserted from the parent node, and the memory block deletion operation is passed upwards.

[0077] The memory block insertion operation inserts a memory block into a child node. If the inserted memory block is larger than the upper bound, the node is split, and a memory block is inserted into the parent node. The insertion operation is then passed up the chain. If the memory block is not larger than the upper bound, the operation is passed up the chain.

[0078] The operation involves replacing the predecessor and successor memory blocks, replacing the corresponding memory blocks, updating the maximum memory block length of the node, and passing the operation upwards.

[0079] For example, when the insertion operation is passed to node 3d, it exceeds the node's upper bound of 2, so the node is split and a memory block is inserted into the parent node 3b. The same judgment and operation are performed on 3b and 3a.

[0080] After the above steps, the reclamation of memory block (3, 4) is complete. The memory allocation and reclamation processes are similar, that is, they are converted into deletion and insertion operations on the search tree through a bidirectional pipeline. Therefore, they will not be described in detail further.

[0081] It should be noted that the specific embodiments described above are exemplary. Those skilled in the art can devise various solutions inspired by the disclosure of this invention, and these solutions all fall within the scope of this invention and its protection. Those skilled in the art should understand that this specification and its accompanying drawings are illustrative and not intended to limit the scope of the claims. The scope of protection of this invention is defined by the claims and their equivalents. This specification contains multiple inventive concepts; terms such as "preferredly," "according to a preferred embodiment," or "optionally" indicate that the corresponding paragraph discloses an independent concept. The applicant reserves the right to file divisional applications based on each inventive concept.

Claims

1. A dynamic memory management device for high-level synthesis, characterized in that, The device includes at least: several search cache modules (6), several modification write-back modules (8), and a switching module (9). The search cache module (6) establishes a connection relationship with the DRAM storage module (4) and the BRAM cache module (7) respectively, and the modification write-back module (8) establishes a connection relationship with the DRAM storage module (4) and the BRAM cache module (7) respectively. The BRAM cache module (7) is used to cache the node information on the search path and temporarily store the modification information of the node. The search cache modules (6) are configured in a multi-level structure in the same manner as the number of levels in the search tree, and the modification write-back modules (8) are configured in a multi-level structure in the same manner as the number of levels in the search tree, wherein the hierarchical transmission order of the data of the search cache modules (6) is the opposite of the hierarchical transmission order of the data of the modification write-back modules (8). The search cache module (6) reads node data from the DRAM storage module (4) and writes it into the BRAM cache module (7) according to the received operator and node address. The modification write-back module (8) reads node data from the BRAM cache module (7) and writes it back to the DRAM storage module (4). The search cache module (6) and the modification write-back module (8) located at the bottom layer establish a connection relationship with the switching module (9). When the search cache module (6) located at the bottom layer passes the operator for releasing the memory block to the switching module (9), the switching module (9) switches the passing order of the operator to the reverse order and passes the operator to the modification write-back module (8) connected to it. The DRAM storage module (4) is divided into at least a static storage area (1), a dynamic storage area (2), and a multi-way search tree storage area (3); The static storage area (1) is used to store information that will not be released after being written. The dynamic storage area (2) is a dynamically managed memory area; The multi-way search tree storage area (3) is used to store search tree structure information, wherein the search tree structure information is managed at the node level based on the free node linked list. When extracting a node, the multi-way search tree storage area (3) extracts the next node from the head of the free node list, and when releasing a node, the empty node is reinserted into the head of the free node list.

2. The dynamic memory management device for high-level synthesis according to claim 1, characterized in that, After one of the search cache modules (6) analyzes the operator and the node data, the search cache module (6) will pass the corresponding operator and the node address to be read to the adjacent search cache module (6).

3. The dynamic memory management device for high-level synthesis according to claim 1 or 2, characterized in that, The modification write-back module (8) modifies the nodes in the BRAM cache module (7) according to the received operator and writes the node data back to the multi-way search tree storage area (3) in the DRAM storage module (4). After one of the modification-write-back modules (8) analyzes the operator and the read node, the modification-write-back module (8) passes the corresponding operator to the adjacent modification-write-back module.

4. The dynamic memory management device for high-level synthesis according to claim 1, characterized in that, The memory management method of the multi-way search tree storage area (3) is configured as follows: The system manages free memory blocks in memory based on a search tree structure. The free memory block is the smallest unit of memory, and it is represented by its starting address and length.

5. The dynamic memory management device for high-level synthesis according to claim 1 or 2, characterized in that, The device further includes a request queue module (5), which is connected to several of the search cache modules (6). The request queue module (5) is used to cache memory allocation requests and memory release requests sent by the computing unit, wherein, Failed allocation requests due to insufficient memory are cached in a queue. The dequeue allocation request is added to the pipeline for computation.

6. A dynamic memory management method for high-level synthesis, characterized in that, The method includes at least: Several search cache modules (6) are configured into a multi-level structure in the same way as the number of levels in the search tree. The modification write-back modules (8) are configured as a multi-level structure in the same way as the number of levels of the search tree, wherein the hierarchical transfer order of the data of the search cache modules (6) is the opposite of the hierarchical transfer order of the data of the modification write-back modules (8). The search cache module (6) reads node data from the DRAM storage module (4) and writes it into the BRAM cache module (7) according to the operator and node address passed from the previous layer. The BRAM cache module (7) caches node information on the search path and temporarily stores modification information of the nodes. The modification write-back module (8) reads node data from the BRAM cache module (7) and writes it back to the DRAM storage module (4). The search cache module (6) and the modification write-back module (8) located at the bottom layer establish a connection relationship with the switching module (9). When the search cache module (6) located at the bottom layer passes the operator for releasing the memory block to the switching module (9), the switching module (9) switches the passing order of the operator to the reverse order and passes the operator to the modification write-back module (8) connected to it. The DRAM storage module (4) is divided into at least a static storage area (1), a dynamic storage area (2), and a multi-way search tree storage area (3); The static storage area (1) is used to store information that will not be released after being written. The dynamic storage area (2) is a dynamically managed memory area; The multi-way search tree storage area (3) is used to store search tree structure information, and the memory management method of the multi-way search tree storage area (3) is configured as follows: The system manages free memory blocks in memory based on a search tree structure; wherein, the free memory block is the smallest unit of memory.

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