Display apparatus and method of operating the same

Abstract

A display device and an operating method thereof are provided. The display device includes a first gamma line providing a first gamma voltage, a second gamma line providing a second gamma voltage, a local tap line, a first switch configured to connect the first gamma line to the local tap line based on a tap division enable signal, and a second switch configured to connect the second gamma line to the local tap line based on the tap division enable signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0060684, filed on May 11, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to display devices and methods of operation thereof. Background Technology

[0004] Typically, a display device includes a display panel for displaying images and a display driving circuit for driving the display panel. The display driving circuit can receive image data from an external host and apply an image signal corresponding to the received image data to the source line of the display panel, thereby driving the display panel. Summary of the Invention

[0005] One or more example embodiments provide a display device and a method of operating thereof for rapidly stabilizing gamma voltage.

[0006] One or more example embodiments also provide a display device and a method of operation thereof for reducing additional current consumption while stabilizing gamma voltage.

[0007] According to one aspect of an example embodiment, a display device is provided, comprising: a first gamma line providing a first gamma voltage; a second gamma line providing a second gamma voltage; a partial contact line; a first switch configured to connect the first gamma line to the partial contact line based on a tap division enable signal; and a second switch configured to connect the second gamma line to the partial contact line based on the tap division enable signal.

[0008] According to one aspect of an example embodiment, a display device is provided, comprising: a gamma voltage generator configured to generate a gamma voltage; at least one first source driver disposed to the left of the gamma voltage generator, the at least one first source driver being configured to connect one of a plurality of first gamma lines corresponding to the gamma voltage to a corresponding first source channel based on first data; and at least one second source driver disposed to the right of the gamma voltage generator, the at least one second source driver being configured to connect the gamma line to the corresponding first source channel based on second data. One of the multiple second gamma lines corresponding to the voltage is connected to the corresponding second source channel; a first tap divider switch block is connected to the multiple first gamma lines; and a second tap divider switch block is connected to the multiple second gamma lines, wherein both the first tap divider switch block and the second tap divider switch block include: a first switch configured to connect the one first gamma line to a partial contact line in response to a tap divider enable signal; and a second switch configured to connect the one second gamma line to the partial contact line in response to the tap divider enable signal.

[0009] According to one aspect of an example embodiment, a method of operating a display device is provided, the method comprising: detecting a data pattern by comparing previous row data with current row data; and generating partial junctions between gamma lines based on the detected data pattern. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating a display device according to an example embodiment;

[0012] Figure 2A The example embodiment shows two source drivers configured side-by-side;

[0013] Figure 2B The stabilization time of the gamma lines of a conventional display device according to an example embodiment is shown;

[0014] Figure 3 This is a view illustrating the concept of a fast gamma-stabilized circuit (GFS) according to an example embodiment;

[0015] Figure 4 This is a view illustrating a voltage stabilization path using a fast gamma stabilization circuit (GFS) according to an example embodiment;

[0016] Figure 5A , Figure 5B and Figure 5C This is a view illustrating an embodiment of a data comparison method using a fast gamma-stabilized circuit;

[0017] Figure 6A This is a view illustrating a fast gamma-stabilized circuit for a data comparison method according to an example embodiment, and Figure 6B This is a timing diagram of the fast gamma stabilization circuit according to an example embodiment;

[0018] Figure 7A and Figure 7B This is a view illustrating the operation of data comparison logic according to an example embodiment;

[0019] Figure 8A and Figure 8B This is a view showing a fast gamma stabilization circuit 145b according to another example embodiment and its operation timing diagram;

[0020] Figure 9 This is a view comparing a prior art display device with an analog waveform of a display device according to an example embodiment;

[0021] Figure 10 This is a view showing the positions of the tap divider blocks according to an example embodiment;

[0022] Figure 11 This is a view showing the positions of the tap divider blocks according to an example embodiment;

[0023] Figure 12 This is a view showing the positions of the tap divider blocks according to an example embodiment;

[0024] Figure 13 This is a flowchart illustrating a method of operating a display device according to an example embodiment;

[0025] Figure 14 This is a view showing an electronic device according to an example embodiment. Detailed Implementation

[0026] In the following, exemplary embodiments will be described clearly and in detail with the aid of accompanying drawings to enable those skilled in the art to readily implement this disclosure.

[0027] Figure 1 This is a block diagram illustrating a display device 100 according to an example embodiment. (Refer to...) Figure 1The display device 100 may include a display panel 110, a gate driver 120, a source driver 130, a gamma voltage generator 140, a fast gamma stabilization circuit (GFS) 145, and a timing controller (TCON) 150.

[0028] Display panel 110 may include a plurality of pixels PX arranged in a matrix. In embodiments, display panel 110 may be implemented to display images in units of frames. For example, display panel 110 may be implemented as one of liquid crystal display (LCD), light-emitting diode (LED) display, organic LED (OLED) display, active matrix OLED (AMOLED) display, electrochromic display (ECD), digital mirror device (DMD), actuated mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD), and may also be implemented as other types of flat panel display or flexible display.

[0029] like Figure 1 As shown, the display panel 110 may include: gate lines GL1 to GLm (m is an integer of 2 or greater) arranged along the row direction, source lines SL1 to SLn (n is an integer of 2 or greater) arranged along the column direction, and pixels PX formed at the intersections of the gate lines GL1 to GLm and the source lines SL1 to SLn. In an embodiment, some pixels connected to the same gate line, having different colors, and being adjacent to each other can be configured as a unit pixel. Here, each of the pixels in a unit pixel may be referred to as a sub-pixel.

[0030] The gate driver 120 is implemented to select gate lines GL1 to GLm by providing a scan clock (or gate turn-on signal) to gate lines GL1 to GLm in response to a first control signal CTRL1 provided from the timing controller 150.

[0031] In this embodiment, one of the gate lines GL1 to GLm can be selected based on a scan clock output from the gate driver 120. Display operations can be performed by applying pixel signals (or image signals) corresponding to each pixel to the pixels of the horizontal line corresponding to the selected gate line via source lines SL1 to SLn. Source lines can also be referred to as source channels. In this embodiment, gate lines GL1 to GLm can be selected sequentially or non-sequentially.

[0032] The source driver 130 can be implemented to convert image data into pixel signals as analog signals (e.g., grayscale voltage or current corresponding to each pixel data) in response to a second control signal CTRL2, and to provide the pixel signals to source lines SL1 to SLn to drive the source lines SL1 to SLn. For example, the source driver 130 can charge the source lines SL1 to SLn based on the pixel signals. The source driver 130 can provide a pixel signal for one horizontal line to the source lines SL1 to SLn during one horizontal drive cycle. Thereafter, when a scan clock is provided, the source driver 130 can provide pixel signals to pixels of the horizontal lines corresponding to selected gate lines through the source lines SL1 to SLn.

[0033] The source driver 130 may include a plurality of amplifiers. In an embodiment, each of the plurality of amplifiers can provide a pixel signal to at least one corresponding source line. Here, the amplifier may be referred to as a channel amplifier or a source amplifier. In an embodiment, some of the plurality of amplifiers may be turned off while others may be turned on, depending on the pixel data. Here, some of the amplifiers that are turned on may drive two source lines.

[0034] The timing controller 150 can be implemented to control the overall operation of the display device 100. For example, the timing controller 150 can receive image data RGB and timing signals (e.g., horizontal synchronization signal HSYNC, vertical synchronization signal VSYNC, clock signal DCLK, and data enable signal DE) from an external device (e.g., a host device), and generate a first control signal CTRL1 and a second control signal CTRL2 for controlling the gate driver 120 and the source driver 130, respectively, based on the received image data RGB and timing signals.

[0035] The gamma voltage generator 140 can be implemented to generate and output gamma voltages corresponding to image data RGB. In an embodiment, the gamma voltage generator 140 can generate gamma voltages using a voltage divider method. In another embodiment, the gamma voltage generator 140 can output gamma voltages to multiple corresponding gamma lines GML.

[0036] The fast gamma stabilization circuit 145 can be implemented to quickly stabilize the gamma voltage corresponding to each gamma line GML.

[0037] Additionally, the timing controller 150 can convert the RGB format of image data received from the outside to match the interface specification of the source driver 130, and send the converted image data to the source driver 130. For example, the converted image data may include packet data.

[0038] The display device 100 may further include interface circuitry. The interface circuitry can be implemented to communicate with an external device (e.g., a host processor) and receive image data (RGB) and timing signals from the external device. In embodiments, the interface circuitry may include one of the following: an RGB interface, a CPU interface, a serial interface, a Mobile Display Digital Interface (MDDI), an Internal Integrated Circuit (I2C) interface, a Serial Peripheral Interface (SPI), a Microcontroller Unit (MCU) interface, a Mobile Industrial Processor Interface (MIPI), an Embedded Display Port (eDP) interface, a D-sub connector, an optical interface, or a High Definition Multimedia Interface (HDMI). Additionally, the interface circuitry may also include various serial or parallel interfaces.

[0039] exist Figure 1 In this embodiment, gate driver 120, source driver 130, gamma voltage generator 140, fast gamma stabilization circuit 145, and timing controller 150 are shown as different functional blocks. In this embodiment, the various components can be implemented as different semiconductor chips. In another embodiment, at least two of gate driver 120, source driver 130, gamma voltage generator 140, fast gamma stabilization circuit 145, and timing controller 150 can be implemented as a single semiconductor chip. For example, source driver 130 and timing controller 150 can be integrated into a single semiconductor chip. Furthermore, some components can be integrated onto display panel 110. For example, gate driver 120 can be integrated onto display panel 110.

[0040] Figure 2A Show Figure 1 The source drivers 130 are configured as side-by-side source drivers 130A and 130B. A gamma voltage generator 140 provides gamma voltage to the source drivers 130A and 130B via a gamma line GMLi. Similar to... Figure 1 DATA and CTRL2 from TCON are supplied to source drivers 130A and 130B. DATA is latched. Figure 2A The data is stored in a buffer (called a "data latch"). The output of each data latch is provided to a decoder. The output of each decoder is provided to an amplifier (AMP) that applies a gamma voltage to the source line. Figure 2A The diagram shows four example source lines, which are source channels Edge_Ch and Center_Ch.

[0041] Figure 2B The stabilization time of the gamma lines in a conventional display device is shown.

[0042] Generally, for high-frequency and high-resolution display drivers, the charging time of pixels on a single line of the panel continuously decreases. Furthermore, a greater number of source channels are required in the display driver circuit (DDI) to support high resolution. The increased number of source channels increases gamma load, thereby increasing the settling time of the gamma lines. This worsens the settling time of the source lines, potentially causing problems during rapid operation.

[0043] Due to RC delay, the gamma line of the source channel, structurally furthest from the gamma voltage generator, stabilizes the slowest. As a fast drive technique, a fast switching technique can be used to improve the output slew characteristics of the source amplifier (AMP). Even with such a fast switching technique, such as... Figure 2B As shown, if gamma stabilization is slow, the gamma stabilization time is a bottleneck in the source stabilization time due to the input delay of the source amplifier (AMP). Therefore, in order to improve the characteristics of IC output stabilization time, it is necessary to improve the gamma stabilization time in order to improve the characteristics of IC output stabilization time, given the increasing need to support high frequencies and high resolutions.

[0044] Figure 3 This is a view illustrating the concept of a fast gamma-stabilized circuit (GFS) according to an example embodiment.

[0045] Reference Figure 3 The Fast Gamma Stabilization Circuit (GFS) may include switches SW1 and SW2 connected in series between gamma tab lines TAPk and TAPk+1. The tab voltage is a boost voltage used to accelerate the gamma lines to an appropriate value. Here, gamma tab lines TAPk and TAPk+1 may correspond to gamma lines GMLk and GMLk+1. A first switch SW1 may be connected between gamma tab line TAPk and local tab line LTAPk. A second switch SW2 may be connected between gamma tab line TAPk+1 and local tab line LTAPk. In an embodiment, the first switch SW1 and the second switch SW2 may be turned on in response to a GFS enable signal EN. That is, in response to the GFS enable signal EN, the Fast Gamma Stabilization Circuit (GFS) can generate a local tab. Here, the generated local tab can create a high-speed AC path. The local tab line may also be referred to herein as a local boost line.

[0046] Switches SW1 and SW2 can receive voltages from gamma tap lines TAPk and TAPk+1, respectively. At the timing of each switch's turn-on, a local tap voltage can be generated using the resistive components of the switches through a resistor divider.

[0047] Furthermore, the k-th gamma tap line TAPk and the (k+1)-th gamma tap line TAPk+1 can be divided by resistors in a gamma voltage generator. The partial tap line LTAPk of the resistor divider can generate a low-speed DC path. As mentioned above, the partial tap line can also be referred to as the partial boost line in this paper.

[0048] Figure 4 This is a view illustrating a voltage stabilization path using a fast gamma stabilization circuit (GFS) according to an example embodiment.

[0049] Reference Figure 4 This illustrates the gamma line path when using a stable path and a stabilization function. In the prior art, a unidirectional stable path is formed in the gamma block. When using the stabilization function, the parasitic capacitance C stored in the line can be controlled by using the low-impedance resistor Rt of the switch. Line The DC voltage value is divided to generate a high-speed AC path. In other words, in addition to the existing stable DC path, an additional stability-related AC path can be generated. The settling-time characteristics of the gamma line can be improved through both the DC and AC paths.

[0050] The reason for using a switch instead of a resistor to generate the partial tap voltage here is to reduce the quiescent current caused by using a resistor through timing control. When performing such timing control, offset due to switch resistor mismatch can be prevented during voltage distribution using the switch. Referring to the switch's on / off timing control, the switch can be set to turn on at the point where gamma fluctuations due to data updates occur via a register. After the on-time timing operation, the off-time timing operation can be performed. Here, because the on / off operation is performed when the data changes, additional current consumption can be minimized in operations corresponding to gamma stabilization and panel charging current.

[0051] Typically, when data changes significantly, operations corresponding to the dynamic current generated during panel operation are included to minimize the additional current consumption of the GFS. However, when data remains constant, such as in monochromatic patterns, increased current consumption occurs due to the additional dynamic current generated by switch "on / off" operations. Therefore, data comparison methods can be applied to prevent increased current consumption due to GFS operations in modes with small data changes.

[0052] Figure 5A , Figure 5B and Figure 5C This is a view illustrating an embodiment of a data comparison method that applies a fast gamma-stabilized circuit.

[0053] Figure 5AIt is a symbolic representation of a screen display where the same intensity value spans the entire screen and changes at specific points along the line. For example... Figure 5A As shown, when the data variation in the channel is large (red dot), significant gamma fluctuations occur. Therefore, the source output also slows down due to the input delay of the source amplifier. Considering this, the GFS function can be activated when the data variation is large. Figure 5A The pixel intensity values ​​"Black", "68 Gray", "Black" and "128 Gray" are shown.

[0054] In addition, such as Figure 5B As shown, compared to the presence of fewer data variation channels (blue dotted line, "128 gray" spans almost all channels), when there are more data variation channels (red dotted line, "128 gray" does not span all channels), gamma fluctuations increase due to the increased load required for stabilization. Therefore, the gamma settling time delay increases. Considering... Figure 5A and Figure 5B Its characteristics mean that when the amount of data changes significantly, such as Figure 5C As shown, changes in the most significant two bits of data for each channel can be detected. Therefore, the amount of data change in each channel can be checked. However, it should be understood that data change detection is not limited to the most significant two bits of each channel. Figure 5B The pixel intensity values ​​"Black", "128 Gray", "Black" and "128 Gray" are shown.

[0055] The data comparison logic 152 can compare the previous channel data with the current channel data, determine the weight (high / low) of the data change based on the comparison result, count the number of channels with large data changes through the counter 153, and generate the GFS enable signal (also known as the "data comparison signal") COMP_EN when the count value is greater than the reference value.

[0056] Figure 6A This is a view illustrating a fast gamma stabilization circuit 145a according to an example embodiment of a data comparison method, and Figure 6B This is a timing diagram illustrating a fast gamma stabilization circuit 145a according to an example embodiment.

[0057] Reference Figure 6A The fast gamma stabilization circuit 145a may include a first switch SW1, a second switch SW2, and a logic circuit AND. The logic circuit AND generates a tap divider enable signal DIV_ENH by performing a logical operation on the GFS enable signal COMP_EN and the switch signal (also referred to as the "high-speed switch enable signal") FS_SW_EN. The first switch SW1 and the second switch SW2 can be turned on in response to the tap divider enable signal DIV_ENH.

[0058] Data can be updated in response to the data enable signal DE, and data can be sent to each source channel in response to the horizontal synchronization signal HSYNC. The GFS enable signal COMP_EN goes high when the count of the changed channel count exceeds a reference value, as shown below. Figure 6B As shown. When the GFS enable signal COMP_EN is high, the switch signal FS_SW_EN, which determines the on / off timing of switches SW1 / SW2, can turn on switches SW1 / SW2 of the GFS during the high-level timing period. When the tap divider enable signal DIV_ENH is high, the functional operation of the GFS (gamma fast stabilization operation) can be executed.

[0059] The fast gamma stabilization circuit 145a of the above data comparison method can control the GFS operation according to the data mode, thereby preventing unnecessary dynamic current.

[0060] Figure 7A and Figure 7B This is a view illustrating the operation of the data comparison logic according to an example embodiment. In this embodiment, the source driver can be applied in two groups, left and right. In this embodiment, changes can be checked in the (N-1)th row of data CH_DATA_PRE and the Nth row of data CH_DATA_CUR, which are the most significant two bits of the source channel. The GFS function can be operated when the number of channels in which the most significant two bits of data have changed is greater than the number of channels set in the register (e.g., 720).

[0061] Meanwhile, the switch of the fast gamma-stabilized circuit can be implemented as a transmission gate.

[0062] Figure 8A and Figure 8B This is a view showing a fast gamma stabilization circuit 145b according to another embodiment and its timing diagram.

[0063] Reference Figure 8A The fast gamma stabilization circuit 145b includes a first transmission gate TG1, a second transmission gate TG2, a first logic circuit NAND, and a second logic circuit INV.

[0064] The first transmission gate TG1 can be connected between the first gamma tap line TAPk and the local tap line LTAPk, responding to the tap division enable signal DIV_ENH and the inverted tap division enable signal DIV_ENHB. The second transmission gate TG2 can be connected between the second gamma tap line TAPk+1 and the local tap line LTAPk, responding to the tap division enable signal DIV_ENH and the inverted tap division enable signal DIV_ENHB.

[0065] The first logic circuit NAND can perform a first operation on the source output enable signal SD_SOUT_EN, the left most significant bit comparison signal MSB_COMP_EN_L, and the right most significant bit comparison signal MSB_COMP_EN_R to generate an inverting tap divider enable signal DIV_ENHB. According to embodiments of this disclosure, the left most significant bit comparison signal MSB_COMP_EN_L and the right most significant bit comparison signal MSB_COMP_EN_R can be based on, as follows: Figure 7A The comparison between the previous row data and the current row data is generated. The second logic circuit INV can invert the inverted tap divider enable signal DIV_ENHB to generate the tap divider enable signal DIV_ENH.

[0066] like Figure 8B As shown, when both the left most significant bit comparison signal MSB_COMP_EN_L and the right most significant bit comparison signal MSB_COMP_EN_R are high, the tap divider enable signal (DIV_ENH) responds to the data enable signal DE by being low for a predetermined time.

[0067] According to the example embodiment, the fast gamma stabilization circuit 145b can branch the gamma line during the routing of the gamma voltage to the source driver (using gamma taps). In the fast gamma stabilization circuit 145b, the switch can be located between adjacent tap voltages, thereby generating a first voltage of the first gamma tap line TAPk and a second voltage of the second gamma tap line TAPk+1, and providing this half voltage to the center gamma line.

[0068] Figure 9 This is a view comparing a prior art display device with a simulated waveform of a display device according to an example embodiment. Figure 9 The x-axis of the graph is marked using time units of 10u, 11u, 12u, and 13u.

[0069] Reference Figure 9 When using the worst gamma mode, such as the source output waveform, the settling time can be improved by approximately 554 ns (improvement rate: 22%).

[0070] Therefore, the same source characteristics can be satisfied at a 22% higher frequency. Thus, even at 144Hz, a 22% improvement in settling time can achieve the same effect as satisfying the source characteristics of the worst-case settling mode at 120Hz. In the case of GFS, it is a method to improve settling speed by directly generating voltage through a switch, in which the peak level of the gamma voltage change according to the data variation is lower than that of existing technologies, exhibiting optimal characteristics at the same initial speed.

[0071] The fast gamma stabilization circuit according to the example embodiments may be arranged differently within the DDI. Hereinafter, some embodiments of the fast gamma stabilization circuit are described as tap divider blocks within the DDI.

[0072] Figure 10 This is a view showing the positions of the tap divider blocks of the display device 200 according to an example embodiment. (Refer to...) Figure 10 Two source drivers 231-1 and 231-2 can be positioned on the left side of the gamma voltage generator 240, and two source drivers 232-1 and 232-2 can be positioned on the right side of the gamma voltage generator 240. The two source drivers 231-1 and 231-2 can be referred to as the two half-source drivers on the left side (i.e., SDRV_Half_L). The two source drivers 232-1 and 232-2 can be referred to as the two half-source drivers on the right side (i.e., SDRV_Half_R). A tap divider block TAB_DIV_SW 245 can be positioned between the two source drivers 231-1 and 231-2, and a tap divider block TAB_DIV_SW 246 can be positioned between the two source drivers 232-1 and 232-2.

[0073] In an embodiment, the tap divider switch block 245 or 246 may include a first switch block R-SW corresponding to red gamma R_GAMMA, a second switch block G-SW corresponding to green gamma G_GAMMA, and a third switch block B-SW corresponding to blue gamma B_GAMMA.

[0074] In an embodiment, each of the first switch block R-SW, the second switch block G-SW, and the third switch block B-SW may include a plurality of transmission gates connected in series for tap division.

[0075] Figure 11 This is a view showing the position of the tap divider switch blocks of the display device 300 according to an example embodiment. (Refer to...) Figure 11 Two source drivers 331-1 and 331-2 can be positioned on the left side of the gamma voltage generator 340, and two source drivers 332-1 and 332-2 can be positioned on the right side of the gamma voltage generator 340. Figure 10 Compared to those shown, tap divider block TAB_DIV_SW 345 can be set on the edges of the left source drivers 331-1 and 331-2, and tap divider block TAB_DIV_SW 346 can be set on the edges of the right source drivers 332-1 and 332-2.

[0076] exist Figure 10 and Figure 11In this embodiment, the tap divider block is configured using all the red gamma (R_GAMMA), green gamma (G_GAMMA), and blue gamma (B_GAMMA). However, the embodiment is not limited to this. In some embodiments, the tap divider block may be configured using at least one of the red gamma (R_GAMMA), green gamma (G_GAMMA), and blue gamma (B_GAMMA).

[0077] Figure 12 This is a view showing the position of the tap divider switch blocks of the display device 400 according to an example embodiment. (Refer to...) Figure 12 Two source drivers 431-1 and 431-2 can be positioned on the left side of the gamma voltage generator 440, and two source drivers 432-1 and 432-2 can be positioned on the right side of the gamma voltage generator 440. Figure 11 Compared to those shown, tap divider blocks TAB_DIV_SW 445 and 446 can be set using only the green gamma G_GAMMA.

[0078] Figure 13 This is a flowchart illustrating a method of operating a display device according to an example embodiment. (Refer to...) Figure 13 The display device can be operated as follows.

[0079] Each channel is provided to the display panel 110 (see Figure 1 Previous row data CH_DATA_PRE (see) Figure 7A The current row data CH_DATA_CUR to be provided to the display panel 110 can be compared (S110). By enabling the fast gamma stabilization circuit according to the data pattern or the number of variable channels as the comparison result, a partial cut can be generated between the gamma lines (S120).

[0080] Figure 14 This is a view showing an electronic device 2000 according to an example embodiment. (Refer to...) Figure 14 The electronic device (or mobile device) 2000 may include a processor AP 2100, a display driver circuit DDI 2200, a panel 2300, and a power supply circuit PMIC 2400.

[0081] Processor 2100 can be implemented to control the overall operation of electronic device 2000. In embodiments, processor 2100 can be implemented as an integrated circuit, system-on-a-chip, or mobile application processor (AP). Processor 2100 can send data to be displayed (e.g., image data, video data, or still image data) to display driver circuit 2200. In embodiments, data can be categorized into source data SD units corresponding to horizontal (or vertical) lines of display panel 2300.

[0082] The display driver circuit 2200 can transform the data sent from the processor 2100 into a form that can be sent to the display panel 2300, and then send the transformed data to the display panel 2300. The source data SD can be provided in pixels.

[0083] Furthermore, the display driver circuit 2200 can be implemented as a fast gamma stabilization circuit or may include the above-mentioned reference circuit. Figures 1 to 13 The description describes the tap division switch block.

[0084] The processor interface can interface with signals or data exchanged between the processor 2100 and the display driver circuit 2200. The processor interface can interface with source data SD (line data) sent from the processor 2100 and send the interfaced source data to the display driver circuit 2200. In embodiments, the processor interface can be an interface associated with a serial interface, such as a Mobile Industrial Processor Interface (MIPI), a Mobile Display Digital Interface (MDDI), a display port, or an embedded display port (eDP).

[0085] The display panel 2300 can use the gate signal GS to display the source data SD provided by the display driver circuit 2200.

[0086] The power supply circuit 2400 can be implemented to manage the power of an electronic device. In embodiments, the power supply circuit 2400 may include a power management integrated circuit (PMIC), a charger integrated circuit (IC), or a battery or fuel gauge. Furthermore, the power supply circuit 2400 may have wired and / or wireless charging methods. Wireless charging methods may include, for example, resonant magnetic coupling, inductive coupling, or electromagnetic wave methods, and may also include additional circuitry for wireless charging, such as a coil circuit, a resonant circuit, or a rectifier.

[0087] The power supply circuit 2400 can receive commands from the processor 2100 and supply power to each component of the electronic device. The power supply circuit 2400 can supply power to each of the display driver circuit 2200 and the display panel 2300. For example, the power supply circuit 2400 can provide an external voltage EV to the display driver circuit 2200. Here, the external voltage EV can be processed and used internally within the display driver circuit 2200. A power interface can be used between the power supply circuit 2400 and the display driver circuit 2200. For example, the power interface can send commands from the display driver circuit 2200 to the power supply circuit 2400. The power interface can exist separately from the processor interface. The display driver circuit 2200 can be directly connected to the power supply circuit 2400 without going through the processor 2100.

[0088] The dual-source driver according to the example embodiment can be applied to foldable smartphones. Typically, foldable smartphones can be implemented with various foldable display types such as C-INFOLD, C+1, G, C-OUTFOLD, S, etc. Generally, foldable smartphones can be categorized into in-fold and out-fold structures based on their folding method.

[0089] As described above, the display device and its operation method according to the example embodiment can stabilize the gamma voltage more quickly by performing tap division according to the data pattern.

[0090] The display device and its operation method according to the example embodiment can improve the stabilization time of the source output by rapidly stabilizing the gamma voltage.

[0091] The display device and its operation method according to the example embodiment can prevent additional power consumption due to gamma tapping by performing tapping via data comparison.

[0092] The display device and its operation method according to the example embodiment improve the stable timing of gamma routing by using timing control without causing quiescent current.

[0093] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A display device for displaying image data comprising multiple rows, the display device comprising: A first gamma line, the first gamma line providing a first gamma voltage; The second gamma line provides a second gamma voltage; Partial contact line, the partial contact line being configured to provide a boost voltage for accelerating the first gamma line to a predetermined value; A first switch is connected between the first gamma line and the partial contact line, and is configured to connect the first gamma line to the partial contact line for the first of the plurality of rows of the image data at a first time based on a tap division enable signal. as well as A second switch, connected between the second gamma line and the partial tap line, is configured to connect the second gamma line to the partial tap line for the first of the plurality of lines of the image data at a first time based on the tap division enable signal.

2. The display device according to claim 1, wherein, The first gamma voltage and the second gamma voltage are generated by a resistor voltage divider.

3. The display device according to claim 1, wherein, Both the first switch and the second switch include a transmission gate.

4. The display device according to claim 1, wherein, The tap split enable signal is generated based on a comparison between the previous row data and the current row data.

5. The display device according to claim 4, further comprising: A logic circuit configured to generate the tap division enable signal by performing a bitwise AND operation on a high-speed switch enable signal and a data comparison signal, and to output the tap division enable signal. The data comparison signal is generated based on the comparison between the previous row data and the current row data.

6. The display device according to claim 5, wherein, The data comparison signal is generated based on the fact that the difference between the most significant 2 bits of the previous row data and the most significant 2 bits of the current row data is equal to or greater than a reference value.

7. The display device according to claim 5, further comprising: Data comparison logic, which is configured as follows: For each of the multiple source channels, compare the previous row data with the current row data. A first number of source channels in the plurality of source channels whose difference between the previous row data and the current row data is equal to or greater than a reference value is counted, and... The data comparison signal is generated based on the fact that the first number of source channels exceeds a threshold.

8. The display device according to claim 7, wherein, The reference value is 4, and the threshold is 720.

9. The display device according to claim 4, further comprising: A first logic circuit is configured to output an enable signal, a left most significant bit enable signal, and a right most significant bit enable signal to the source, and perform a NAND operation. as well as An inverter configured to generate and output the tap divider enable signal by inverting the output value from the first logic circuit.

10. The display device of claim 1, further comprising a decoder configured to receive row data and connect one of a plurality of gamma lines to a source channel corresponding to the row data.

11. A display device, comprising: A gamma voltage generator, the gamma voltage generator being configured to generate a gamma voltage; At least one first source driver is disposed on the left side of the gamma voltage generator, and the at least one first source driver is configured to connect one of a plurality of first gamma lines corresponding to the gamma voltage to a corresponding first source channel based on first data. At least one second source driver is disposed on the right side of the gamma voltage generator, and the at least one second source driver is configured to connect one of a plurality of second gamma lines corresponding to the gamma voltage to a corresponding second source channel based on second data. A first tap divider switch block is connected to the plurality of first gamma lines; as well as The second tap divider switch block is connected to the plurality of second gamma lines. Both the first tap division switch block and the second tap division switch block include: A first switch, configured to connect a first gamma line to a partial tap line in response to a tap divider enable signal; and A second switch is configured to connect a second gamma line to the partial tap line in response to the tap divider enable signal.

12. The display device according to claim 11, wherein, Each of the at least one first source driver and the at least one second source driver includes two half-source drivers, and The first tap divider block is disposed between the two half-source drivers of the at least one first source driver, and the second tap divider block is disposed between the two half-source drivers of the at least one second source driver.

13. The display device according to claim 11, wherein, Each of the at least one first source driver and the at least one second source driver includes two half-source drivers, and The first tap divider block is disposed outside the two half-source drivers of the at least one first source driver, and the second tap divider block is disposed outside the two half-source drivers of the at least one second source driver.

14. The display device according to claim 11, wherein, Both the first tap divider block and the second tap divider block include: The first switching block corresponds to the red gamma voltage; A second switching block, the second switching block corresponding to the green gamma voltage; and The third switching block corresponds to the blue gamma voltage.

15. The display device according to claim 11, wherein, Each of the first tap divider switch block and the second tap divider switch block includes at least one of a first switch block corresponding to a red gamma voltage, a second switch block corresponding to a green gamma voltage, and a third switch block corresponding to a blue gamma voltage.

16. A method of operating a display device for displaying image data comprising multiple rows, the method comprising: Data patterns are detected by comparing previous row data with current row data. as well as A partial junction is generated between the first gamma line and the second gamma line based on the detected data pattern. The partial connection is configured to provide a boost voltage to accelerate the first gamma line to a predetermined value.

17. The method of claim 16, wherein, The detection data mode includes: comparing at least one most significant bit of the previous row data with at least one most significant bit of the current row data.

18. The method according to claim 16, wherein, The detection data mode includes: generating a tap division enable signal based on the difference between the previous row data and the current row data being equal to or greater than a reference value, and The partial tap is generated based on the tap division enable signal.

19. The method of claim 16, wherein, The detection data modes include: Count the number of source channels whose difference between the previous row data and the current row data is equal to or greater than a reference value; and If the number of source channels exceeds a threshold, a tap division enable signal is generated. The partial tapping is generated based on the tapping enable signal.

20. The method according to claim 19, wherein, The local connection corresponds to at least one of the red gamma voltage, green gamma voltage, and blue gamma voltage.

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