A CMOS Direct-Integrated Infrared Detector Structure and its Fabrication

Abstract

This invention provides a CMOS directly integrated infrared detector structure and its fabrication process, comprising a CMOS infrared detection structure and a CMOS measurement circuit system. Both the CMOS infrared detection structure and the CMOS measurement circuit system are fabricated using CMOS technology. The CMOS infrared detection structure is directly integrated onto a single-crystal silicon / silicon dioxide layer outside the CMOS measurement circuit system. A metal electrode or a conductive layer is disposed on the silicon dioxide layer, which can be connected to the CMOS measurement circuit system for signal transmission. A thermoelectric material layer is disposed on the metal electrode or conductive layer, serving as the photosensitive part of the entire infrared detector. A conductive glass layer is disposed on the thermoelectric material layer. This invention features direct integration with CMOS, resulting in a small pixel pitch and enabling the fabrication of ultra-large pixel f-aperture detectors (FPAs). This invention also offers low fabrication costs, low requirements for material single-crystal properties, a miniaturized device structure, and simple operation.

Description

Technical Field

[0001] This invention relates to the field of infrared detector technology, and specifically to a CMOS directly integrated infrared detector structure and its process. Background Technology

[0002] Infrared detectors have wide applications in infrared night vision, infrared guidance, autonomous driving, medical diagnosis, environmental monitoring, industrial monitoring, and astronomical exploration. However, traditional infrared detectors typically require low-temperature operating environments and are costly to manufacture, hindering practical applications. The fabrication of short-wave infrared (SWIR), mid-wave infrared (MWIR), or long-wave infrared (LWIR) detectors faces certain challenges due to factors such as operating environment, detector performance, and manufacturing cost. The problems limiting the development of traditional infrared detectors are as follows:

[0003] (1) Low operating temperature. To provide a good signal-to-noise ratio, the operating temperature is generally less than 200K, such as InGaAs SWIR infrared detectors, HgCdTe MWIR infrared detectors, etc., especially LWIR infrared detectors, which need to operate below 77K. Due to the need for additional cooling equipment, the size, weight, power consumption and cost of infrared detectors increase accordingly, and their application scenarios are also limited.

[0004] (2) Complex fabrication process. The fabrication process of traditional infrared detectors consists of CMOS (Complementary Metal-Oxide-Semiconductor) and MEMS (Micro-Electro-Mechanical System) fabrication. Therefore, the manufacturing process requires the independent fabrication of CMOS readout circuit system, MEMS thermal insulation microbridge, amorphous silicon thermistor and infrared absorption layer, etc., and it is not possible to directly integrate infrared sensor on CMOS.

[0005] (3) High cost. Focal plane array (FPA) is the core component of the thermal phase system of infrared detectors, which can detect, identify and analyze the infrared information of the object being measured. However, the manufacturing process of FPA requires complex processes such as epitaxial growth of crystal substrate, mold hybridization, substrate thinning technology and anti-reflection coating technology. Its manufacturing (e.g., only a single FPA can be produced at a time, and multiple FPAs cannot be directly prepared) and assembly (e.g., the phase spacing is greater than 10μm) are very expensive.

[0006] (4) High material quality requirements. Traditional infrared detectors rely on photosensitive materials (such as HgCdTe). The working principle is that after the material is exposed to infrared radiation, non-equilibrium charge carriers are generated in the pn junction region, forming a built-in electric field. The charge carriers drift in this region, thereby changing the electric field distribution in space. Therefore, the material is required to have good single crystal properties. Summary of the Invention

[0007] The purpose of this invention is to provide a CMOS directly integrated infrared detector structure and its process to solve the problems of low operating temperature, high cost, and inability to directly achieve CMOS integration in traditional infrared detectors. The aim is to realize a room temperature operating, low-cost, and CMOS directly integrated infrared detector structure with wafer-level FPA and spectral response range of SWIR, MWIR, LWIR single band or wide band.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a CMOS directly integrated infrared detector structure, comprising a CMOS infrared detection structure and a CMOS measurement circuit system, wherein both the CMOS infrared detection structure and the CMOS measurement circuit system are fabricated using CMOS technology; the CMOS infrared detection structure is directly integrated on a single-crystal silicon / silicon dioxide layer outside the CMOS measurement circuit system, wherein a metal electrode or a conductive layer is disposed on the silicon dioxide layer, and the metal electrode or conductive layer can be connected to the CMOS measurement circuit system for signal transmission; a thermoelectric material layer is disposed on the metal electrode or conductive layer, and the thermoelectric material layer serves as the photosensitive part of the entire infrared detector; a conductive glass layer is disposed on the thermoelectric material layer.

[0009] Furthermore, the CMOS measurement circuit system includes at least one hermetically sealed release isolation layer, which is used to protect the CMOS measurement circuit system from the influence of the process during the fabrication of the CMOS infrared detection structure.

[0010] The present invention also provides a fabrication process for the above-mentioned CMOS directly integrated infrared detector structure, including substrate pretreatment, preparation of metal electrodes or conductive layers and growth of thermoelectric materials;

[0011] The substrate fabrication includes a monocrystalline silicon layer, a silicon dioxide layer, and a heat sink layer. The thickness of the monocrystalline silicon layer is 400 μm to 600 μm, and its dimensions are 1 mm to 30 mm in width and 1 mm to 30 mm in length. The thickness of the silicon dioxide layer is 100 nm to 1000 nm, and its dimensions are the same as those of the monocrystalline silicon layer, with a width and length of 1 mm to 30 mm. Three heat sink layers are embedded in the silicon dioxide layer. Each heat sink layer has a thickness of 20 to 100 nm, a width of 0.1 mm to 1 mm, and a length of 1 mm to 30 mm. The interlayer width is 20 nm to 50 nm, and the inter-group width is 0.1 mm to 5 mm. The two groups of heat sink layers are symmetrically distributed. The metal electrode or conductive layer can be fabricated using one of the following techniques: vapor deposition, transfer deposition, or growth deposition. The fabrication environment for the metal electrode or conductive layer must meet the requirement of a vacuum degree < 10. -3pa;

[0012] The heat sink layer is one of tungsten, copper-tungsten alloy, molybdenum, and copper-molybdenum alloy;

[0013] The metal electrode has the following dimensions: thickness 100nm~500nm, width 1μm~3mm, and length 1μm~3cm;

[0014] The metal electrode is at least one of copper, aluminum, gold, silver, chromium, cadmium, nickel, titanium, and platinum;

[0015] The conductive layer has the following dimensions: thickness 100nm~1000nm, width 10μm~3cm, and length 10μm~3cm;

[0016] The conductive layer is one of graphene, ZnO, SnO2, and TiO2.

[0017] The metal electrode or conductive layer can be prepared using one of the following techniques: vapor deposition, transfer deposition, or growth deposition; the preparation environment for the metal electrode or conductive layer must meet the requirement of a vacuum degree <10. -3 Pa;

[0018] The growth of the thermoelectric material includes the following steps:

[0019] Step 1: Substrate cleaning. Immerse the silicon / silicon dioxide substrate in anhydrous ethanol and ultrasonically clean for 0.1 to 10 hours. Remove residues on the silicon wafer with deionized water and air dry with inert gas.

[0020] Step 2: Material preparation. Depending on the substrate size, 0.1 to 0.3 grams of precursor powder should be prepared per square centimeter and placed in a quartz crucible.

[0021] Step 3, chemical vapor deposition, includes adjusting the position of the substrate and material in the chemical vapor deposition furnace, controlling the furnace vacuum to reach a predetermined value, introducing a certain flow rate of argon or nitrogen, and completing the growth according to the set heating process;

[0022] The gas flow rate is 50 sccm to 450 sccm. The heating parameters include the starting temperature, the ending temperature, the heating time, and the temperature holding time. The starting temperature is room temperature, the ending temperature is 500℃ to 900℃, the heating time is 30 minutes to 120 minutes, and the temperature holding time is 1 minute to 1 hour.

[0023] The thermoelectric material enables the CMOS infrared detector to operate based on the thermoelectric effect, including at least one of bismuth telluride and its alloys, lead telluride and its alloys, silicon-germanium alloys, carbon nanotubes, bismuth nanowires, lead selenide, lead selenide-sulfur, and lead sulfide.

[0024] The thermoelectric material is coated with an indium tin oxide (ITO) conductive glass layer by magnetron sputtering.

[0025] The conductive glass layer has the following dimensions: thickness 100nm–1000nm, width 10μm–3cm, and length 10μm–3cm.

[0026] The infrared detector pixel array is arranged by etching the above-mentioned material using wafer-level technology, and the resulting pixel pitch is 3μm to 10μm. FPA can prepare arrays ranging from 1 pixel × 1 pixel to 300 pixels × 300 pixels as required.

[0027] The solution provided by this invention exhibits the following performance characteristics in the SWIR band: quantum efficiency > 70%, operating temperature > 298 K, and D* > 10. 12 Jones, spectral response range 0.4μm~2.5μm, dark current density <10nA / cm 2 ;

[0028] The solution provided by this invention exhibits the following performance characteristics in the MWIR band: quantum efficiency > 70%, operating temperature ≥ 270 K, and D* > 10. 10 Jones, spectral response range 3-5μm, noise equivalent temperature difference ≤50mK;

[0029] The solution provided by this invention exhibits the following performance characteristics in the LWIR band: quantum efficiency > 50%, operating temperature > 298 K, and D* > 10. 8 Jones, spectral response range 8.0–12.0 μm, dark current <0.05 A / cm 2 .

[0030] Compared with the prior art, the beneficial effects of the present invention are:

[0031] (1) Direct integration with CMOS, small pixel pitch, enabling the fabrication of ultra-large pixel FPA;

[0032] (2) Low preparation cost, low requirement for single crystallization of materials, small device structure, and simple operation;

[0033] (3) It is operable at room temperature and has a wide range of applications;

[0034] (4) It has a wide spectral response range, covering short-wave infrared, mid-wave infrared and long-wave infrared. Attached Figure Description

[0035] Figure 1 This is a cross-sectional structural diagram of a CMOS directly integrated infrared detector pixel according to Embodiment 1 of the present invention.

[0036] Figure 2This is a schematic diagram of the structure of a CMOS directly integrated infrared detector according to Embodiment 1 of the present invention;

[0037] Figure 3 This is a cross-sectional view of another CMOS directly integrated infrared detector pixel according to Embodiment 2 of the present invention.

[0038] Illustrations: 1. Infrared detector pixel; 11. Conductive glass layer; 12. Thermoelectric material layer; 13. Electrode structure; 2. CMOS substrate; 21. Heat sink layer group one; 22. Heat sink layer group two; 3. CMOS readout circuit; 4. Pixel array of CMOS directly integrated infrared detector. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings.

[0040] Example 1

[0041] Figure 1 This is a schematic cross-sectional view of a CMOS directly integrated infrared detector pixel. Figure 2 This is a schematic diagram of a CMOS directly integrated infrared detector FPA. The infrared detector system includes: an infrared detector pixel 1 based on thermoelectric materials, a CMOS substrate 2, a CMOS readout circuit 3, and a pixel array 4 of the CMOS directly integrated infrared detector. The specific implementation steps are as follows:

[0042] Step 1: Prepare a silicon / silicon dioxide substrate with a width of 10 mm, a length of 10 mm, a silicon wafer thickness of 400 μm, a silicon dioxide layer thickness of 100 nm, a heat sink layer thickness of 20 nm, a width of 0.2 mm, a length of 10 mm, an interlayer width of 20 nm, and an intergroup width of 2 mm. Integrate a CMOS readout circuit 3 in the substrate.

[0043] Step 2: Ultrasonically clean the silicon / silicon dioxide substrate for 0.5 hours, remove it after cleaning, and air dry it with nitrogen.

[0044] Step 3: A copper metal electrode, i.e., electrode structure 13, is deposited on the silicon / silicon dioxide substrate prepared in step 2 using vapor deposition technology. The preparation environment has a vacuum degree of 3×10⁻⁶. -4 Pa, the copper metal electrode has a thickness of 200 nm, a width of 1.5 μm, and a length of 1 cm;

[0045] Step 4: Prepare 0.1 grams of lead selenide powder and place it in a quartz crucible;

[0046] Step 5: Place the substrate and material sequentially into the chemical vapor deposition furnace, adjust their positions, evacuate the furnace, then introduce argon gas at a flow rate of 150 sccm, and begin heating. The heat treatment process is as follows: initial temperature is room temperature, final temperature is 800℃, heating time is 30 minutes, and temperature holding time is 10 minutes.

[0047] Step 6: Deposit an ITO conductive glass layer 11 with a thickness of 200nm, a width of 0.8cm, and a length of 1cm on the thermoelectric material layer 12 prepared in step 5. The conductive glass layer 11 and the thermoelectric material layer 12 form an infrared detector pixel 1. Connect a CMOS readout circuit 3 to the conductive glass layer 11 and the electrode structure 13 respectively.

[0048] Step 7: Wrap an insulating layer around the CMOS readout circuit 3;

[0049] Step 8: Use an etching process to produce an FPA with a pixel pitch of 8μm and a pixel array of 20 pixels × 20 pixels on the above material.

[0050] The solution provided in Example 1 has SWIR band performance, quantum efficiency >75%, operating temperature of 298K, and D* ~1.2×10⁻⁶. 12 Jones, with a spectral response range of 1.0–2.5 μm and a dark current density of 5 nA / cm². 2 .

[0051] Example 2

[0052] Figure 3 This is a cross-sectional schematic diagram of another type of CMOS directly integrated infrared detector pixel, showing the infrared detector FPA structure and... Figure 2 The specific implementation steps are as follows:

[0053] Step 1: Prepare a silicon / silicon dioxide substrate with a width of 15 mm, a length of 15 mm, a silicon wafer thickness of 500 μm, a silicon dioxide layer thickness of 150 nm, a heat sink layer thickness of 30 nm, a width of 0.3 mm, a length of 15 mm, an interlayer width of 20 nm, and an intergroup width of 2 mm. Integrate a CMOS readout circuit 3 in the substrate.

[0054] Step 2: Ultrasonically clean the silicon / silicon dioxide substrate for 1 hour, then remove it and air dry it with argon gas.

[0055] Step 3: Transfer a graphene buffer layer, i.e., electrode structure 13, onto the silicon / silicon dioxide substrate prepared in Step 2 using vapor deposition technology. The preparation environment has a vacuum degree of 10. -5 Pa, the graphene layer is 100 nm thick, 1.5 cm wide, and 1.5 cm long;

[0056] Step 4: Prepare 0.5 grams of selenium-sulfur-lead powder and place it in a quartz crucible;

[0057] Step 5: Place the substrate and material sequentially into the chemical vapor deposition furnace, adjust their positions, evacuate the furnace, then introduce argon gas at a flow rate of 180 sccm, and begin heating. The heat treatment process is as follows: initial temperature is room temperature, final temperature is 800℃, heating time is 30 minutes, and temperature holding time is 30 minutes.

[0058] Step 6: Deposit an ITO conductive glass layer 11 with a thickness of 100nm, a width of 1.5cm, and a length of 1cm on the thermoelectric material layer 12 prepared in step 5. The infrared detector pixel 1 is composed of the conductive glass layer 11, the thermoelectric material layer 12, and the electrode structure 13. CMOS readout circuit 3 is connected to the conductive glass layer 11 and the electrode structure 13 respectively.

[0059] Step 7: Wrap an insulating layer around the CMOS readout circuit 3;

[0060] Step 8: Use an etching process to produce an FPA with a pixel pitch of 5μm and a pixel array of 50 pixels × 50 pixels on the above material.

[0061] The solution provided in Example 2 has MWIR band performance, quantum efficiency >75%, operating temperature of 298K, and D* ~2×10⁻⁶. 12 Jones, with a spectral response range of 3–5 μm and a noise equivalent temperature difference ≤ 50 mK.

[0062] Example 3

[0063] Step 1: Prepare a silicon / silicon dioxide substrate with a width of 20 mm, a length of 20 mm, a silicon wafer thickness of 450 μm, a silicon dioxide layer thickness of 200 nm, a heat sink layer thickness of 40 nm, a width of 0.5 mm, a length of 20 mm, an interlayer width of 20 nm, and an intergroup width of 2 mm. Integrate a CMOS readout circuit 3 in the substrate.

[0064] Step 2: Ultrasonically clean the silicon / silicon dioxide substrate for 2 hours, remove it after cleaning, and air dry it with nitrogen.

[0065] Step 3: A silver metal electrode, i.e., electrode structure 13, is deposited on the silicon / silicon dioxide substrate prepared in step 2 using vapor deposition technology. The preparation environment has a vacuum degree of 10. -4 Pa, the silver metal electrode has a thickness of 300 nm, a width of 2 μm, and a length of 2 cm;

[0066] Step 4: Prepare 0.6 grams of silicon-germanium powder (Si... 1-x Ge x (x = 0.5), placed in a quartz crucible;

[0067] Step 5: Place the substrate and material sequentially into the chemical vapor deposition furnace, adjust their positions, evacuate the furnace, then introduce argon gas at a flow rate of 120 sccm, and begin heating. The heat treatment process is as follows: initial temperature is room temperature, final temperature is 600℃, heating time is 60 minutes, and temperature holding time is 20 minutes.

[0068] Step 6: Evaporate an ITO conductive glass layer 11 with a thickness of 200nm, a width of 1.8cm, and a length of 2cm onto the thermoelectric material layer 12 prepared in step 5. The conductive glass layer 11 and the thermoelectric material layer 12 form an infrared detector pixel 1. CMOS readout circuit 3 is connected to the conductive glass layer 11 and the electrode structure 13 respectively.

[0069] Step 7: Wrap an insulating layer around the CMOS readout circuit 3;

[0070] Step 8: Use an etching process to produce an FPA with a pixel pitch of 4μm and a pixel array of 50 pixels × 50 pixels on the above material.

[0071] The solution provided in Example 3 has LWIR band performance, quantum efficiency >60%, operating temperature of 298K, and D*~10 9 Jones, spectral response range 8.0–10.0 μm, dark current density 0.04 A / cm². 2 .

[0072] The above description merely illustrates preferred embodiments of the present invention, and while the description is relatively specific and detailed, it should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications, improvements, and substitutions without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A CMOS directly integrated infrared detector structure, characterized by: The CMOS infrared detection structure and the CMOS measurement circuit system are prepared by using a CMOS process; the CMOS infrared detection structure is directly integrated on a monocrystalline silicon / silicon dioxide layer outside the CMOS measurement circuit system, one of a metal electrode or a conductive layer is arranged on the silicon dioxide layer, the metal electrode or the conductive layer can be connected with the CMOS measurement circuit system and used for signal transmission; a thermoelectric material layer is arranged on the metal electrode or the conductive layer, and the thermoelectric material layer serves as a photosensitive part of the entire infrared detector; a conductive glass layer is arranged on the thermoelectric material layer. The thermoelectric material includes at least one of bismuth telluride and an alloy thereof, lead telluride and an alloy thereof, a silicon germanium alloy, a nanometer carbon tube, a bismuth nanowire, lead selenide, lead selenide sulfide and lead sulfide. The silicon dioxide layer is embedded with at least two groups of heat sink layers, each group of heat sink layers includes multiple layers of heat sink layers, and the two groups of heat sink layers are symmetrically distributed.

2. The CMOS directly integrated infrared detector structure of claim 1, wherein: The CMOS measurement circuit system includes at least one closed release isolation layer, which is used to protect the CMOS measurement circuit system from the process during the preparation of the CMOS infrared detection structure.

3. A process for fabricating a CMOS directly integrated infrared detector structure as claimed in claims 1-2, characterized in that: The substrate pretreatment, the preparation of the metal electrode or the conductive layer and the growth of the thermoelectric material are included. The substrate pretreatment includes the preparation of a monocrystalline silicon layer, a silicon dioxide layer and a heat sink layer. The metal electrode or conductive layer is prepared by one of evaporation, transfer or growth techniques, and the preparation environment of the metal electrode or conductive layer needs to satisfy the vacuum degree < 10 -3 Pa. The growth of the thermoelectric material includes the following steps: Step 1, substrate cleaning, the silicon / silicon dioxide substrate is soaked in anhydrous ethanol and ultrasonically cleaned for 0.1-10 hours, residual materials on the silicon wafer are removed by using deionized water, and the silicon wafer is dried by using an inert gas; Step 2, material configuration, 0.1-0.3 grams of material precursor powder per square centimeter is configured according to the size of the substrate and is placed in a quartz crucible; Step 3, chemical vapor deposition, including adjusting the positions of the substrate and the material in a chemical vapor deposition furnace, controlling the vacuum degree of the furnace body to reach a predetermined value, introducing argon or nitrogen gas with a flow rate of 50-450 sccm, and completing the growth according to a set heating process, the heating parameters including a starting temperature of room temperature, a final temperature of 500-900°C, a heating time of 30-120 minutes and a temperature maintenance time of 1 minute-1 hour.

4. The process for fabricating a CMOS integrated infrared detector structure according to claim 3, wherein: The heat sink layer is one of tungsten, copper tungsten alloy, molybdenum and copper tungsten alloy.

5. The process for fabricating a CMOS integrated infrared detector structure according to claim 3, wherein: The size of the metal electrode is 100-500 nm in thickness, 1-3 mm in width and 1-3 cm in length, the metal electrode is at least one of copper, aluminum, gold, silver, chromium, cadmium, nickel, titanium and platinum, the size of the conductive layer is 100-1000 nm in thickness, 10-3 cm in width and 10-3 cm in length, and the conductive layer is one of graphene, ZnO, SnO2 and TiO2.

6. The process for fabricating a CMOS integrated infrared detector structure according to claim 3, wherein: The size of the conductive glass layer is 100-1000 nm in thickness, 10-3 cm in width and 10-3 cm in length.

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