A command preprocessing method based on NAND Flash AIPR

Abstract

This invention provides a command preprocessing method based on NAND Flash AIPR. A channel connects K NAND flash chips (devices), each NAND chip includes L targets, each target contains M LUNs, and each LUN has N planes, where K, L, M, and N are all values ​​greater than or equal to 1. In this invention, commands are first preprocessed according to the type and address information of the commands issued by the firmware (FW), and then transmitted to the hardware module for processing. This invention pre-sorts spread read commands, allowing multiple spread read commands for the same target and LUN but different planes to be sent to the NAND as a single command group. This not only saves command channel resources but also improves the read rate. After pre-sorting non-read type commands, the LUN addresses of adjacent commands are likely to remain different, ensuring that the commands sent to the hardware module meet the requirements of parallel execution of multiple LUNs as much as possible, thereby improving the command execution rate and further enhancing SSD performance.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to a command preprocessing method based on Nand Flash AIPR. Background Technology

[0002] Typically, NAND flash chips are also called device / packages. Each device contains one or more targets, and each target consists of one or more LUNs. A LUN is the smallest unit of independent command execution within the NAND flash. A LUN can have multiple planes, each composed of hundreds or even thousands of blocks. Each plane has its own page register and cache register. The page register caches data written to or read from the NAND flash. Therefore, based on this NAND flash structure, not only can parallel operations across multiple LUNs be implemented, but independent read operations across different planes within the same LUN can also be achieved.

[0003] Currently, SSDs primarily perform read, write, and erase operations on NAND flash memory using a command-address approach. Address information includes target, LUN, plane, block, page, and column addresses. Common commands include singleplane (sp) read / write / erase, multiple plane (mp) read / write / erase, and AIPR. sp performs a read operation on only one plane within a LUN at a time; while mp can perform operations on multiple planes within a LUN, it requires setting the same page address; AIPR is a flexible mp read operation that can independently read different pages on multiple planes within the same LUN, significantly improving SSD read speeds compared to mp read. Given that NAND flash memory supports AIPR technology, preprocessing commands issued by the firmware (FW) is an effective method to improve SSD performance. Summary of the Invention

[0004] In view of this, the purpose of this invention is to propose a command preprocessing method based on NAND Flash AIPR. Taking advantage of the multi-LUN parallel mechanism and AIPR support of NAND Flash, the method preprocesses the commands issued by the server (FW) before sending them to the hardware module to control the NAND Flash to perform corresponding operations. The main innovation of this invention lies in proposing a command pre-sorting method and introducing an implementation process. This method not only saves command channel resources but also improves the command execution speed and data channel utilization of the SSD.

[0005] To achieve the above objectives, the present invention provides a command preprocessing method based on Nand Flash AIPR, which includes the following steps:

[0006] The commands are preprocessed and sorted according to the type and address information of the commands issued by the FW, and then transmitted to the hardware module for processing.

[0007] The sorted commands are sent to the hardware module in sequence. When the hardware module detects that the continue number value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group.

[0008] As a further aspect of the present invention, a channel connects K Nand flash chips, each Nand chip includes L targets, each target contains M LUNs, and each LUN has N planes.

[0009] As a further aspect of the present invention, in a channel connecting K Nand flash chips, K, L, M, and N are all values ​​greater than or equal to 1, based on the Nand Flash supporting independent plane reading.

[0010] As a further aspect of the present invention, the command preprocessing method based on Nand Flash AIPR further includes pre-sorting, wherein the pre-sorting step is as follows:

[0011] Check if the command is an MP read. If it is an MP read, do not perform sorting and send it directly to the hardware module for execution.

[0012] The number of commands P to be sorted can be set in real time according to the needs, and each P commands completes one sorting operation.

[0013] Command classification: the sp read command is of read type, while the sp / mp write and erase commands are of non-read type;

[0014] If a command is received from the server (FW) and is of type read, it is inserted into the corresponding position according to its target, LUN, and plane address information, so that the addresses of adjacent commands meet the requirements of AIPR or the requirements of parallel execution of multiple LUNs; if it is not of type read, it is inserted into the corresponding position according to its target and LUN addresses, so that the addresses of adjacent commands meet the requirements of parallel execution of multiple LUNs.

[0015] For multiple read commands that meet AIPR requirements, signals are used to record them for hardware identification.

[0016] As a further aspect of the present invention, read-type commands have high priority and are placed in the first half of the entire command sequence, while non-read-type commands have low priority and are placed in the second half of the entire command sequence.

[0017] As a further aspect of the present invention, when the addresses of adjacent commands meet the requirements of AIPR, the targets are the same, the LUNs are the same, and the planes are different.

[0018] As a further aspect of the present invention, based on the pre-sorting principle, if sorting is performed once for every P instructions, sorting is performed on read type commands (read instructions) and non-read type commands (notread instructions), wherein read type commands are read instructions and non-read type commands are notread instructions, including the following steps:

[0019] Each instruction contains [target value] [lun value] [plane value] [status[read / notread]];

[0020] For P instructions, first iterate through them to get the number of read instructions [readnum] and the number of notread instructions [P-readnum].

[0021] Create two string arrays, array_read and array_notread, with lengths readnum and P-readnum respectively, to record the read and notread instructions respectively;

[0022] For array_read, create the check function and the insert function;

[0023] Check if each element [target value] [lun value] in the array_read is the same as all previous instructions, and adjust the position of the array_read elements accordingly;

[0024] Create the `check_new` and `insert_new` functions;

[0025] Call the check_new function to check if each element [target value] [lunvalue] [plane value] in the array_read array is the same as all previous instructions. If the return value is less than the current array index, call the insert_new function to adjust it.

[0026] Calculate (readnum-begin) / same_num=k, and shift the same_num-1 elements starting from begin+1 to the right by k, 2k, ..., (same_num-1)k respectively;

[0027] Set a continue number and a linked list. Each element of the linked list is a tuple consisting of the target-lun and the continue number. During the loop, if the instruction index is 0 or the target-lun is different from the previous element, set the continue number to 1; otherwise, set the continue number to +1.

[0028] For the array_notread array, loop through each element [target][lun] to check if it is the same as all the previous instructions, call the check function, and if the return value is less than the current array index, move the instruction to the end of array_notread;

[0029] Based on the actual format requirements, the arrays of array_read and array_notread, as well as the linked list of continue number, are output to the hardware module.

[0030] As a further aspect of the present invention, the check function includes four parameters: array, original index, target, and lun; the check function is used to check the positions of instructions in the array between positions 0 and src that are the same as the target and lun of the instruction, and returns the index of the same instruction in the array;

[0031] The insert function takes three parameters: the instruction, the original index, and the destination index. The insert function is used to move the instruction at the src position in the array to the dest position, while all instructions in the original array from dest to src-1 are shifted one position to the right.

[0032] As a further aspect of the present invention, the check function is called repeatedly. If the return value of check is equal to the current array index, no adjustment is made; if the return value of check is less than the current array index, the insert function is called to adjust array_read.

[0033] As a further aspect of the present invention, the number of identical adjacent elements [target] [lun][plane] in the array_read array is determined, and the starting index begin and the number of identical elements same, same_num, are output through a linked list.

[0034] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed, implement any of the above-described command preprocessing methods based on Nand Flash AIPR according to the present invention.

[0035] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs any of the above-described command preprocessing methods based on NandFlash AIPR according to the present invention.

[0036] In another aspect, the present invention provides a chip for flow control based on the command preprocessing method of Nand Flash AIPR according to any of the above-mentioned claims, wherein the chip architecture includes a CPU reset vector register, a CPU release control pin, a CPU release control register, and a debug interface, wherein...

[0037] The CPU reset vector register is used to control the address of the instructions read and executed after the CPU is released;

[0038] The CPU release control register is used to control the CPU release when the chip is powered on.

[0039] The CPU release control pin is used to control the validity of the CPU release control register;

[0040] The debug interface is used to read and write on-chip RAM and registers to perform flow control of the chip.

[0041] The present invention has at least the following beneficial technical effects:

[0042] This invention proposes a command preprocessing method based on NAND Flash AIPR, which pre-sorts the sp read commands so that multiple sp read commands from the same target, the same LUN, but different planes can be sent to NAND as a single command group. This not only saves command channel resources but also improves the read rate.

[0043] On the other hand, after pre-sorting the above-mentioned non-read type commands, the LUN addresses of adjacent commands are likely to remain different, so that the commands sent to the hardware module can meet the requirements of parallel execution of multiple LUNs as much as possible, thereby improving the command execution rate and further improving SSD performance.

[0044] These or other aspects of this application will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the application. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0046] In the diagram:

[0047] Figure 1 A schematic diagram of the device structure in the command preprocessing method based on Nand Flash AIPR according to the present invention is shown;

[0048] Figure 2 A flowchart of the command preprocessing method based on Nand Flash AIPR according to the present invention is shown;

[0049] Figure 3 A schematic diagram of an embodiment of a computer-readable storage medium for implementing a command preprocessing method based on Nand Flash AIPR according to the present invention is shown;

[0050] Figure 4 A schematic diagram of the hardware structure of an embodiment of a computer device for implementing a command preprocessing method based on Nand Flash AIPR according to the present invention is shown.

[0051] Figure 5 A schematic diagram of the framework of an embodiment of the chip according to the present invention is shown. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0053] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0054] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0057] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0058] Currently, SSDs primarily perform read, write, and erase operations on NAND flash memory using a command-address approach. Address information includes target, LUN, plane, block, page, and column addresses. Common commands include singleplane (sp) read / write / erase, multiple plane (mp) read / write / erase, and AIPR. sp performs a read operation on only one plane within a LUN at a time; mp, while capable of operating on multiple planes within a LUN, requires setting the same page address; AIPR is a flexible mp read operation that allows independent read operations on different pages across multiple planes within the same LUN, significantly improving SSD read speeds compared to mp read. Given NAND flash's support for AIPR technology, preprocessing commands issued by the firmware (FW) is an effective method to improve SSD performance.

[0059] In SSDs, commands issued by the firmware (FW) are typically transmitted sequentially to the hardware module for processing. On one hand, the spread command occupies a dedicated command channel to control the NAND Flash for read operations, which significantly wastes command channel resources. On the other hand, if two adjacent spread read commands have the same target, the same LUN, but different planes, the second spread read command must wait for the first spread read command to finish executing before it can begin, increasing read latency.

[0060] In view of this, embodiments of the present invention provide a command preprocessing method based on NAND Flash AIPR, which pre-sorts the sp read commands so that multiple sp read commands with the same target, the same LUN, but different planes can be sent to NAND in the form of a single command group, which not only saves command channel resources but also improves the read rate.

[0061] On the other hand, after pre-sorting non-read type commands, the LUN addresses of adjacent commands are likely to remain different, so that the commands sent to the hardware module can meet the requirements of parallel execution of multiple LUNs as much as possible, thereby improving the command execution rate and further improving SSD performance.

[0062] In some embodiments of the present invention, see Figure 1 and Figure 2 As shown, a command preprocessing method based on Nand Flash AIPR is provided, including the following steps:

[0063] Step S10: Preprocess and sort the commands according to the type and address information of the commands issued by the FW, and transmit them to the hardware module for processing;

[0064] Step S20: Send the sorted commands to the hardware module in sequence. When the hardware module detects that the continuenumber value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group.

[0065] In this embodiment, one channel connects K Nand flash chips (devices), such as Figure 1 As shown, each Nand chip includes L targets, each target contains M LUNs, and each LUN has N planes, where K, L, M, and N are all values ​​greater than or equal to 1. Given that Nand Flash can support Independent Plane Read (AIPR) technology, in this invention, the commands are first preprocessed according to the type and address information of the commands issued by the Flash Controller (FW), and then transmitted to the hardware module for processing.

[0066] In some embodiments of the present invention, the command preprocessing method based on Nand Flash AIPR further includes pre-sorting, wherein the pre-sorting step is as follows:

[0067] (1) First, check if the command is mp read. If it is mp read, no sorting is performed and it is sent directly to the hardware module for execution.

[0068] (2) Set the number of commands P to be sorted in real time according to the requirements. Each P commands completes one sorting operation.

[0069] (3) Command classification: sp read command is of type read, sp / mp write and erase command are of type non-read. Read type commands have high priority and are placed in the first half of the entire command sequence, while non-read type commands have low priority and are placed in the second half of the entire command sequence.

[0070] (4) For a command sent by FW, if it is of type read, it is inserted into the corresponding position according to its target, LUN and plane address information so that the addresses of adjacent commands meet the requirements of AIPR (same target, same LUN, different plane) or meet the requirements of multiple LUN parallel execution; if it is of type non-read, it is inserted into the corresponding position according to its target and LUN addresses so that the addresses of adjacent commands meet the requirements of multiple LUN parallel execution.

[0071] (5) For multiple read commands that meet the AIPR requirements, use a signal (continue number) to record them so that the hardware can identify them.

[0072] In an embodiment of the present invention, the sorted commands are sent to the hardware module in sequence. When the hardware module detects that the continue number value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group.

[0073] Based on the pre-sorting principle described above, assuming that sorting is performed once for every P instructions, the specific steps for sorting read type commands (read instructions) and non-read type commands (notread instructions) are as follows:

[0074] (1) Each instruction contains [target value] [lun value] [plane value] [status[read / notread]];

[0075] (2) For P instructions, first traverse them to get the number of read instructions [readnum] and the number of notread instructions [P-readnum];

[0076] (3) Create two string arrays array_read and array_notread, with lengths readnum and P-readnum respectively, to record the read instruction and the notread instruction respectively;

[0077] (4) For array_read, create the check function and the insert function:

[0078] The `check` function takes four parameters: `array_read`, `src`, `target_value`, and `lun_value`, which are the array, the original index, `target`, and `lun`, respectively. The `check` function checks the positions of instructions in the array between positions 0 and `src` that are identical to the specified instruction in both `target` and `lun`, and returns the index of that identical instruction in the array.

[0079] The insert function takes three parameters (instruct, src, dest), which are the instruction, the original index, and the destination index, respectively. The insert function moves the instruction at the src position in the array to the dest position, and at the same time, all instructions in the original array from dest to src-1 are shifted one position to the right.

[0080] (5) Determine whether each element [target value] [lun value] in the array_read array is the same as all previous instructions. Call the check function repeatedly. If the check return value is equal to the current array index, no adjustment is made; if the check return value is less than the current array index, call the insert function to adjust array_read.

[0081] (6) Create the check_new and insert_new functions, which are based on the same principle as the check and insert functions mentioned above.

[0082] (7) Call the check_new function to determine whether each element [target value] [lunvalue] [plane value] in the array_read array is the same as all previous instructions. If the return value is less than the current array index, call the insert_new function to adjust.

[0083] Determine the number of consecutive elements [target] [lun][plane] in the array_read array that are the same, and output the starting index (begin) and the number of identical elements (same_num) in a linked list. This is a loop operation.

[0084] (8) Calculate (readnum-begin) / same_num=k, shift the same_num-1 elements starting from begin+1 to the right by k, 2k, ..., (same_num-1)k respectively. Note that if the instruction of the target position to be moved is the same as the [target] [lun] of the previous position instruction, then shift it one position to the right until they are different.

[0085] (9) Set a continue number and a linked list. Each element of the linked list is a tuple, namely target-lun and continue number. During the loop, if the instruction index is 0 or the target-lun is different from the previous element, set continue number=1; otherwise, set continue number+1.

[0086] (10) For the array_notread array, loop to check whether each element [target][lun] is the same as all the previous instructions, call the check function, and if the return value is less than the current array index, move the instruction to the end of array_notread.

[0087] (11) According to the actual format requirements, output the array_read and array_notread arrays and the continuenumber linked list to the hardware module so that the hardware module can process them.

[0088] Compared to existing technologies in SSDs, where commands issued by the firmware (FW) are typically transmitted sequentially to the hardware module for processing, the current approach in SSDs suffers from several drawbacks. Firstly, the `sp read` command occupies a dedicated command channel to control the NAND Flash for read operations, significantly wasting command channel resources. Secondly, if two adjacent `sp read` commands share the same target and LUN but different planes, the second `sp read` command must wait for the first to finish executing before it can begin, increasing read latency.

[0089] This invention pre-sorts the spread read commands, enabling multiple spread read commands from the same target, the same LUN, but different planes to be sent to the NAND as a single command group. This not only saves command channel resources but also improves the read rate.

[0090] On the other hand, after pre-sorting the above-mentioned non-read type commands, the LUN addresses of adjacent commands are likely to remain different, so that the commands sent to the hardware module can meet the requirements of parallel execution of multiple LUNs as much as possible, thereby improving the command execution rate and further improving SSD performance.

[0091] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0092] A second aspect of the present invention also provides a computer device 400, including a memory 420 and a processor 410. The memory stores a computer program, which, when executed by the processor, implements the method of any of the above embodiments, including the following steps:

[0093] The commands are preprocessed and sorted according to the type and address information of the commands issued by the FW, and then transmitted to the hardware module for processing.

[0094] The sorted commands are sent to the hardware module in sequence. When the hardware module detects that the continue number value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group.

[0095] The command preprocessing method based on Nand Flash AIPR further includes pre-sorting, the pre-sorting steps of which are as follows:

[0096] (1) First, check if the command is mp read. If it is mp read, no sorting is performed and it is sent directly to the hardware module for execution.

[0097] (2) Set the number of commands P to be sorted in real time according to the needs, and each P commands complete one sorting operation.

[0098] (3) Command classification: sp read command is of type read, sp / mp write and erase command are of type non-read. Read type commands have high priority and are placed in the first half of the entire command sequence, while non-read type commands have low priority and are placed in the second half of the entire command sequence.

[0099] (4) For a command sent by FW, if it is of type read, it is inserted into the corresponding position according to its target, LUN and plane address information so that the addresses of adjacent commands meet the requirements of AIPR (same target, same LUN, different plane) or meet the requirements of multiple LUN parallel execution; if it is of type non-read, it is inserted into the corresponding position according to its target and LUN addresses so that the addresses of adjacent commands meet the requirements of multiple LUN parallel execution.

[0100] (5) For multiple read commands that meet the AIPR requirements, use a signal (continue number) to record them so that the hardware can identify them.

[0101] Based on the pre-sorting principle described above, assuming that sorting is performed once for every P instructions, the specific steps for sorting read type commands (read instructions) and non-read type commands (notread instructions) are as follows:

[0102] (1) Each instruction contains [target value] [lun value] [plane value] [status[read / notread]];

[0103] (2) For P instructions, first traverse them to get the number of read instructions [readnum] and the number of notread instructions [P-readnum];

[0104] (3) Create two string arrays array_read and array_notread, with lengths readnum and P-readnum respectively, to record the read instruction and the notread instruction respectively;

[0105] (4) For array_read, create the check function and the insert function:

[0106] The `check` function takes four parameters: `array_read`, `src`, `target_value`, and `lun_value`, which are the array, the original index, `target`, and `lun`, respectively. The `check` function checks the positions of instructions in the array between positions 0 and `src` that are identical to the specified instruction in both `target` and `lun`, and returns the index of that identical instruction in the array.

[0107] The insert function takes three parameters (instruct, src, dest), which are the instruction, the original index, and the destination index, respectively. The insert function moves the instruction at the src position in the array to the dest position, and at the same time, all instructions in the original array from dest to src-1 are shifted one position to the right.

[0108] (5) Determine whether each element [target value] [lun value] in the array_read array is the same as all previous instructions. Call the check function repeatedly. If the check return value is equal to the current array index, no adjustment is made; if the check return value is less than the current array index, call the insert function to adjust array_read.

[0109] (6) Create the check_new and insert_new functions, which are based on the same principle as the check and insert functions mentioned above.

[0110] (7) Call the check_new function to determine whether each element [target value] [lunvalue] [plane value] in the array_read array is the same as all previous instructions. If the return value is less than the current array index, call the insert_new function to adjust.

[0111] Determine the number of consecutive elements [target] [lun][plane] in the array_read array that are the same, and output the starting index (begin) and the number of identical elements (same_num) in a linked list. This is a loop operation.

[0112] (8) Calculate (readnum-begin) / same_num=k, shift the same_num-1 elements starting from begin+1 to the right by k, 2k, ..., (same_num-1)k respectively. Note that if the instruction of the target position to be moved is the same as the [target] [lun] of the previous position instruction, then shift it one position to the right until they are different.

[0113] (9) Set a continue number and a linked list. Each element of the linked list is a tuple, namely target-lun and continue number. During the loop, if the instruction index is 0 or the target-lun is different from the previous element, set continue number=1; otherwise, set continue number+1.

[0114] (10) For the array_notread array, loop to check whether each element [target][lun] is the same as all the previous instructions, call the check function, and if the return value is less than the current array index, move the instruction to the end of array_notread.

[0115] (11) According to the actual format requirements, output the array_read and array_notread arrays and the continuenumber linked list to the hardware module so that the hardware module can process them.

[0116] like Figure 4 The diagram shown is a hardware structure schematic of an embodiment of a computer device for executing a command preprocessing method based on Nand Flash AIPR provided by the present invention. Figure 4 Taking the computer device 400 shown as an example, this computer device includes a processor 410 and a memory 420, and may also include an input device 430 and an output device 440. The processor 410, memory 420, input device 430, and output device 440 can be connected via a bus or other means. Figure 4 Taking a bus connection as an example, input device 430 can receive input digital or character information and generate signal inputs related to command preprocessing based on Nand Flash AIPR. Output device 440 may include display devices such as a display screen.

[0117] Memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the command preprocessing method based on Nand Flash AIPR in the embodiments of this application. Memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by using the command preprocessing method based on Nand Flash AIPR, etc. In addition, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0118] The processor 410 executes various server functions and data processing by running non-volatile software programs, instructions, and modules stored in the memory 420, thereby implementing the command preprocessing method based on Nand Flash AIPR as described in the above method embodiment. The steps are as follows:

[0119] The commands are preprocessed and sorted according to the type and address information of the commands issued by the FW, and then transmitted to the hardware module for processing.

[0120] The sorted commands are sent to the hardware module in sequence. When the hardware module detects that the continue number value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group.

[0121] The command preprocessing method based on Nand Flash AIPR further includes pre-sorting, the pre-sorting steps of which are as follows:

[0122] (1) First, check if the command is mp read. If it is mp read, no sorting is performed and it is sent directly to the hardware module for execution.

[0123] (2) Set the number of commands P to be sorted in real time according to the requirements. Each P commands completes one sorting operation.

[0124] (3) Command classification: sp read command is of type read, sp / mp write and erase command are of type non-read. Read type commands have high priority and are placed in the first half of the entire command sequence, while non-read type commands have low priority and are placed in the second half of the entire command sequence.

[0125] (4) For a command sent by FW, if it is of type read, it is inserted into the corresponding position according to its target, LUN and plane address information so that the addresses of adjacent commands meet the requirements of AIPR (same target, same LUN, different plane) or meet the requirements of multiple LUN parallel execution; if it is of type non-read, it is inserted into the corresponding position according to its target and LUN addresses so that the addresses of adjacent commands meet the requirements of multiple LUN parallel execution.

[0126] (5) For multiple read commands that meet the AIPR requirements, use a signal (continue number) to record them so that the hardware can identify them.

[0127] Based on the pre-sorting principle described above, assuming that sorting is performed once for every P instructions, the specific steps for sorting read type commands (read instructions) and non-read type commands (notread instructions) are as follows:

[0128] (1) Each instruction contains [target value] [lun value] [plane value] [status[read / notread]];

[0129] (2) For P instructions, first traverse them to get the number of read instructions [readnum] and the number of notread instructions [P-readnum];

[0130] (3) Create two string arrays array_read and array_notread, with lengths readnum and P-readnum respectively, to record the read instruction and the notread instruction respectively;

[0131] (4) For array_read, create the check function and the insert function:

[0132] The `check` function takes four parameters: `array_read`, `src`, `target_value`, and `lun_value`, which are the array, the original index, `target`, and `lun`, respectively. The `check` function checks the positions of instructions in the array between positions 0 and `src` that are identical to the specified instruction in both `target` and `lun`, and returns the index of that identical instruction in the array.

[0133] The insert function takes three parameters (instruct, src, dest), which are the instruction, the original index, and the destination index, respectively. The insert function moves the instruction at the src position in the array to the dest position, and at the same time, all instructions in the original array from dest to src-1 are shifted one position to the right.

[0134] (5) Determine whether each element [target value] [lun value] in the array_read array is the same as all previous instructions. Call the check function repeatedly. If the check return value is equal to the current array index, no adjustment is made; if the check return value is less than the current array index, call the insert function to adjust array_read.

[0135] (6) Create the check_new and insert_new functions, which are based on the same principle as the check and insert functions mentioned above.

[0136] (7) Call the check_new function to determine whether each element [target value] [lunvalue] [plane value] in the array_read array is the same as all previous instructions. If the return value is less than the current array index, call the insert_new function to adjust.

[0137] Determine the number of consecutive elements [target] [lun][plane] in the array_read array that are the same, and output the starting index (begin) and the number of identical elements (same_num) in a linked list. This is a loop operation.

[0138] (8) Calculate (readnum-begin) / same_num=k, shift the same_num-1 elements starting from begin+1 to the right by k, 2k, ..., (same_num-1)k respectively. Note that if the instruction of the target position to be moved is the same as the [target] [lun] of the previous position instruction, then shift it one position to the right until they are different.

[0139] (9) Set a continue number and a linked list. Each element of the linked list is a tuple, namely target-lun and continue number. During the loop, if the instruction index is 0 or the target-lun is different from the previous element, set continue number=1; otherwise, set continue number+1.

[0140] (10) For the array_notread array, loop to check whether each element [target][lun] is the same as all the previous instructions, call the check function, and if the return value is less than the current array index, move the instruction to the end of array_notread.

[0141] (11) According to the actual format requirements, output the array_read and array_notread arrays and the continuenumber linked list to the hardware module so that the hardware module can process them.

[0142] A third aspect of the present invention also provides a chip 500 for flow control according to any of the above-described command preprocessing methods based on Nand Flash AIPR. Figure 5 A schematic diagram of the frame of the chip 500 according to the present invention is shown. (As shown) Figure 5 As shown, in this embodiment, the chip 500 architecture includes a CPU reset vector register 510, a CPU release control pin 520, a CPU release control register 530, and a debug interface 540, wherein...

[0143] The CPU reset vector register 510 is used to control the address of the instructions read and executed after the CPU is released;

[0144] The CPU release control register 530 is used to control the CPU release when the chip 500 is powered on.

[0145] The CPU release control pin 520 is used to control the validity of the CPU release control register 530;

[0146] The debug interface 540 is used to read and write on-chip RAM and registers to perform flow control of the chip.

[0147] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0148] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0149] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0150] This invention proposes a command preprocessing method based on Nand Flash AIPR, which uses a hardware watchdog to monitor multiple subsystems, saving costs and facilitating implementation. Before a system abnormal reset, a notification is sent to the host, requesting the host to stop communication with the board firmware, preventing board firmware restarts from causing host-side anomalies, reducing the spread of anomalies, and improving host-side stability. It can automatically dump core data to the host side for easy analysis and problem localization. It also supports actively triggering the generation and export of core data on the host side, which is beneficial for developers to analyze system operating status.

[0151] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0152] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0153] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A command preprocessing method based on NAND Flash AIPR, characterized in that, The command preprocessing method based on Nand FlashAIPR includes the following steps: The commands are preprocessed and sorted according to the type and address information of the commands issued by the FW, and then transmitted to the hardware module for processing. The sorted commands are sent to the hardware module in sequence. When the hardware module detects that the continue number value is greater than 1, it automatically sends a command to enable the AIPR function to the Nand Flash and sends the commands marked with the continue number to the Nand Flash in the form of a command group. The command preprocessing method based on Nand Flash AIPR also includes pre-sorting, the pre-sorting steps of which are as follows: Check if the command is an MP read. If it is an MP read, do not perform sorting and send it directly to the hardware module for execution. The number of commands P to be sorted can be set in real time according to the needs, and each P commands completes one sorting operation. Command classification: the sp read command is of read type, while the sp / mp write and erase commands are of non-read type; If a command is received from the server (FW) and is of type read, it is inserted into the corresponding position according to its target, LUN, and plane address information, so that the addresses of adjacent commands meet the requirements of AIPR or the requirements of parallel execution of multiple LUNs; if it is not of type read, it is inserted into the corresponding position according to its target and LUN addresses, so that the addresses of adjacent commands meet the requirements of parallel execution of multiple LUNs. For multiple read commands that meet AIPR requirements, the "continue number" signal is used to record them for hardware identification.

2. The command preprocessing method based on Nand Flash AIPR according to claim 1, characterized in that, A channel connects K Nand flash chips. Each Nand chip includes L targets, each target contains M LUNs, and each LUN has N planes.

3. The command preprocessing method based on Nand Flash AIPR according to claim 2, characterized in that, In a channel connecting K Nand flash chips, K, L, M, and N are all values ​​greater than or equal to 1, based on the Nand Flash supporting independent plane reading.

4. The command preprocessing method based on Nand Flash AIPR according to claim 1, characterized in that, Commands of type 'read' have high priority and are placed in the first half of the command sequence, while commands of type 'non-read' have low priority and are placed in the second half of the command sequence.

5. The command preprocessing method based on Nand Flash AIPR according to claim 4, characterized in that, When adjacent commands meet the AIPR requirements, they have the same target, the same LUN, and different planes.

6. The command preprocessing method based on Nand Flash AIPR according to claim 5, characterized in that, Based on the pre-sorting principle, if sorting is performed once every P instructions, sorting is performed on read type commands and non-read type commands, where read type commands are read instructions and non-read type commands are notread instructions, including the following steps: Each instruction contains [target value] [lun value] [plane value] [status[read / notread]]; For P instructions, first iterate through them to get the number of read instructions [readnum] and the number of notread instructions [P-readnum]. Create two string arrays, array_read and array_notread, with lengths readnum and P-readnum respectively, to record the read and notread instructions respectively; For array_read, create the check function and the insert function; Check if each element [target value] [lun value] in the array_read is the same as all previous instructions, and adjust the position of the array_read elements accordingly; Create the `check_new` and `insert_new` functions; The `check_new` function is called to check if each element [target value] [lun value] [plane value] in the `array_read` array is the same as all previous instructions. If the return value is less than the current array index, the `insert_new` function is called to adjust it. In this function, the number of adjacent elements [target] [lun] [plane] that are the same in the `array_read` array is checked, and the starting index of the adjacent elements that are the same, `begin`, and the number of the same elements, `same_num`, are output through a linked list. Calculate (readnum-begin) / same_num=k, and shift the same_num-1 elements starting from begin+1 to the right by k, 2k, ..., (same_num-1)k respectively; Set a continue number and a linked list. Each element of the linked list is a tuple consisting of the target-lun and the continue number. During the loop, if the instruction index is 0 or the target-lun is different from the previous element, set the continue number to 1; otherwise, set the continue number to +1. For the array_notread array, loop through each element [target][lun] to check if it is the same as all the previous instructions, call the check function, and if the return value is less than the current array index, move the instruction to the end of array_notread; Based on the actual format requirements, the arrays of array_read and array_notread, as well as the linked list of continue number, are output to the hardware module.

7. The command preprocessing method based on Nand Flash AIPR according to claim 6, characterized in that, The check function contains four parameters: array, original index src, target, and lun; the check function is used to check the positions of instructions in the array between positions 0 and src that are the same as the target and lun of the instruction, and returns the index of the same instruction in the array; The insert function takes three parameters: the instruction, the original index, and the destination index. The insert function is used to move the instruction at the src position in the array to the dest position, while all instructions in the original array from dest to src-1 are shifted one position to the right.

8. The command preprocessing method based on Nand Flash AIPR according to claim 7, characterized in that, The check function is called repeatedly. If the check return value is equal to the current array index, no adjustment is made; if the check return value is less than the current array index, the insert function is called to adjust array_read.

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