A semiconductor silicon wafer surface topography model prediction method based on metrology data

Abstract

The application discloses a kind of based on metrology data's semiconductor silicon wafer surface topography model prediction method, comprising the following steps: S1, obtains the original metrology data of a piece of silicon wafer with D diameter in metrology platform according to linear arrangement distribution;S2, original metrology data is converted into binary data;S3, constructs silicon wafer polar coordinate parameter model;S4, constructs silicon wafer Cartesian coordinate parameter model;S5, constructs the multi-dimensional grid structure model of silicon wafer surface topography;S6, constructs metrology parameter information model;S7, establishes silicon wafer surface topography prediction algorithm model;S8, calculates silicon wafer surface topography parameter;S9, generates silicon wafer surface topography chart.The application can predict the surface topography of silicon wafer, the surface topography chart obtained has high accuracy, is convenient for user to carry out visual observation, is favorable to the overall surface topography quality evaluation of silicon wafer accordingly, the problem that may appear in production process is modified in advance, to improve silicon wafer yield.

Description

Technical Field

[0001] This invention relates to the field of silicon wafer morphology, and in particular to a method for predicting the surface morphology of semiconductor silicon wafers based on measurement data. Background Technology

[0002] In the electronics industry, the surface quality of large-scale integrated circuit (LC) chips directly affects the performance and yield of LCs. Silicon wafers, as the basic material for manufacturing LCs, have their surface morphology directly impacting the quality of the LC chip surface. With the booming development of the semiconductor and LC industries, the production scale of silicon wafers is constantly expanding. During the silicon wafer processing, processes such as wire cutting, thinning, and polishing all affect the surface morphology, thus requiring continuous monitoring. Furthermore, surface morphology can be used to evaluate the quality of silicon wafers and to monitor and optimize the manufacturing process.

[0003] During silicon wafer manufacturing, numerous characteristic parameter tests are required to monitor the process. To effectively manage the usage status of silicon wafers on various testing machines, the testing system generates a large amount of testing data daily. Therefore, quickly and intuitively evaluating the surface morphology of silicon wafers using raw data, visualizing abnormal data, and identifying problematic testing machines based on these abnormalities is crucial for improving chip yield and reducing costs.

[0004] Currently, most manufacturers' metrology equipment on the market operates on a linear motion, back-and-forth scanning principle. Therefore, the measurement data is also linearly distributed, and this data is mostly discrete, failing to cover every point on the entire silicon wafer surface. Engineers primarily rely on visual inspection, switching between measurement lines and checking the uniformity of data distribution, rather than visually observing the overall surface appearance of the silicon wafer. Furthermore, due to the large volume of data, this method is cumbersome, time-consuming, and prone to identification errors. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for predicting the surface morphology of semiconductor silicon wafers based on measurement data. This method can predict the surface morphology of silicon wafers based on limited measurement data. The predicted surface morphology map fully reflects the surface morphology of the silicon wafer, has high accuracy, and is convenient for users to visualize and observe. This facilitates the evaluation of silicon wafer quality based on the generated surface morphology map, allowing for proactive modifications to address potential problems during production, thereby improving silicon wafer yield.

[0006] The method for predicting the surface morphology of semiconductor silicon wafers based on measurement data according to the present invention includes the following steps:

[0007] Step S1: Obtain the original measurement data of a silicon wafer with a diameter of D arranged in a straight line in the measurement machine. The original measurement data includes: the number of scanning measurement lines, the angle of each measurement line, the spacing between each measurement point on each measurement line, and the measurement value of the characteristic parameters of each measurement point.

[0008] Step S2: Convert the raw measurement data into binary data;

[0009] Step S3: Traverse and analyze the data of each measurement point to construct a polar coordinate parameter model of the silicon wafer;

[0010] Step S4: Construct a silicon wafer Cartesian coordinate parameter model based on the polar coordinate parameter model;

[0011] Step S5: Construct a multidimensional grid structure model of the silicon wafer surface morphology based on the Cartesian coordinate parameter model;

[0012] Step S6: Traverse and analyze the characteristic parameter measurement values ​​of each measurement point to construct a measurement parameter information model;

[0013] Step S7: Establish a silicon wafer surface morphology prediction algorithm model based on the measurement parameter information model;

[0014] Step S8: Calculate the silicon wafer surface morphology parameters based on the silicon wafer surface morphology prediction algorithm model and the multidimensional grid structure model in step S5.

[0015] Step S9: Generate a silicon wafer surface morphology map based on the silicon wafer surface morphology parameters.

[0016] According to the semiconductor silicon wafer surface morphology model prediction method based on measurement data of the present invention, the surface morphology of the silicon wafer can be predicted based on limited silicon wafer measurement data. The predicted surface morphology map can fully reflect the actual surface morphology of the silicon wafer with high accuracy. The generated surface morphology map can be easily visualized by users, which is conducive to evaluating the quality of the silicon wafer surface morphology. This facilitates the monitoring of silicon wafers in the production process and allows for early modification of possible problems in the production process, optimizing the manufacturing process, thereby improving the silicon wafer yield and reducing costs. It has good portability and flexibility and can adapt to different changes.

[0017] In some embodiments of the present invention, the step S3 of constructing the silicon wafer polar coordinate parameter model includes the following steps:

[0018] Step S3-1: Use the center of the silicon wafer as the pole in the polar coordinate system. ;

[0019] Step S3-2: When constructing the polar coordinate system, ensure that the notch position on the silicon wafer is directly below the center of the silicon wafer circle. The notch position on the silicon wafer is then used as the reference point. Starting from the center of the silicon wafer, rotate 90 degrees counterclockwise to the end point. ,point With the extreme point The formed rays It is the polar axis;

[0020] Step S3-3: Each measurement line is divided into an upper half and a lower half by the line containing the polar axis. The polar angles of all measurement points on the upper half of the same measurement line are the same, and the polar angles of all measurement points on the lower half of the same measurement line are the same. The difference between the polar angles of measurement points in the upper half and the lower half of the same measurement line is... Measurement point b on the measurement line and the pole The distance between the radial distances is The polar angle is Then the polar coordinates of the measurement point are ;

[0021] Step S3-4: Traverse all measurement points to construct silicon wafer polar coordinates Parametric model.

[0022] In some embodiments of the present invention, constructing the silicon wafer Cartesian coordinate parameter model in step S4 includes the following steps:

[0023] Step S4-1: Construct a Cartesian coordinate system for the surface morphology of the silicon wafer: using the poles from step S3-1... Using the origin of the Cartesian coordinate system, the polar axis of step S3-2 is taken as the positive x-axis direction of the Cartesian coordinate system;

[0024] Step S4-2: Calculate the coordinates of each measurement point on the silicon wafer in the Cartesian coordinate system according to the first to fifth formulas. The first to fifth formulas are as follows:

[0025] First formula: ;

[0026] Second formula: ;

[0027] Third formula: ;

[0028] Fourth formula: ;

[0029] Fifth formula: For measurement points on the same measurement line, ;

[0030] in, Let F be the polar radius of any measurement point F in the upper half of any measurement line. Let F be the polar angle of the measurement point. The polar angles of each measurement point in the lower half of the measurement line are given. Let S be the polar radius of any measurement point S in the lower half of the measurement line. Let F be the XY coordinates of the upper measurement point F on the upper half of the measurement line. Let S be the XY coordinates of the measurement point S on the lower half of the measurement line, and D be the diameter of the silicon wafer.

[0031] Step S4-3: Traverse all measurement points to construct Cartesian coordinates Parametric model.

[0032] In some embodiments of the present invention, the step S5 of constructing a multidimensional grid structure model of the silicon wafer surface morphology includes the following steps:

[0033] Step S5-1: Determine the qualified quality area of ​​the silicon wafer: The ring with a width of d near the edge of the silicon wafer is the edge ring. The other areas on the silicon wafer except for the area where the edge ring is located are the qualified quality areas. All measurement points are located within the qualified quality areas.

[0034] Step S5-2: Based on the Cartesian coordinate parameter model in step S4, calculate the XY coordinates of all measurement points and generate a two-dimensional coordinate matrix XY_POINTS, where XY_POINTS = , , ,in, Indicates the first The X coordinates of each measurement point Indicates the first The Y-coordinate of each measurement point ;

[0035] Step S5-3, Data Vectorization: Convert the two-dimensional coordinate matrix XY_POINTS into a one-dimensional row vector X_POINTS containing only the X coordinate and a one-dimensional column vector Y_POINTS containing only the Y coordinate, respectively. Then, the extreme values ​​of the grid point coordinates in the grid structure are the maximum values ​​of the X coordinates. Minimum value of X coordinate Maximum value of Y coordinate minimum value of Y coordinate ;

[0036] Step S5-4: Determine the grid spacing of the grid structure model, including the grid length of the unit grid. , grid width and the number of grid cells, where the number of grid cells is determined by the grid length of the cells. Grid width It is determined together with the extreme values ​​of the grid point coordinates;

[0037] Step S5-5: Construct a multi-dimensional grid structure model of the silicon wafer surface morphology based on the grid spacing.

[0038] In some embodiments of the present invention, step S5-5 includes the following steps:

[0039] Step S5-5-1: Calculate the limit values ​​of the grid point coordinates based on the silicon wafer diameter D and the edge ring width d, as follows:

[0040] Maximum value of X coordinate ;

[0041] Minimum value of X-coordinate =- ;

[0042] Maximum value of Y coordinate ;

[0043] Minimum value of Y coordinate =- ;

[0044] Step S5-5-2: Based on the grid length of the cell grid Grid width Calculate the distribution matrices of the first-dimensional and second-dimensional data in the raster structure model. The distribution matrix of the first-dimensional data is: The distribution matrix of the second dimension data is composed of... indivual Form a first-order matrix ,

[0045] in, ; ;

[0046] It is by indivual The first-order matrix formed

[0047] ;

[0048] ,

[0049] Step S5-5-3: Combining the distribution matrix and , obtain 2× × A three-dimensional matrix, including Grid points.

[0050] In some embodiments of the present invention, the construction of the measurement parameter information model in step S6 includes the following steps:

[0051] Step S6-1: Based on the binary data in step S2, obtain a one-dimensional vector including the silicon wafer thickness value at each measurement point. This one-dimensional vector is the measurement parameter information vector.

[0052] Step S6-2: Construct a measurement parameter information model based on the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model in step S4. The measurement parameter model is a relational function between the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model.

[0053] In some embodiments of the present invention, the step S7 of establishing the silicon wafer surface morphology prediction algorithm model includes the following steps:

[0054] Step S7-1: Let the measurement parameter information model in step S6 be element z, the one-dimensional row vector X_POINTS in step S5-2 be element x, and the one-dimensional column vector Y_POINTS be element y. Assume the function... satisfy , Let n+1 be the number of measurement points; construct the following system of equations:

[0055] ;

[0056] make , , Then the matrix form of the system of equations is as follows:

[0057] ,

[0058] in, The two-dimensional coordinate matrix XY_POINTS is obtained from step S5-1; when the highest power n is a fixed value, the matrix A that can be determined is unique; when the highest power n is sufficiently large, i.e., it satisfies... , It can be determined that there is only one. Polynomial;

[0059] Step S7-2: Construct a piecewise cubic interpolation polynomial model, the specific formula of which is as follows:

[0060] ;

[0061] Where n is the total number of measurement points and the number of points contained in the segmented unit; Let x be the x-coordinate value of the (i+1)th measurement point under the Cartesian coordinate parameter model of the silicon wafer; Let represent the ordinate value of the (i+1)th measurement point in the Cartesian coordinate parameter model of the silicon wafer. Obtained from the two-dimensional coordinate matrix XY_POINTS in step S5-1, .

[0062] In some embodiments of the present invention, the silicon wafer surface morphology parameters calculated according to the silicon wafer surface morphology prediction algorithm model in step S8 are as follows:

[0063] Substituting the multidimensional grid structure model of the silicon wafer surface morphology from step S5 into the piecewise cubic interpolation polynomial model formula in step S7-2, a two-dimensional matrix of the predicted measurement parameter values ​​of all grid points in the multi-grid structure model is obtained. The matrix size is... × In the corresponding multi-grid structure model There are n+1 grid points; the coordinates and measurement data of these grid points together constitute the basic elements of the silicon wafer surface topography parameters.

[0064] In some embodiments of the present invention, generating a silicon wafer surface topography map based on silicon wafer surface topography parameters in step S9 refers to drawing a two-dimensional or three-dimensional silicon wafer surface topography map as needed, combining the basic elements of silicon wafer surface topography parameters. The two-dimensional silicon wafer surface topography map is drawn in the XY coordinate system using contour lines, where the color of each point on the silicon wafer represents the measured value of the characteristic parameter at that point. The three-dimensional silicon wafer surface topography map is drawn in the XYZ coordinate system using contour lines plus three-dimensional drawing, where the Z-axis value represents the measured value of the characteristic parameter at that point.

[0065] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0066] Figure 1 This is a schematic flowchart of a method for constructing the surface morphology of a semiconductor silicon wafer based on measurement data according to the present invention;

[0067] Figure 2 This is a schematic diagram illustrating the establishment of the silicon wafer polar coordinate parameter model of the present invention;

[0068] Figure 3 This is a reference schematic diagram of the multidimensional grid structure model of the present invention;

[0069] Figure 4 This is a partial data diagram of the two-dimensional coordinate matrix XY_POINTS of the Cartesian coordinate parameter model of this invention;

[0070] Figure 5 This is a schematic diagram of the distribution matrix of the first-dimensional data in the raster structure model in Embodiment 1 or 3 of the present invention;

[0071] Figure 6This is a schematic diagram of the distribution matrix of the second-dimensional data in the raster structure model in Embodiment 1 or 3 of the present invention;

[0072] Figure 7 This is a schematic diagram of the multidimensional grid structure model in Embodiment 1 or 3 of the present invention;

[0073] Figure 8 These are the first 11 and last 11 elements of the silicon wafer measurement parameter information vector in Embodiment 1 of the present invention;

[0074] Figure 9 These are some elements of the two-dimensional matrix of predicted measurement parameter values ​​for grid points in Embodiment 1 of the present invention;

[0075] Figure 10 This is a two-dimensional silicon wafer surface morphology diagram of Embodiment 1 of the present invention;

[0076] Figure 11 This is a three-dimensional silicon wafer surface morphology diagram of Embodiment 1 of the present invention;

[0077] Figure 12 yes Figure 11 Top view along the Z-axis;

[0078] Figure 13 This is a schematic diagram of the distribution matrix of the first-dimensional data in the grid structure model in Embodiment 2 or 4 of the present invention;

[0079] Figure 14 This is a schematic diagram of the distribution matrix of the second-dimensional data in the raster structure model in Embodiment 2 or 4 of the present invention;

[0080] Figure 15 This is a schematic diagram of the multidimensional grid structure model in Embodiment 2 or 4 of the present invention;

[0081] Figure 16 This is a two-dimensional silicon wafer surface morphology diagram of Embodiment 2 of the present invention;

[0082] Figure 17 This is a two-dimensional silicon wafer surface morphology diagram of Embodiment 3 of the present invention;

[0083] Figure 18 This is a two-dimensional silicon wafer surface morphology diagram of Embodiment 4 of the present invention.

[0084] Figure label:

[0085] Silicon wafer 100;

[0086] 10 edge rings; 20 quality qualified areas; 30 unit grids. Detailed Implementation

[0087] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0088] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. Additionally, examples of various specific processes and materials are provided in this invention; however, those skilled in the art will recognize the applicability of other processes and / or the use of other materials.

[0089] Example 1

[0090] The following is for reference. Figures 1-18 A method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data, according to an embodiment of the present invention, is described, including steps S1 to S9.

[0091] Step S1: Obtain the original measurement data of a silicon wafer with a diameter of D arranged in a straight line in the measurement machine. The original measurement data includes: the number of scanning measurement lines, the angle of each measurement line, the spacing between each measurement point on each measurement line, and the measurement value of the characteristic parameters of each measurement point.

[0092] It should be noted that when the above-mentioned measurement equipment scans the silicon wafer, it generally uses a straight line passing through the center of the circle as the measurement line, and randomly selects multiple points on the measurement line as measurement points. After the measurement points on the measurement line are scanned, the center of the silicon wafer is used as a fixed point, and after rotating it by a certain angle, another straight line passing through the center of the circle is used as another measurement line. After scanning each measurement point on the other measurement line, the silicon wafer is rotated again... and so on, until all measurement lines and measurement points are scanned and measured.

[0093] It is understandable that all measurement lines are straight lines passing through the center of the silicon wafer, and the spacing between any two adjacent measurement lines can be equal or unequal; the spacing between any two measurement points can also be equal or unequal.

[0094] Specifically, taking a silicon wafer with a diameter D of 300mm as an example, the thickness of the silicon wafer is a characteristic parameter measurement value. The measurement value is the silicon wafer thickness value at each measurement point, and the number of measurement points n+1 is 2344.

[0095] Step S2: Convert the raw measurement data into binary data.

[0096] Step S3: Traverse and analyze the data of each measurement point to construct a silicon wafer polar coordinate parameter model.

[0097] Furthermore, the construction of the silicon wafer polar coordinate parameter model in step S3 specifically includes the following steps:

[0098] Step S3-1, refer to Figure 2 As shown, the center of the silicon wafer is taken as the pole in the polar coordinate system. ;

[0099] Step S3-2: When constructing the polar coordinate system, ensure that the notch position on the silicon wafer is directly below the center of the silicon wafer circle. The notch position on the silicon wafer is then used as the reference point. Starting from the center of the silicon wafer, rotate 90 degrees counterclockwise to the end point. ,point With the extreme point The formed rays It is the polar axis;

[0100] Step S3-3: Each measurement line is divided into an upper half and a lower half by the line containing the polar axis. The polar angles of all measurement points on the upper half of the same measurement line are the same, and the polar angles of all measurement points on the lower half of the same measurement line are the same. The difference between the polar angles of measurement points in the upper half and the lower half of the same measurement line is... Measurement points and poles on the measurement line The distance between the radial distances is The polar angle is Then the polar coordinates of the measurement point are ;

[0101] Step S3-4: Traverse all measurement points to construct silicon wafer polar coordinates Parametric model, i.e., polar coordinate parametric model

[0102] Understandably, since all measurement lines pass through the center of the silicon wafer, each measurement line is affected by X-rays. The line is divided into an upper and lower half, and the lower half of the same measuring line is connected to the ray. The angle between them is greater than that between the upper half and the ray. The angle between them is large The upper half of each measurement line and the X-ray The included angle is the polar angle of each measurement point on the upper half of each measurement line. The polar angles of each measurement point on the same part (upper half or lower half) of the same measurement line are equal. Therefore, the polar angle of each measurement point in the upper half of the same measurement line differs from the polar angle of each measurement point in the lower half. For example, the upper half of a certain measurement line and the ray The included angle between them is Then the polar angle of each measurement point on the upper half of this measurement line. The polar angles of each measurement point on the lower half of this measurement line. .

[0103] Step S4: Construct a silicon wafer Cartesian coordinate parameter model based on the polar coordinate parameter model.

[0104] Furthermore, the construction of the silicon wafer Cartesian coordinate parameter model in step S4 includes the following steps:

[0105] Step S4-1: Construct a Cartesian coordinate system for the surface morphology of the silicon wafer: using the poles from step S3-1... Using the origin of the Cartesian coordinate system, the polar axis of step S3-2 is taken as the positive x-axis direction of the Cartesian coordinate system;

[0106] Step S4-2: Calculate the coordinates of each measurement point on the silicon wafer in the Cartesian coordinate system according to the first to fifth formulas. The first to fifth formulas are as follows:

[0107] First formula: ;

[0108] Second formula: ;

[0109] Third formula: ;

[0110] Fourth formula: ;

[0111] Fifth formula: For measurement points on the same measurement line, ;

[0112] in, Let F be the polar radius of any measurement point F in the upper half of any measurement line. Let F be the polar angle of the measurement point. The polar angles of each measurement point in the lower half of the measurement line are given. Let S be the polar radius of any measurement point S in the lower half of the measurement line. Let F be the XY coordinates of the upper measurement point F on the upper half of the measurement line. Let S be the XY coordinates of the measurement point S on the lower half of the measurement line, and D be the diameter of the silicon wafer.

[0113] Step S4-3: Traverse all measurement points to construct Cartesian coordinates Parametric model.

[0114] Step S5: Construct a multidimensional grid structure model of the silicon wafer surface morphology based on the Cartesian coordinate parameter model.

[0115] Furthermore, the construction of the multidimensional grid structure model of the silicon wafer surface morphology in step S5 includes the following steps:

[0116] Step S5-1: Determine the acceptable quality area of ​​the silicon wafer: Refer to Figure 3 As shown, the circular ring with a width of d near the edge of the silicon wafer 100 is called the edge ring 10, and the other areas on the silicon wafer 100 other than the area where the edge ring 10 is located are called the quality qualified area 20. All measurement points are located within the quality qualified area 20.

[0117] Step S5-2: Based on the Cartesian coordinate parameter model in step S4, calculate the XY coordinates of all measurement points and generate a two-dimensional coordinate matrix XY_POINTS, where XY_POINTS = , , ,in, Indicates the first The X coordinates of each measurement point Indicates the first The Y-coordinate of each measurement point Present it in tabular form, with some data referenced. Figure 4 As shown, the number of rows represents the number of statistical measurement points, which varies depending on the number of statistical measurement points; there are two columns, the first column represents the X coordinate of the measurement point, and the second column represents the Y coordinate of the measurement point, both in mm;

[0118] Step S5-3, Data Vectorization: Convert the two-dimensional coordinate matrix XY_POINTS into a one-dimensional row vector X_POINTS containing only the X coordinates and a one-dimensional column vector Y_POINTS containing only the Y coordinates, respectively. X_POINTS = Y_POINTS= Then the extreme values ​​of the grid point coordinates in the grid structure are the maximum values ​​of the X coordinates. Minimum value of X coordinate Maximum value of Y coordinate minimum value of Y coordinate ;

[0119] Step S5-4: Determine the grid spacing of the grid structure model, including the grid length of the unit grid 30. , grid width and the number of grid cells, where the number of grid cells is determined by the grid length of the cells. , grid width Determined jointly by the limit values ​​of the grid point coordinates; refer to Figure 2 As shown, the cell grid 30 is distributed within the entire quality-compliant area 20;

[0120] Step S5-5: Construct a multi-dimensional grid structure model of the silicon wafer surface morphology based on the grid spacing. Ultimately, the design scope of the multi-dimensional grid structure model should cover the entire quality-compliant area allowed by the silicon wafer.

[0121] Further, step S5-5 includes the following steps:

[0122] Step S5-5-1: Calculate the limit values ​​of the grid point coordinates based on the silicon wafer diameter D and the edge ring width d, as follows:

[0123] Maximum value of X coordinate ;

[0124] Minimum value of X-coordinate =- ;

[0125] Maximum value of Y coordinate ;

[0126] Minimum value of Y coordinate =- ;

[0127] Step S5-5-2: Based on the grid length of cell grid 30 , grid width Calculate the distribution matrices of the first-dimensional and second-dimensional data in the raster structure model. The distribution matrix of the first-dimensional data is: The distribution matrix of the second dimension data is composed of... indivual Form a first-order matrix ,

[0128] in, ; ;

[0129] It is by indivual The first-order matrix formed

[0130] ;

[0131] ,

[0132] Step S5-5-3: Combining the distribution matrix and , obtain 2× × A three-dimensional matrix, including Grid points.

[0133] Specifically, the silicon wafer has a diameter D = 300 mm, an edge ring width d = 5 mm, and a grid length of 30. =Gate width Substituting a square grid of 1 mm into the above equations, we can obtain... , , , , Since the length and width of cell 30 are equal, refer to... Figure 5 and Figure 6 As shown, the matrix and All are 291×291 matrices. The final grid structure model is a 2 × 291 × 291 matrix, comprising 291*291 = 84681 grid points. See Figure 7 As shown.

[0134] Step S6: Traverse and analyze the characteristic parameter measurement values ​​of each measurement point to construct a measurement parameter information model.

[0135] Furthermore, the construction of the measurement parameter information model in step S6 includes the following steps:

[0136] Step S6-1: Based on the binary data in step S2, obtain a one-dimensional vector including the silicon wafer thickness value at each measurement point. This one-dimensional vector is the measurement parameter information vector. Specifically, in this embodiment, the number of measurement points is 2344, therefore the measurement parameter information vector is a 2344 × 1 one-dimensional vector. (Refer to...) Figure 8 As shown, these are the first 11 and last 11 elements of the silicon wafer measurement parameter information vector.

[0137] Step S6-2: Construct a measurement parameter information model based on the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model in step S4. The measurement parameter model is a relational function between the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model.

[0138] Step S7: Establish a silicon wafer surface morphology prediction algorithm model based on the measurement parameter information model.

[0139] Furthermore, the step S7 of establishing the silicon wafer surface morphology prediction algorithm model includes the following steps:

[0140] Step S7-1: Let the measurement parameter information model in step S6 be element z, the one-dimensional row vector X_POINTS in step S5-2 be element x, and the one-dimensional column vector Y_POINTS be element y. Assume the function... satisfy , n+1 represents the number of measurement points. In this embodiment, the number of measurement points is 2344, so n=2343. The following system of equations is constructed:

[0141] ;

[0142] make , , The matrix form of the system of equations is as follows:

[0143] ,

[0144] in, The two-dimensional coordinate matrix XY_POINTS is obtained from step S5-1; when the highest power n is a fixed value, the matrix A that can be determined is unique; when the highest power n is sufficiently large, i.e., it satisfies... , It can be determined that there is only one. Polynomial;

[0145] Step S7-2: Construct a piecewise cubic interpolation polynomial model, the specific formula of which is as follows:

[0146] ;

[0147] Where n is the total number of measurement points and the number of points contained in the segmented unit; Let x be the x-coordinate value of the (i+1)th measurement point under the Cartesian coordinate parameter model of the silicon wafer; Let represent the ordinate value of the (i+1)th measurement point in the Cartesian coordinate parameter model of the silicon wafer. Obtained from the two-dimensional coordinate matrix XY_POINTS in step S5-1, .

[0148] Step S8: Calculate the surface morphology parameters of the silicon wafer based on the silicon wafer surface morphology prediction algorithm model and the multidimensional grid structure model in step S5.

[0149] Further, in step S8, the silicon wafer surface morphology parameters are calculated based on the silicon wafer surface morphology prediction algorithm model as follows:

[0150] Substituting the multidimensional grid structure model of the silicon wafer surface morphology from step S5 into the piecewise cubic interpolation polynomial model formula in step S7-2, a two-dimensional matrix of the predicted measurement parameter values ​​of all grid points in the multi-grid structure model is obtained. The matrix size is... × The matrix size is 291×291, and it is displayed in tabular form, with some elements referenced. Figure 9As shown. At this time, there are 291*291=84681 grid points in the multi-grid structure model; these grid points, together with the coordinate values ​​and measurement data values ​​of n+1 (i.e. 2344) measurement points, constitute the basic elements of the silicon wafer surface morphology parameters.

[0151] Step S9: Generate a silicon wafer surface morphology map based on the silicon wafer surface morphology parameters.

[0152] Further, in step S9, generating a silicon wafer surface morphology map based on silicon wafer surface morphology parameters refers to drawing a two-dimensional or three-dimensional silicon wafer surface morphology map as needed, combining the basic elements of the silicon wafer surface morphology parameters, wherein, referring to Figure 10 As shown, the two-dimensional silicon wafer surface topography is drawn in the XY coordinate system using contour plotting. The color of each point on the silicon wafer represents the measured value of its characteristic parameter, namely the thickness of the silicon wafer. Figure 10 The image clearly shows the thickness distribution of different parts of the silicon wafer, providing a more intuitive view of the thickness distribution in various areas and the overall thickness, facilitating subsequent adjustments. (Refer to...) Figure 11 As shown, the 3D silicon wafer surface topography is drawn using contour lines and a 3D plotting method within the XYZ coordinate system. The Z-axis value represents the measured value of the characteristic parameter at that point, i.e., the thickness of the silicon wafer. (Refer to...) Figure 12 As shown, this is a top-down view of the three-dimensional silicon wafer surface topography along the z-axis.

[0153] Finally, according to the semiconductor silicon wafer surface morphology model prediction method based on measurement data of the present invention, the surface morphology can be predicted based on limited measurement data. Compared with existing discrete data, the surface morphology map predicted by the present invention covers every point on the entire silicon wafer surface, which can fully reflect the actual surface morphology of the silicon wafer, with high accuracy, and facilitates the overall surface morphology evaluation of the silicon wafer. The generated surface morphology map allows users to conduct intuitive visual observation, quickly identify abnormal data, and then identify problematic machines based on the abnormal data, and make modifications in advance to address the problems. This enables monitoring of silicon wafers in production processes such as wire cutting, thinning, or polishing, optimizing the manufacturing process, thereby improving silicon wafer yield and reducing costs.

[0154] Example 2

[0155] Taking a silicon wafer with a diameter D of 300mm as an example, the thickness of the silicon wafer is a measured value of a characteristic parameter. This measured value is the silicon wafer thickness at each measurement point, and the number of measurement points n+1 is 2344. The width of the edge ring d=5mm, and the unit grid 30 is the grid length. =2mm, gate width =1 mm grid. In other words, based on Example 1, only the size of the cell grid is changed, while other conditions or steps remain unchanged.

[0156] Substituting the above parameters into the corresponding formulas, we can obtain... , , , , , Then the matrix yes ,Right now The matrix, yes The final grid structure model is a 2 × 146 × 291 three-dimensional matrix, comprising ( )*( ) == 146 * 291 = 42486 grid points. At this point, the corresponding matrix... ,matrix and three-dimensional matrices are respectively as follows Figures 13 to 15 As shown.

[0157] Finally, the two-dimensional silicon wafer surface topography diagram drawn in the XY coordinate system using contour plotting is as follows: Figure 16 As shown, the color of each point on the silicon wafer represents the thickness value at that point.

[0158] Example 3

[0159] Taking a silicon wafer with a diameter D of 300mm as an example, the number of measurement points n+1 is 2344; the width of the edge ring d=5mm; the unit grid 30 is the grid length. =1mm, gate width =1 mm grid; with the warpage of the silicon wafer as the characteristic parameter measurement value, the measurement value is the warpage of each measurement point.

[0160] In other words, based on Example 1, this example only replaces the thickness value of the measurement point with the warp value of the measurement point, while other conditions or steps remain unchanged.

[0161] Specifically, compared with Example 1, in step S1 of this example, except for the characteristic parameter measurement value of warp, the number of measurement lines, the angle of each measurement line, and the spacing between each measurement point on each measurement line have not changed.

[0162] In step S2, converting the original measurement data into binary data means converting the data, including the warp of each measurement point, into binary data.

[0163] The construction methods of the silicon wafer polar coordinate parameter model, silicon wafer Cartesian coordinate parameter model, and silicon wafer surface morphology multidimensional grid structure model in steps S3 to S5, as well as the final constructed models, are consistent with those in Example 1, and will not be repeated here.

[0164] In step S6, constructing a measurement parameter information model by traversing and analyzing the characteristic parameter measurement values ​​of each measurement point means: first, obtaining a one-dimensional vector including the silicon wafer warpage of each measurement point based on the binary data in step S2; this one-dimensional vector is the measurement parameter information vector; then, constructing a measurement parameter information model based on the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model in step S4; the measurement parameter model is the relationship function between the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model.

[0165] The methods for predicting silicon wafer surface morphology, calculating silicon wafer surface morphology parameters, and generating silicon wafer surface morphology maps in steps S7 to S9 are all the same as in Example 1, and will not be repeated here.

[0166] Finally, the two-dimensional silicon wafer surface topography diagram drawn in the XY coordinate system using contour plotting is as follows: Figure 17 As shown, the color of each point on the silicon wafer represents the warpage at that point.

[0167] Example 4

[0168] Based on Example 3, the size of the cell grid is changed to the grid length. =2mm, gate width =1 mm, other conditions or steps remain unchanged.

[0169] Substituting the parameters into the formulas above, we can obtain... , , , , , Then the matrix yes ,Right now The matrix, yes The final grid structure model is a 2 × 146 × 291 three-dimensional matrix, comprising ( )*( ) == 146 * 291 = 42486 grid points. At this point, the corresponding matrix... ,matrix and three-dimensional matrices are respectively as follows Figures 13 to 15 As shown.

[0170] Finally, the two-dimensional silicon wafer surface topography diagram drawn in the XY coordinate system using contour plotting is as follows: Figure 18 As shown, the color of each point on the silicon wafer represents the warpage at that point.

[0171] Reference Figure 10 , Figures 16 to 18It is evident that using different cell grid sizes results in varying cell counts and cell point counts, leading to silicon wafer surface topography maps with different levels of accuracy. In other words, the accuracy of the prediction model changes as the cell grid size changes within the multidimensional grid structure model; under the same conditions, smaller cell grids result in higher accuracy. However, considering that the cell count is determined by both the cell grid size and the grid point coordinate limits in step S5, more cells are not necessarily better. Therefore, a reasonable point selection rule must be adopted to match the surface topography algorithm prediction model in step S7.

[0172] Of course, the characteristic parameter measurement values ​​of each measurement point in the original measurement data in step S1 can be the thickness value or warpage mentioned above, or they can be characteristic parameters such as curvature and flatness. As long as the corresponding measurement parameters are adjusted, the prediction method of the overall silicon wafer surface morphology remains unchanged. Therefore, in addition to being able to predict the surface morphology based on limited measurement data, avoiding the various losses caused by only being able to view the data on a single measurement line and being unable to evaluate the overall surface morphology of the silicon wafer, and being able to make modifications in advance for possible problems, effectively improving the silicon wafer yield, this invention has good portability and flexibility, can adapt to different changes, and can generate silicon wafer surface morphology maps corresponding to different parameters as needed.

[0173] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0174] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0175] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0176] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0177] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0178] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for predicting the surface morphology of semiconductor silicon wafers based on measurement data, characterized in that, Includes the following steps: Step S1: Obtain the original measurement data of a silicon wafer with a diameter of D arranged in a straight line in the measurement machine. The original measurement data includes: the number of scanning measurement lines, the angle of each measurement line, the spacing between each measurement point on each measurement line, and the measurement value of the characteristic parameters of each measurement point. Step S2: Convert the raw measurement data into binary data; Step S3: Traverse and analyze the data of each measurement point to construct a polar coordinate parameter model of the silicon wafer; Step S4: Construct a silicon wafer Cartesian coordinate parameter model based on the polar coordinate parameter model; Step S5: Construct a multidimensional grid structure model of the silicon wafer surface morphology based on the Cartesian coordinate parameter model; Step S6: Traverse and analyze the characteristic parameter measurement values ​​of each measurement point to construct a measurement parameter information model; Step S7: Establish a silicon wafer surface morphology prediction algorithm model based on the measurement parameter information model; Step S8: Calculate the silicon wafer surface morphology parameters based on the silicon wafer surface morphology prediction algorithm model and the multidimensional grid structure model in step S5. Step S9: Generate a silicon wafer surface morphology map based on the silicon wafer surface morphology parameters; The step of traversing and analyzing the characteristic parameter measurement values ​​of each measurement point to construct a measurement parameter information model includes: obtaining a one-dimensional vector containing the characteristic parameter measurement values ​​of each measurement point based on the binary data in step S2, which is the measurement parameter information vector; constructing a measurement parameter information model based on the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model in step S4, wherein the measurement parameter information model is a relationship function between the measurement parameter information vector and the silicon wafer Cartesian coordinate parameter model; The construction of the multidimensional grid structure model of the silicon wafer surface morphology in step S5 includes the following steps: Step S5-1: Determine the qualified quality area of ​​the silicon wafer: The ring with a width of d near the edge of the silicon wafer is the edge ring. The other areas on the silicon wafer except for the area where the edge ring is located are the qualified quality areas. All measurement points are located within the qualified quality areas. Step S5-2: Based on the Cartesian coordinate parameter model in step S4, calculate the XY coordinates of all measurement points and generate a two-dimensional coordinate matrix XY_POINTS, where XY_POINTS = , , ,in, Indicates the first The X coordinates of each measurement point Indicates the first The Y-coordinate of each measurement point ; Step S5-3, Data Vectorization: Convert the two-dimensional coordinate matrix XY_POINTS into a one-dimensional row vector X_POINTS containing only the X coordinate and a one-dimensional column vector Y_POINTS containing only the Y coordinate, respectively. Then, the extreme values ​​of the grid point coordinates in the grid structure are the maximum values ​​of the X coordinates. Minimum value of X coordinate Maximum value of Y coordinate minimum value of Y coordinate ; Step S5-4: Determine the grid spacing of the grid structure model, including the grid length of the unit grid. , grid width The number of grids, where the limiting values ​​of the grid point coordinates are determined by the silicon wafer diameter D and the width d of the silicon wafer edge annulus according to the following formula: Maximum value of X coordinate ; Minimum value of X-coordinate =- ; Maximum value of Y coordinate ; Minimum value of Y coordinate =- ; The number of grid cells is determined by the grid length of the cells. , grid width The extreme values ​​of the grid point coordinates are calculated and determined according to the following formula: Number of grid cells in the X direction Number of grid cells in the Y direction Step S5-5: Construct a multi-dimensional grid structure model of the silicon wafer surface morphology based on the grid spacing; The step S7 of establishing the silicon wafer surface morphology prediction algorithm model includes the following steps: Step S7-1: Let the measurement parameter information model in step S6 be element z, the one-dimensional row vector X_POINTS in step S5-2 be element x, and the one-dimensional column vector Y_POINTS be element y. Assume the function... satisfy , Let n+1 be the number of measurement points; construct the following system of equations: ； make , , Then the matrix form of the system of equations is as follows: ， in, Obtained from the two-dimensional coordinate matrix XY_POINTS in step S5-2; When the highest power n is a fixed value, the matrix A that can be determined is unique; according to , Determine the only one Polynomial; Step S7-2: Construct a piecewise cubic interpolation polynomial model, the specific formula of which is as follows: ； Where n is the total number of measurement points and the number of points contained in the segmented unit; Let x be the x-coordinate value of the (i+1)th measurement point under the Cartesian coordinate parameter model of the silicon wafer; Let represent the ordinate value of the (i+1)th measurement point in the Cartesian coordinate parameter model of the silicon wafer. Obtained from the two-dimensional coordinate matrix XY_POINTS in step S5-2, .

2. The method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data according to claim 1, characterized in that, The step S3 of constructing the polar coordinate parameter model of the silicon wafer includes the following steps: Step S3-1: Use the center of the silicon wafer as the pole in the polar coordinate system. ; Step S3-2: When constructing the polar coordinate system, ensure that the notch position on the silicon wafer is directly below the center of the silicon wafer circle. The notch position on the silicon wafer is then used as the reference point. Starting from the center of the silicon wafer, rotate 90 degrees counterclockwise to the end point. ,point With the extreme point The formed rays It is the polar axis; Step S3-3: Each measurement line is divided into an upper half and a lower half by the line containing the polar axis. The polar angles of all measurement points on the upper half of the same measurement line are the same, and the polar angles of all measurement points on the lower half of the same measurement line are the same. The difference between the polar angles of measurement points in the upper half and the lower half of the same measurement line is... Measurement points and poles on the measurement line The distance between the radial distances is The polar angle is Then the polar coordinates of the measurement point are ; Step S3-4: Traverse all measurement points to construct silicon wafer polar coordinates Parametric model.

3. The method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data according to claim 2, characterized in that, The step S4 of constructing the Cartesian coordinate parameter model of the silicon wafer includes the following steps: Step S4-1: Construct a Cartesian coordinate system for the surface morphology of the silicon wafer: using the poles from step S3-1... Using the origin of the Cartesian coordinate system, the polar axis of step S3-2 is taken as the positive x-axis direction of the Cartesian coordinate system; Step S4-2: Calculate the coordinates of each measurement point on the silicon wafer in the Cartesian coordinate system according to the first to fifth formulas. The first to fifth formulas are as follows: First formula: ; Second formula: ; Third formula: ; Fourth formula: ; Fifth formula: For measurement points on the same measurement line, ; in, Let F be the polar radius of any measurement point F in the upper half of any measurement line. Let F be the polar angle of the measurement point. The polar angles of each measurement point in the lower half of the measurement line are given. Let S be the polar radius of any measurement point S in the lower half of the measurement line. Let F be the XY coordinates of the upper measurement point F on the upper half of the measurement line. Let S be the XY coordinates of the measurement point S on the lower half of the measurement line, and D be the diameter of the silicon wafer. Step S4-3: Traverse all measurement points to construct Cartesian coordinates Parametric model.

4. The method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data according to claim 1, characterized in that, Step S5-5 includes the following steps: Step S5-5-1: Calculate the limit values ​​of grid point coordinates based on the silicon wafer diameter D and the edge ring width d; Step S5-5-2: Based on the grid length of the cell grid Grid width Calculate the distribution matrices of the first-dimensional and second-dimensional data in the raster structure model. The distribution matrix of the first-dimensional data is: ; The distribution matrix of the second-dimensional data is derived from... indivual Form a first-order matrix , in, ; ; It is by indivual The first-order matrix formed ； ， Step S5-5-3: Combining the distribution matrix and , obtain 2× × A three-dimensional matrix, including Grid points.

5. The method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data according to claim 1, characterized in that, In step S8, the silicon wafer surface morphology parameters are calculated based on the silicon wafer surface morphology prediction algorithm model as follows: Substituting the multidimensional grid structure model of the silicon wafer surface morphology from step S5 into the piecewise cubic interpolation polynomial model formula in step S7-2, a two-dimensional matrix of the predicted measurement parameter values ​​of all grid points in the multi-grid structure model is obtained. The matrix size is... × In the corresponding multi-grid structure model There are n+1 grid points; the coordinates and measurement data of these grid points together constitute the basic elements of the silicon wafer surface topography parameters.

6. The method for predicting the surface morphology of a semiconductor silicon wafer based on measurement data according to claim 5, characterized in that, In step S9, generating a silicon wafer surface topography map based on the silicon wafer surface topography parameters refers to drawing a two-dimensional or three-dimensional silicon wafer surface topography map according to the basic elements of the silicon wafer surface topography parameters. The two-dimensional silicon wafer surface topography map is drawn in the XY coordinate system using contour lines, and the color of each point on the silicon wafer represents the measured value of the characteristic parameter of that point. The three-dimensional silicon wafer surface topography map is drawn in the XYZ coordinate system using contour lines plus three-dimensional drawing, and the Z-axis value represents the measured value of the characteristic parameter of that point.

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