Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a protrusion on a substrate discretely located in a device region; a channel structure on the protrusion; an isolation layer on the substrate surrounding the protrusion and exposing the channel structure; a buried power rail penetrating the isolation layer and a portion of the substrate thickness, the buried power rail being parallel and spaced apart from the protrusion; a gate structure on the isolation layer and spanning the channel structure; source / drain doped regions located in the channel structures on both sides of the gate structure; an interlayer dielectric layer on the isolation layer on the side of the gate structure and covering the source / drain doped regions; and a source / drain interconnect layer penetrating the source / drain doped regions and the interlayer dielectric layer on top of the buried power rail, the source / drain interconnect layer contacting the source / drain doped regions, and the bottom of the source / drain interconnect layer contacting the top surface of the buried power rail. This eliminates the need for a contact plug (Via) to achieve electrical connection between the source / drain interconnect layer and the buried power rail, thus optimizing the electrical connection performance between the source / drain interconnect layer and the buried power rail.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To meet the ever-growing needs of logic chip miniaturization, and to optimize power supply capabilities when metal spacing is very tight, one approach is to move the power rails down into the substrate to form buried power rails (BPR).

[0003] In buried power rail structures, power rails are embedded in the substrate, extending deep into the shallow trench isolation (STI) module, thereby freeing up interconnect wiring resources. Furthermore, buried power rails provide lower resistive local current distribution for techniques that increase BEOL resistance through pitch reduction. Additionally, buried power rails help reduce the effects of wiring congestion and resistance degradation on the grid-like distribution of VDD, VSS, word lines, and bit lines, improving write margin and read speed. Moreover, in transistors, buried power rails are typically connected to the source-drain interconnect layer, thereby supplying power to the source-drain doped regions through the source-drain interconnect layer.

[0004] However, the electrical connection performance between the buried power rail and the source-drain interconnect layer is currently poor. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which optimizes the electrical connection performance between the source / drain interconnect layer and the buried power rail.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a plurality of discrete device regions and a power rail region located between the device regions; a protrusion discretely located on the substrate of the device regions; a channel structure located on the protrusion; an isolation layer located on the substrate, surrounding the protrusion and exposing the channel structure; a buried power rail penetrating the isolation layer and a portion of the substrate thickness within the power rail region, the buried power rail being disposed parallel to and spaced apart from the protrusion; a gate structure located on the isolation layer and spanning the channel structure; source / drain doped regions located in the channel structures on both sides of the gate structure; an interlayer dielectric layer located on the isolation layer on the side of the gate structure and covering the source / drain doped regions; and a source / drain interconnect layer penetrating the source / drain doped regions and the interlayer dielectric layer on the top of the buried power rail, the source / drain interconnect layer contacting the source / drain doped regions, and the bottom of the source / drain interconnect layer contacting the top surface of the buried power rail.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a plurality of discrete device regions and a power rail region located between the device regions, wherein discrete protrusions are formed on the substrate of the device regions, a channel structure is formed on the protrusions, an isolation layer is formed on the substrate surrounding the protrusions, the isolation layer exposes the channel structure, and a buried power rail is formed in the isolation layer and a partially thick substrate of the power rail region, the buried power rail being disposed parallel to and spaced apart from the protrusions; forming a gate structure located on the isolation layer and spanning the channel structure, source / drain doped regions in the channel structures located on both sides of the gate structure, and an interlayer dielectric layer located on the isolation layer on the side of the gate structure and covering the source / drain doped regions; forming a source / drain interconnect layer penetrating the source / drain doped regions and the top of the interlayer dielectric layer on the buried power rail, the source / drain interconnect layer being in contact with the source / drain doped regions, and the bottom of the source / drain interconnect layer being in contact with the top surface of the buried power rail.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention has a source-drain interconnect layer that contacts the source-drain doped region, and the bottom of the source-drain interconnect layer also contacts the top surface of the buried power rail. Therefore, the source-drain interconnect layer and the buried power rail do not need to be electrically connected via a contact plug (Via). This not only shortens the current transmission path between the source-drain interconnect layer and the buried power rail, but also prevents excessive resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnect layer and the buried power rail. This optimizes the electrical connection performance between the source-drain interconnect layer and the buried power rail, thereby improving power supply efficiency.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, in the step of forming the source-drain interconnect layer, the source-drain interconnect layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnect layer is also in contact with the top surface of the buried power rail. Therefore, the source-drain interconnect layer and the buried power rail do not need to be electrically connected through a contact plug (Via). This not only shortens the current transmission path between the source-drain interconnect layer and the buried power rail, but also prevents the excessive resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnect layer and the buried power rail. This optimizes the electrical connection performance between the source-drain interconnect layer and the buried power rail and improves power supply efficiency. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a semiconductor structure;

[0012] Figures 2 to 3This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 4 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As can be seen from the background technology, the electrical connection performance between buried power rails and source-drain interconnect layers is currently poor.

[0015] Specifically, in conjunction with reference Figure 1 This is a partial cross-sectional view of a semiconductor structure. The source / drain interconnect layer 1 penetrates the interlayer dielectric layer 3 above the source / drain doped region 2, serving to achieve electrical connection between the source / drain doped region 2 and external circuitry. The buried power rail 4 is located in the substrate 5, with its top surface lower than the bottom surface of the source / drain interconnect layer 1. Therefore, as shown... Figure 1 As shown, a power rail contact plug (Via) 6 is typically required to achieve electrical connection between the source / drain interconnect layer 1 and the buried power rail 4.

[0016] The power rail contact plug 6 typically has a large aspect ratio, resulting in high resistance. This leads to poor electrical connection performance between the source / drain interconnect layer and the buried power rail 4, affecting the power supply efficiency to the source / drain doped region 2. In particular, as device dimensions continue to shrink, the critical dimensions of the power rail contact plug 6 also decrease, while its aspect ratio increases. Therefore, the impact of the power rail contact plug 6 on the electrical connection performance between the source / drain interconnect layer 1 and the buried power rail 4 is becoming increasingly significant.

[0017] To address the technical problem, this invention provides a semiconductor structure in which the source-drain interconnect layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnect layer is in contact with the top surface of the buried power rail. This eliminates the need for a contact plug (Via) to achieve electrical connection between the source-drain interconnect layer and the buried power rail. This not only shortens the current transmission path between the source-drain interconnect layer and the buried power rail but also prevents excessive resistance of the contact plug from negatively impacting the electrical connection performance between the source-drain interconnect layer and the buried power rail. Consequently, this optimizes the electrical connection performance between the source-drain interconnect layer and the buried power rail and improves power supply efficiency.

[0018] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 2 to 3 The top view and the bottom view are respectively. Figure 2 A cross-sectional view along the a-a1 direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0019] like Figure 2 and Figure 3As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including a plurality of discrete device regions 100a and power rail regions 100b located between the device regions 100a; a protrusion 105, discretely located on the substrate 100 of the device regions 100a; a channel structure 110, located on the protrusion 105; an isolation layer 115, located on the substrate 100 and surrounding the protrusion 105, and exposing the channel structure 110; and a buried power rail 120, penetrating the isolation layer 115 and a portion of the substrate 100 of the power rail region 100b, burying the power rail 120 between the protrusion 105 and the device regions 100a. Parallel spacing is provided; a gate structure 130 is located on the isolation layer 115 and spans the channel structure 110; source / drain doped regions 140 are located in the channel structures 110 on both sides of the gate structure 130; an interlayer dielectric layer 150 is located on the isolation layer 115 on the side of the gate structure 130 and covers the source / drain doped regions 140; a source / drain interconnect layer 180 penetrates the source / drain doped regions 140 and the interlayer dielectric layer 150 on the top of the buried power rail 120, the source / drain interconnect layer 180 is in contact with the source / drain doped regions 140, and the bottom of the source / drain interconnect layer 180 is in contact with the top surface of the buried power rail 120.

[0020] Substrate 100 provides a process platform for the formation of semiconductor structures. The material of substrate 100 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, substrate 100 is a silicon substrate.

[0021] Device region 100a is used to form field-effect transistors, such as one or both of PMOS and NMOS transistors. Power rail region 100b is used to set up buried power rails 120.

[0022] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure, and the material of the protrusion 105 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0023] When the device is operating, the channel structure 110 is used to provide a conductive channel for the field-effect transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0024] As an example, device region 100a is used to form a fin field-effect transistor (FinFET). Accordingly, the channel structure 110 is a fin. Specifically, the fin is connected to the protrusion 105. In this embodiment, the fin and the protrusion 105 are an integral structure.

[0025] In this embodiment, the material of the fin is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other semiconductor materials suitable for forming fins, and the material of the fin may also be different from the material of the substrate.

[0026] In other embodiments, when the first device and the second device are Gate-All Around (GAA) transistors or Forksheet transistors, the channel structure can also be a channel structure layer, with the channel structure layer and the protrusions spaced apart, and the channel structure layer including one or more channel layers spaced apart in sequence.

[0027] In this embodiment, both the channel structure 110 and the protrusion 105 extend laterally, and the multiple protrusions 105 or the multiple channel structures 110 are arranged sequentially at intervals along the longitudinal direction. The lateral direction is perpendicular to the longitudinal direction.

[0028] The isolation layer 115 is used to isolate adjacent protrusions 105, and the isolation layer 115 is also used to isolate the substrate 100 from the subsequent gate structure. In this embodiment, the isolation layer 115 is a shallow trench isolation layer (STI), and the material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0029] In this embodiment, the top surface of the isolation layer 115 is flush with the top surface of the protrusion 105.

[0030] In this embodiment, the buried power rail 120 is used to provide power to different components of the chip. In this embodiment, the buried power rail 120 is located in the substrate 100 of the power rail region 100b. The buried power rail 120 is a buried power rail (BPR), which is beneficial for freeing up wiring resources for back-end interconnects and for reducing the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rail uses the technique of increasing back-end of line (BEOL) resistance by reducing pitch, which is also beneficial for providing a lower resistance local current distribution.

[0031] Both the buried power rail 120 and the trench structure 110 extend laterally, and there is a gap between the buried power rail 120 and the trench structure 110. The direction perpendicular to the lateral direction is the longitudinal direction.

[0032] The buried power rail 120 is made of a conductive material. In this embodiment, the buried power rail 120 is made of a metallic material, such as one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the buried power rail 120 is low, which is beneficial for improving RC delay, increasing chip processing speed, and power supply efficiency.

[0033] In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115.

[0034] The top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, thereby exposing the top surface of the isolation layer 115. The top surface of the buried power rail 120 is relatively high, making it easier for the bottom of the source-drain interconnect layer 180 to contact the top surface of the buried power rail 120. This helps to reduce the process difficulty of forming the source-drain interconnect layer, improve process compatibility and process stability.

[0035] In other embodiments, the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer; the semiconductor structure further includes a covering dielectric layer located in the isolation layer and located on the top surface of the buried power rail.

[0036] The overlay dielectric layer is used to isolate buried power rails from the gate structure, or to isolate buried power rails from other conductive structures located on the isolation layer. The overlay dielectric layer is made of a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the overlay dielectric layer is made of the same material as the isolation layer, which improves process compatibility.

[0037] Specifically, the top surface of the covering dielectric layer is flush with the top surface of the isolation layer so that the top surface of the isolation layer is a flat surface, which is conducive to the formation of the gate structure.

[0038] The top surface of the buried power rail 120 is lower than or flush with the top surface of the isolation layer 115. Along the direction perpendicular to the surface of the substrate 100, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 should not be too large. Otherwise, if the covering dielectric layer on the top surface of the buried power rail 120 is too thick, the source / drain interconnect layer will need to penetrate the covering dielectric layer to contact the top surface of the buried power rail 120. If the covering dielectric layer on the top surface of the buried power rail 120 is too thick, the source / drain interconnect layer 180 will be too deep, increasing the difficulty of forming the source / drain interconnect layer 180, reducing process compatibility, and increasing process risks. Therefore, in this embodiment, along the direction perpendicular to the surface of the substrate 100, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0 nm to 15 nm.

[0039] When the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0nm, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115.

[0040] In this embodiment, the semiconductor structure further includes an insulating layer 125 located between the buried power rail 120 and the substrate 100, and between the buried power rail 120 and the isolation layer 115. The insulating layer 125 is used to achieve electrical isolation between the buried power rail 120 and the substrate 100. The insulating layer 125 is made of an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0041] When the device is in operation, the gate structure 130 is used to control the opening or closing of the conductive channel.

[0042] Specifically, in this embodiment, the gate structure 130 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure spans the channel structure layer and surrounds the channel layer.

[0043] The extension direction of the gate structure 130 is perpendicular to the extension direction of the channel structure 110, that is, the gate structure 130 extends longitudinally. In this embodiment, there are multiple gate structures 130, which are arranged at lateral intervals.

[0044] In this embodiment, the gate structure 130 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0045] The gate structure 130 is made of a conductive material. The material of the gate structure 130 includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. Specifically, the gate structure 130 may include a work function layer (not shown) and a metal electrode layer located on the work function layer; alternatively, the gate structure 130 may be a work function layer or a metal electrode layer.

[0046] In this embodiment, the semiconductor structure further includes a gate dielectric layer (not shown) located between the gate structure 130 and the channel structure 110. In this embodiment, the gate dielectric layer is also located between the gate structure 130 and the top surface of the isolation layer 115. The gate dielectric layer is used to achieve insulation between the gate structure 130 and the conductive channel.

[0047] Specifically, when the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, the gate dielectric layer is also located between the gate structure 130 and the buried power rail 120 to achieve insulation between the gate structure 130 and the buried power rail 120. In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a cover dielectric layer is also formed on the top surface of the buried power rail, the gate dielectric layer is correspondingly located between the gate structure and the cover dielectric layer.

[0048] The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

[0049] The semiconductor structure further includes a sidewall (not shown) located on the sidewall of the gate structure 130. The sidewall is used to protect the sidewall of the gate structure 130 and also to define the formation location of the source / drain doped regions 140.

[0050] The source / drain doped region 140 serves as the source or drain of the field-effect transistor (FET). During FET operation, the source / drain doped region 140 provides a carrier source. Specifically, the source / drain doped region 140 is located within the channel structure 110 on both sides of the gate structure 130 and the sidewalls. In this embodiment, the source / drain doped region 140 is located within the fins on both sides of the gate structure 130 and the sidewalls.

[0051] In this embodiment, the source / drain doped region 140 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. When forming a PMOS transistor, the source / drain doped region 140 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped region 140 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC.

[0052] The interlayer dielectric layer 150 is used to isolate adjacent devices and also to electrically isolate adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation layer 115 on the side of the gate structure 130.

[0053] In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, and the interlayer dielectric layer 150 also covers the top surface of the buried power rail 120. In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top of the buried power rail, the interlayer dielectric layer also covers the covering dielectric layer accordingly.

[0054] The interlayer dielectric layer 150 is made of an insulating material. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. It should be noted that, for ease of illustration and explanation, only the insulating layer 115 and the interlayer dielectric layer 150 are shown in the cross-sectional view.

[0055] The source / drain interconnect layer 180 contacts the source / drain doped region 140 to enable electrical connection between the source / drain doped region 140 and external circuitry or other interconnect structures. The bottom of the source / drain interconnect layer 180 contacts the top surface of the buried power rail 120, thereby enabling electrical connection between the source / drain interconnect layer 180 and the buried power rail 120, so that power can be supplied to the source / drain doped region 140 through the buried power rail 120 when the device is in operation.

[0056] Furthermore, the bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120, so that the source-drain interconnect layer 180 and the buried power rail 120 do not need to be electrically connected through a contact plug (Via). This not only shortens the current transmission path between the source-drain interconnect layer 180 and the buried power rail 120, but also helps to prevent the resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnect layer and the buried power rail, thereby optimizing the electrical connection performance between the source-drain interconnect layer 180 and the buried power rail 120 and improving power supply efficiency.

[0057] Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115. Thus, when the source-drain interconnect layer 180 penetrates the source-drain doped region 140 and the interlayer dielectric layer 150 on top of the buried power rail 120, the source-drain interconnect layer 180 can contact the source-drain doped region 140 and the bottom surface of the source-drain interconnect layer 180 can contact the buried power rail 120. This helps to reduce the difficulty of making direct contact between the source-drain interconnect layer 180 and the buried power rail 120.

[0058] In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is also formed on the top surface of the buried power rail, the source-drain interconnect layer correspondingly penetrates the interlayer dielectric layer on the top of the source-drain doped region, as well as the covering dielectric layer and interlayer dielectric layer on the top of the buried power rail, which can also achieve the purpose of the source-drain interconnect layer contacting the source-drain doped region and the bottom of the source-drain interconnect layer contacting the top surface of the buried power rail.

[0059] In this embodiment, the source-drain interconnect layer 180 extends longitudinally, and the extension direction of the source-drain interconnect layer 180 is perpendicular to the extension direction of the buried power rail 120.

[0060] In this embodiment, the bottom of the source-drain interconnect layer 180 is flush with the top surface of the buried power rail 120, which achieves the purpose of the bottom of the source-drain interconnect layer 180 contacting the top surface of the buried power rail 120, and the bottom surface of the source-drain interconnect layer 180 is not too low, which is beneficial to improving process compatibility and process stability.

[0061] In other embodiments, the bottom of the source-drain interconnect layer may be lower than the top surface of the buried power rail and higher than the top surface of the substrate. This allows the bottom of the source-drain interconnect layer to contact the top surface of the buried power rail. Furthermore, it helps ensure that the bottom of each source-drain interconnect layer can contact the top surface of the buried power rail, reducing the probability that some source-drain interconnect layers will not be able to contact the buried power rail due to inconsistent bottom heights. This, in turn, ensures the electrical connection performance between the source-drain interconnect layer and the buried power supply. Specifically, the source-drain interconnect layer also extends through a partial thickness of the isolation layer.

[0062] The source-drain interconnect layer 180 is made of a conductive material, including one or more of W, Co, Cu, Ru, and Ni. The low resistivity of the material helps reduce the resistance of the source-drain interconnect layer 180, thereby reducing RC delay and improving the performance of the semiconductor structure.

[0063] In this embodiment, the semiconductor structure further includes a silicide layer 170 located between the source / drain interconnect layer 180 and the source / drain doped region 140. The silicide layer 170 reduces the contact resistance between the source / drain interconnect layer 180 and the source / drain doped region 140, and during device operation, current flows through the source / drain interconnect layer 180 and across the surface of the silicide layer 170. In this embodiment, the material of the silicide layer 170 can be a nickel-silicon compound, a cobalt-silicon compound, or a titanium-silicon compound.

[0064] In an alternative embodiment, the semiconductor structure further includes: a partition layer 190, which penetrates a portion of the source-drain interconnect layer 180 located in the power rail region 100b, and the partition layer 190 longitudinally partitions the source-drain interconnect layer 180 located in the adjacent device region 100a.

[0065] By setting the split layer 190, the source-drain interconnect layer 180 can be disconnected at locations where it is not needed, and the source-drain interconnect layer 180, which does not need to be electrically connected to the buried power rail 120, can be isolated from the buried power rail 120, thereby increasing the design freedom of the source-drain interconnect layer 180.

[0066] In other embodiments, based on actual process requirements, the semiconductor structure may not have a partition layer, and the source and drain interconnect layers of adjacent device regions may be connected along the longitudinal direction.

[0067] As an example, the steps of forming the source-drain interconnect layer 180 include: forming a source-drain interconnect trench through the source-drain doped region 140 and the interlayer dielectric layer 150 on top of the buried power rail 120; and forming the source-drain interconnect layer 180 in the source-drain interconnect trench.

[0068] In the step of forming the source-drain interconnect trench, a portion of the width of the interlayer dielectric layer 150 located longitudinally between adjacent device regions 100a is retained as the partition layer 190. Accordingly, the material of the partition layer 190 is the same as the material of the interlayer dielectric layer 150. In other embodiments, the material of the partition layer may be different from the material of the interlayer dielectric layer, and the material of the partition layer may also be other materials with electrical isolation properties.

[0069] As an example, the source-drain interconnect layer 180 located on either side of the partition layer 190 is in contact with the buried power rail 120.

[0070] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0071] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0072] refer to Figures 4 to 8 A substrate 100 is provided, including a plurality of discrete device regions 100a and power rail regions 100b located between the device regions 100a. Discrete protrusions 105 are formed on the substrate 100 of the device regions 100a. A channel structure 110 is formed on the protrusions 105. An isolation layer 115 is formed on the substrate 100 surrounding the protrusions 105. The isolation layer 115 exposes the channel structure 110. A buried power rail 120 is formed in the isolation layer 115 and a portion of the substrate 100 of the power rail region 100b. The buried power rail 120 is disposed parallel to and spaced apart from the protrusions 105.

[0073] Substrate 100 serves as a process platform for subsequent fabrication processes. The material of substrate 100 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, substrate 100 is a silicon substrate.

[0074] Device region 100a is used to form field-effect transistors, such as one or both of PMOS and NMOS transistors. Power rail region 100b is used to set up buried power rails 120.

[0075] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure, and the material of the protrusion 105 and the substrate 100 is the same, both being silicon. For a detailed description of the material of the protrusion 105, please refer to the corresponding description in the foregoing embodiments, and it will not be repeated here.

[0076] When the device is operating, the channel structure 110 is used to provide a conductive channel for the field-effect transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0077] As an example, device region 100a is used to form a fin field-effect transistor (FinFET). Accordingly, the channel structure 110 is a fin. Specifically, the fin is connected to the protrusion 105. In this embodiment, the fin and the protrusion 105 are an integral structure.

[0078] In this embodiment, the material of the fin is the same as that of the substrate 100, which is silicon. For a detailed description of the fin material, please refer to the corresponding description in the foregoing embodiments, and it will not be repeated here.

[0079] In other embodiments, when the first and second devices are fully enclosed gate transistors or fork-type gate transistors, the channel structure can also be a channel structure layer, with the channel structure layer and the protrusions spaced apart. The channel structure layer includes one or more channel layers spaced apart sequentially. Specifically, in the step of providing the substrate, a sacrificial layer is also formed between the channel layer and the protrusions, or between adjacent channel layers. The sacrificial layer is used to support the channel layer, so as to provide a process basis for the subsequent implementation of the spaced-out arrangement of the channel layers. The sacrificial layer is also used to occupy space for the subsequent formation of the gate structure.

[0080] In this embodiment, both the channel structure 110 and the protrusion 105 extend laterally, and the multiple protrusions 105 or the multiple channel structures 110 are arranged sequentially at intervals along the longitudinal direction. The lateral direction is perpendicular to the longitudinal direction.

[0081] The isolation layer 115 is used to isolate adjacent protrusions 105, and also to isolate the substrate 100 from the subsequent gate structure. The isolation layer 115 includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the top surface of the isolation layer 115 is flush with the top surface of the protrusion 105.

[0082] The buried power rail 120 is used to provide power to different components of the chip. In this embodiment, the buried power rail 120 is located in the substrate 100 of the power rail region 100b. The buried power rail 120 is a buried power rail (BPR), which is beneficial for freeing up wiring resources for back-end interconnects and for reducing the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rail uses pitch miniaturization to increase back-end (BEOL) resistance, which is also beneficial for providing a lower resistance local current distribution.

[0083] The buried power rail 120 is a long strip structure. Both the buried power rail 120 and the trench structure 110 extend laterally, and there is a gap between the buried power rail 120 and the trench structure 110.

[0084] The material used to bury the power rail 120 is a conductive material. In this embodiment, the material used to bury the power rail 120 is a metallic material, such as one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the buried power rail 120 is low, which is beneficial for improving RC delay and increasing the processing speed of the chip.

[0085] In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115.

[0086] The top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, thereby exposing the top surface of the isolation layer 115. The top surface of the buried power rail 120 is relatively high, which makes it easier for the source-drain interconnect layer to contact the top surface of the buried power rail 120 in the subsequent steps of forming the source-drain interconnect layer that contacts the source-drain doped region and the top surface of the buried power rail 120. This helps to reduce the process difficulty of forming the source-drain interconnect layer and improve process compatibility and process stability.

[0087] In other embodiments, the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer, and a covering dielectric layer located on the top surface of the buried power rail is also formed in the isolation layer.

[0088] A covering dielectric layer located in the isolation layer is also formed on the top surface of the buried power rail, thereby making the buried power rail and subsequent process compatible with existing process technologies.

[0089] The overlay dielectric layer is used to isolate buried power rails from the gate structure, or to isolate buried power rails from other conductive structures located on the isolation layer. The overlay dielectric layer is made of a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the overlay dielectric layer is made of the same material as the isolation layer, which improves process compatibility.

[0090] Specifically, the top surface of the covering dielectric layer is flush with the top surface of the isolation layer so that the top surface of the isolation layer is a flat surface, which is beneficial to the formation of the subsequent gate structure.

[0091] The top surface of the buried power rail 120 is lower than or flush with the top surface of the isolation layer 115. Along the direction perpendicular to the surface of the substrate 100, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 should not be too large. Otherwise, if the covering dielectric layer on the top surface of the buried power rail 120 is too thick, the source-drain interconnect layer will need to penetrate the covering dielectric layer to contact the top surface of the buried power rail 120 in the subsequent step of forming the source-drain interconnect layer. An excessively thick covering dielectric layer on the top surface of the buried power rail 120 will result in an excessively deep source-drain interconnect layer, which will increase the difficulty of forming the source-drain interconnect layer and also reduce process compatibility and increase process risks. Therefore, in this embodiment, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 along the direction perpendicular to the surface of the substrate 100 is 0 nm to 15 nm.

[0092] When the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0nm, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115.

[0093] It should be noted that, in this embodiment, an insulating layer 125 is also formed between the buried power rail 120 and the substrate 100, and between the buried power rail 120 and the isolation layer 115. The insulating layer 125 is used to achieve electrical isolation between the buried power rail 120 and the substrate 100. The material of the insulating layer 125 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0094] The steps for providing the substrate 100 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0095] like Figure 4 As shown, a substrate 100, a protrusion 105 discretely disposed on the substrate 100 in device region 100a, and a channel structure 110 located on the protrusion 105 are provided; an isolation material layer 135 is formed on the substrate 100 surrounding the protrusion 105 and covering the channel structure 110. The isolation material layer 135 is used for subsequent formation of the isolation layer, and also plays a role in protecting the channel structure 110 and the protrusion 105 during the formation of the buried power rail.

[0096] As an example, the use of flowable chemical vapor deposition (FCVD) to form the isolation membrane is beneficial to improving the gap filling ability of the isolation membrane, thereby reducing the probability of defects such as voids in the isolation membrane; the use of chemical mechanical planarization to planarize the isolation membrane is beneficial to improving the flatness of the top surface of the isolation material layer 135.

[0097] like Figure 5As shown, a trench 145 is formed, penetrating the power track region 100b through an isolation material layer 135 and a partially thick substrate 100. The trench 145 defines the formation location of the buried power track and provides formation space for the buried power track. Specifically, an anisotropic etching process is used to sequentially etch the isolation material layer 135 and the partially thick substrate 100 of the power track region 100b to form the trench 145. The anisotropic etching process has the characteristics of anisotropic etching, which is beneficial for improving the control of the etching profile and the dimensional accuracy of the trench.

[0098] like Figure 6 As shown, a buried power rail 120 is formed in the trench 145. The top surface of the buried power rail 120 is higher than the top surface of the substrate 100 and lower than or flush with the top surface of the protrusion 105.

[0099] Specifically, the step of forming the buried power rail 120 in the trench 145 includes: forming a power rail material layer (not shown) in the trench 145, the power rail material layer also being located on top of the insulating material layer 135; and removing a portion of the thickness of the power rail material layer.

[0100] In this embodiment, the forming method further includes forming an insulating film 101 on the bottom and sidewalls of the trench 145 and on the top surface of the isolation material layer 135 before forming the power rail material layer in the trench 145. The insulating film 101 is used for subsequent formation of an insulating layer to achieve electrical isolation between the buried power rail and the substrate 100.

[0101] like Figure 7 As shown, a dielectric material layer 103 is formed on the buried power rail 120 to fill the trench 145.

[0102] The dielectric material layer 103 serves to protect the buried power rail 120 during the subsequent etching of the isolation material layer 135. In a specific implementation, when the top surface of the isolation layer formed by the subsequent etching of the isolation material layer 135 is higher than the top surface of the buried power rail 120, the dielectric material layer 103 is also used to form a covering dielectric layer.

[0103] As an example, a dielectric material layer 103 is formed using a flow chemical vapor deposition (FCVD) process.

[0104] like Figure 8 As shown, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the protrusion 105. The dielectric material layer 103 and the insulating material layer 135 that are higher than the top surface of the buried power rail 120 are removed, and the remaining insulating material layer 135 is used as the insulating layer 115. The top surface of the insulating layer 115 is flush with the top surfaces of the buried power rail 120 and the protrusion 105.

[0105] In other embodiments, when the top surface of the buried power rail is lower than the top surface of the protrusion, a portion of the dielectric material layer and the insulating material layer are removed. The remaining insulating material layer serves as an insulating layer, and the remaining dielectric material layer on the top surface of the buried power rail serves as a covering dielectric layer. Accordingly, the top surface of the insulating layer is higher than the top surface of the buried power rail. Specifically, the top surface of the covering dielectric layer is flush with the top surface of the insulating layer.

[0106] refer to Figure 9 and Figure 10 , Figure 9 This is a top view. Figure 10 for Figure 9 A cross-sectional view along the a-a1 direction shows a gate structure 130 located on the isolation layer 115 and spanning the channel structure 110, source / drain doped regions 140 located on both sides of the gate structure 130 in the channel structure 110, and an interlayer dielectric layer 150 located on the isolation layer 115 on the side of the gate structure 130 and covering the source / drain doped regions 140.

[0107] When the device is in operation, the gate structure 130 is used to control the opening or closing of the conductive channel.

[0108] Specifically, in this embodiment, the gate structure 130 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure spans the channel structure layer and surrounds the channel layer.

[0109] The extension direction of the gate structure 130 is perpendicular to the extension direction of the channel structure 110, that is, the gate structure 130 extends longitudinally. In this embodiment, there are multiple gate structures 130, which are arranged at lateral intervals.

[0110] In this embodiment, the gate structure 130 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0111] The gate structure 130 is made of a conductive material. The material of the gate structure 130 includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. Specifically, the gate structure 130 may include a work function layer (not shown) and a metal electrode layer located on the work function layer; alternatively, the gate structure 130 may be a work function layer or a metal electrode layer.

[0112] It should be noted that, in this embodiment, a gate dielectric layer (not shown) is also formed between the gate structure 130 and the channel structure 110. In this embodiment, the gate dielectric layer is also located between the gate structure 130 and the top surface of the isolation layer 115. The gate dielectric layer is used to achieve insulation between the gate structure 130 and the conductive channel.

[0113] Specifically, in this embodiment, when the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, the gate dielectric layer is also located between the gate structure 130 and the buried power rail 120 to achieve insulation between the gate structure 130 and the buried power rail 120. In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a cover dielectric layer is also formed on the top surface of the buried power rail, the gate dielectric layer is also located between the gate structure and the cover dielectric layer.

[0114] The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

[0115] It should be noted that sidewalls (not shown) can also be formed on the sidewalls of the gate structure 130 to protect the sidewalls of the gate structure 130 and to define the formation location of the source and drain doped regions 140.

[0116] The source / drain doped region 140 serves as the source or drain of the field-effect transistor. When the field-effect transistor is operating, the source / drain doped region 140 provides a carrier source. In this embodiment, the source / drain doped region 140 is located within the fins on both sides of the gate structure 130. For a detailed description of the material of the source / drain doped region 140, please refer to the corresponding description in the foregoing embodiments; it will not be repeated here.

[0117] The interlayer dielectric layer 150 is used to isolate adjacent devices and also to electrically isolate adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation layer 115 on the side of the gate structure 130.

[0118] In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, and the interlayer dielectric layer 150 also covers the top surface of the buried power rail 120. In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top of the buried power rail, the interlayer dielectric layer also covers the covering dielectric layer.

[0119] The interlayer dielectric layer 150 is made of an insulating material. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. It should be noted that, for ease of illustration and explanation, only the insulating layer 115 and the interlayer dielectric layer 150 are shown in the cross-sectional view.

[0120] As one embodiment, the steps of forming the gate structure 130, the source / drain doped regions 140, and the interlayer dielectric layer 150 may include: forming a dummy gate structure (not shown) across the channel structure 110 in the isolation layer 115; forming sidewalls on the sidewalls of the dummy gate structure; forming source / drain doped regions 140 in the channel structure 110 on both sides of the dummy gate structure and the sidewalls; forming the interlayer dielectric layer 150 on the isolation layer 115 exposed by the dummy gate structure; removing the dummy gate structure to form a gate opening (not shown); and forming the gate structure 130 in the gate opening.

[0121] The dummy gate structure occupies space for forming the gate structure. Specifically, the dummy gate structure may include a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. As an example, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride; the material of the dummy gate layer is polycrystalline silicon or amorphous silicon.

[0122] The gate opening provides space for forming the gate structure. In this embodiment, a fin-like channel structure is used as an example. In other embodiments, when the channel structure is a channel structure layer suspended at a distance from the protrusion, after forming the gate opening, the gate opening exposes the channel structure layer and the sacrificial layer; correspondingly, after forming the gate opening, the forming method further includes: removing the sacrificial layer to form a through-slot. The through-slot and the gate opening are connected, and the through-slot and the gate opening together provide space for forming the gate structure.

[0123] refer to Figures 11 to 14 A source-drain interconnect layer 180 is formed that penetrates the interlayer dielectric layer 150 on the top of the source-drain doped region 140 and the buried power rail 120. The source-drain interconnect layer 180 is in contact with the source-drain doped region 140, and the bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120.

[0124] The source / drain interconnect layer 180 is in contact with the source / drain doped region 140 to enable electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0125] The bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120, so that the source-drain interconnect layer 180 and the buried power rail 120 can be electrically connected, and then when the device is working, the source-drain doped region 140 can be powered through the buried power rail 120.

[0126] Furthermore, the bottom of the source-drain interconnect layer 180 contacts the top surface of the buried power rail 120, so that the source-drain interconnect layer 180 and the buried power rail 120 do not need to be electrically connected through a contact plug (Via). This not only shortens the current transmission path between the source-drain interconnect layer 180 and the buried power rail 120, but also prevents the contact plug from having excessive resistance, which would have an adverse effect on the electrical connection performance between the source-drain interconnect layer and the buried power rail. This optimizes the electrical connection performance between the source-drain interconnect layer 180 and the buried power rail 120 and improves power supply efficiency.

[0127] Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115. Thus, when the source-drain interconnect layer 180 penetrates the source-drain doped region 140 and the interlayer dielectric layer 150 on top of the buried power rail 120, the source-drain interconnect layer 180 can contact the source-drain doped region 140 and the bottom surface of the source-drain interconnect layer 180 can contact the buried power rail 120. This helps to reduce the difficulty of making direct contact between the source-drain interconnect layer 180 and the buried power rail 120.

[0128] In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is also formed on the top surface of the buried power rail, the source-drain interconnect layer penetrates the interlayer dielectric layer on the top of the source-drain doped region, as well as the covering dielectric layer and interlayer dielectric layer on the top of the buried power rail, which can also achieve the purpose of the source-drain interconnect layer contacting the source-drain doped region and the bottom of the source-drain interconnect layer contacting the top surface of the buried power rail.

[0129] In this embodiment, the source-drain interconnect layer 180 extends longitudinally, and the extension direction of the source-drain interconnect layer 180 is perpendicular to the extension direction of the buried power rail 120.

[0130] In this embodiment, the bottom of the source-drain interconnect layer 180 is flush with the top surface of the buried power rail 120, which achieves the purpose of the bottom of the source-drain interconnect layer 180 contacting the top surface of the buried power rail 120, and the bottom surface of the source-drain interconnect layer 180 is not too low, which is beneficial to improving process compatibility and process stability.

[0131] In other embodiments, the bottom of the source-drain interconnect layer may be lower than the top surface of the buried power rail and higher than the top surface of the substrate. This allows the bottom of the source-drain interconnect layer to contact the top surface of the buried power rail. Furthermore, it helps ensure that the bottom of each source-drain interconnect layer can contact the top surface of the buried power rail, reducing the probability that some source-drain interconnect layers will not be able to contact the buried power rail due to inconsistent bottom heights. This, in turn, ensures the electrical connection performance between the source-drain interconnect layer and the buried power supply. Specifically, the source-drain interconnect layer also extends through a partial thickness of the isolation layer.

[0132] The source-drain interconnect layer 180 is made of a conductive material, including one or more of W, Co, Cu, Ru, and Ni. The low resistivity of the material helps reduce the resistance of the source-drain interconnect layer 180, thereby reducing RC delay and improving the performance of the semiconductor structure.

[0133] The specific steps for forming the source-drain interconnect layer 180 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0134] like Figure 11 As shown, a source / drain interconnect trench 160 is formed, penetrating the interlayer dielectric layer 150 on top of the source / drain doped region 140 and the buried power rail 120. The source / drain interconnect trench 160 exposes the top surface of the buried power rail 120 and the source / drain doped region 140. The source / drain interconnect trench 160 provides space for the formation of the source / drain interconnect layer. The bottom of the source / drain interconnect trench 160 exposes the top surface of the buried power rail 120 and the source / drain doped region 140, so that the subsequent source / drain interconnect layer can contact the top surface of the buried power rail 120 and the source / drain doped region 140.

[0135] In this embodiment, before forming the source / drain interconnect trench 160, a hard mask layer 155 is formed on the interlayer dielectric layer 150. The hard mask layer 155 has mask openings (not shown) located above the source / drain doped regions 140 and the buried power rails 120. The hard mask layer 155 serves as an etching mask for forming the source / drain interconnect trench 160. The mask openings define the shape and location of the source / drain interconnect trench.

[0136] The hard mask layer 155 is made of a material that has etching selectivity with the material of the interlayer dielectric layer 150, such as titanium nitride, titanium oxide, or silicon nitride. As an example, the material of the hard mask layer 155 is titanium nitride.

[0137] Specifically, the step of forming the source-drain interconnect trench 160 includes: using a hard mask layer 155 as a mask, performing a main etching on the interlayer dielectric layer 150 on top of the source-drain doped region 140 and the buried power rail 120 to form an initial interconnect trench (not shown), exposing the source-drain doped region 140; and performing an over etch on the bottom of the initial interconnect trench to expose the top of the buried power rail 120, thus forming the source-drain interconnect trench 160.

[0138] By over-etching the bottom of the initial interconnect trench during the formation of the source-drain interconnect trench 160, the top surface of the buried power rail 120 can be exposed. This allows the existing process for forming the source-drain interconnect trench 160 and the source-drain interconnect layer to be utilized without introducing additional process steps. This minimizes modifications to the existing process, improves process compatibility and stability, and also helps save costs.

[0139] In this embodiment, over-etching the bottom of the initial interconnect trench refers to over-etching the dielectric material at the bottom of the initial interconnect trench.

[0140] Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, and the dielectric material on the top of the buried power rail 120 includes an interlayer dielectric layer 150. Therefore, the dielectric material at the bottom of the initial interconnect trench includes an interlayer dielectric layer 150. The interlayer dielectric layer 150 at the bottom of the initial interconnect trench is over-etched to expose the top surface of the buried power rail 120.

[0141] In other embodiments, the top surface of the buried power rail is lower than the top surface of the isolation layer, and a cover dielectric layer is also formed on top of the buried power rail. Correspondingly, the dielectric material at the bottom of the initial interconnect trench includes an interlayer dielectric layer and a cover dielectric layer. The interlayer dielectric layer and cover dielectric layer at the bottom of the initial interconnect trench are over-etched to expose the top surface of the buried power rail. The dielectric material at the bottom of the initial interconnect trench also includes an isolation layer. During the over-etching process of the interlayer dielectric layer and cover dielectric layer at the bottom of the initial interconnect trench, the isolation layer at the bottom of the initial interconnect trench is also etched. Correspondingly, the subsequent source / drain interconnect layers are also located within a partial thickness of the isolation layer.

[0142] It should be noted that during the over-etching process of the bottom of the initial interconnect trench, part of the bottom of the initial interconnect trench is the source / drain doped region 140. Correspondingly, the bottom of the initial interconnect trench exposed by the source / drain doped region 140 is over-etched. Therefore, after the source / drain interconnect trench 160 is formed, the bottom of the source / drain interconnect trench 160 exposed by the source / drain doped region 140 is lower than the bottom of the source / drain interconnect trench 160 at the location of the source / drain doped region 140.

[0143] In an optional embodiment, a dividing layer 190 protruding from the bottom of the source-drain interconnect trench 160 is also formed in the source-drain interconnect trench 160. The dividing layer 190 longitudinally divides the source-drain interconnect trench 160 located on both sides of the buried power rail 120. By forming the dividing layer 190, the source-drain interconnect layer can be disconnected at locations where it is not needed, and the source-drain interconnect layer that does not need to be electrically connected to the buried power rail 120 can be isolated from the buried power rail 120, thereby increasing the design freedom of the source-drain interconnect layer.

[0144] Specifically, in this embodiment, during the step of forming the source-drain interconnect trench 160, a portion of the width of the interlayer dielectric layer 150 located longitudinally between adjacent device regions 100a is retained as a partition layer 190. Accordingly, the material of the partition layer 190 is the same as the material of the interlayer dielectric layer 150. In other embodiments, the material of the partition layer may be different from the material of the interlayer dielectric layer; the material of the partition layer may also be other dielectric materials with isolation functions.

[0145] In other embodiments, based on actual process requirements, a separation layer may not be formed in the source-drain interconnect trench, and the source-drain interconnect trenches of adjacent device regions along the longitudinal direction may be connected.

[0146] It should be noted that, as Figure 12 As shown, in this embodiment, after forming the source-drain interconnect trench 160, the forming method further includes forming a silicide layer 170 on the surface of the exposed source-drain doped region 140 of the source-drain interconnect trench 160. The silicide layer 170 is used to reduce the contact resistance between the source-drain interconnect layer and the source-drain doped region 140, and during device operation, current flows through the source-drain interconnect layer and across the surface of the silicide layer 170. In this embodiment, the material of the silicide layer 170 can be a nickel-silicon compound, a cobalt-silicon compound, or a titanium-silicon compound.

[0147] It should also be noted that, in this embodiment, after forming the source-drain interconnect trench 160 and before forming the silicide layer 170, the formation method further includes: removing the hard mask layer 155.

[0148] like Figure 13 and Figure 14 As shown, the source-drain interconnect layer 180 is filled in the source-drain interconnect trench 160.

[0149] Specifically, conductive material (not shown) is filled in the source-drain interconnect trench 160, and the conductive material is also formed on the interlayer dielectric layer 150; a planarization process is used to remove the conductive material on the interlayer dielectric layer 150, and the remaining conductive material in the source-drain interconnect trench 160 is used as the source-drain interconnect layer 180.

[0150] In this embodiment, the process for forming the conductive material may include one or more of physical vapor deposition, chemical vapor deposition, and electrochemical plating. In this embodiment, the planarization process may be chemical mechanical planarization (CMP). CMP is a type of global planarization process that improves the removal efficiency of the conductive material while enhancing the top surface flatness and high consistency between the source / drain interconnect layer 180 and the interlayer dielectric layer 150.

[0151] In an alternative embodiment, when a partition layer 190 protruding from the bottom of the source-drain interconnect trench 160 is also formed in the source-drain interconnect trench 160, the source-drain interconnect layers 180 of adjacent device regions 100a are isolated by the partition layer 190 along the longitudinal direction.

[0152] It should be noted that the above description uses the formation of a partition layer 190 during the formation of the source-drain interconnect trench 160 as an example. In other embodiments, a partition layer can be formed after the formation of the source-drain interconnect layer, penetrating a portion of the source-drain interconnect layer located between adjacent device regions, with the partition layer longitudinally dividing the source-drain interconnect layer located in the adjacent device regions.

[0153] As an example, the source-drain interconnect layer 180 located on either side of the partition layer 190 is in contact with the buried power rail 120. It should also be noted that, for ease of illustration and explanation, the partition layer 190 is only shown in the cross-sectional view.

[0154] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple discrete device regions and a power rail region located between the device regions; The protrusions are distributed on the substrate of the device region; A channel structure is located on the protrusion; An isolation layer is located on the substrate and surrounds the protrusion, exposing the channel structure; The buried power rail penetrates the isolation layer and part of the thickness substrate in the power rail area, and the buried power rail is arranged parallel to the protrusion; the top surface of the buried power rail is flush with the top surface of the isolation layer. A gate structure is located on the isolation layer and spans the channel structure; The source and drain doped regions are located in the channel structures on both sides of the gate structure; An interlayer dielectric layer is located on the isolation layer on the side of the gate structure and covers the source / drain doped regions; A source-drain interconnect layer extends through the interlayer dielectric layer on top of the source-drain doped region and the buried power rail. The source-drain interconnect layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnect layer is in contact with the top surface of the buried power rail. A gate dielectric layer is located between the gate structure and the channel structure, and between the gate structure and the isolation layer; the gate dielectric layer is also located between the buried power rail and the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer; The semiconductor structure further includes: a covering dielectric layer located in the isolation layer and on the top surface of the buried power rail; The source-drain interconnect layer extends through the interlayer dielectric layer on top of the source-drain doped region, as well as the overlay dielectric layer and the interlayer dielectric layer on top of the buried power rail.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The bottom of the source-drain interconnect layer is flush with the top surface of the buried power rail; or, the bottom of the source-drain interconnect layer is lower than the top surface of the buried power rail and higher than the top surface of the substrate.

4. The semiconductor structure as described in claim 1, characterized in that, The buried power rail and trench structure both extend laterally, and the direction perpendicular to the lateral direction is longitudinal; the source-drain interconnect layer extends along the longitudinal direction; the semiconductor structure further includes: a dividing layer that penetrates a portion of the source-drain interconnect layer located in the power rail region, the dividing layer dividing the source-drain interconnect layer located in adjacent device regions along the longitudinal direction.

5. The semiconductor structure as described in claim 4, characterized in that, The bottom surface of the source-drain interconnect layer located on either side of the segmentation layer is in contact with the top surface of the buried power rail; or, the bottom surfaces of the source-drain interconnect layers located on both sides of the segmentation layer are in contact with the top surface of the buried power rail.

6. The semiconductor structure as described in claim 1, characterized in that, The top surface of the buried power rail is lower than or flush with the top surface of the isolation layer; the distance between the top surface of the buried power rail and the top surface of the isolation layer is 0 nm to 15 nm along a direction perpendicular to the substrate surface.

7. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; the protrusion and channel structure material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; the buried power rail material includes one or more of the following: Co, W, Ni, and Ru.

8. The semiconductor structure as described in claim 2, characterized in that, The top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer; the gate dielectric layer is also located between the cover dielectric layer and the gate structure.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the gate structure includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni; the material of the source-drain interconnect layer includes one or more of W, Co, Cu, Ru, and Ni.

11. The semiconductor structure as claimed in claim 1, characterized in that, The channel structure is a fin; the gate structure spans the fin and covers part of the top and part of the sidewalls of the fin; or, the channel structure is a channel structure layer, with the channel structure layer and the protrusion spaced apart, the channel structure layer including one or more channel layers spaced apart in sequence; the gate structure spans the channel structure layer and surrounds the channel layer.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, comprising a plurality of discrete device regions and a power rail region located between the device regions. Discrete protrusions are formed on the substrate of the device regions, and channel structures are formed on the protrusions. An isolation layer is formed on the substrate surrounding the protrusions, and the isolation layer exposes the channel structures. Buried power rails are formed in the isolation layer and a portion of the substrate in the power rail region, and the buried power rails are disposed parallel to and spaced apart from the protrusions. In the step of providing the substrate, the top surface of the buried power rails is flush with the top surface of the isolation layer. A gate structure is formed on the isolation layer and spans the channel structure, source and drain doped regions are formed in the channel structure on both sides of the gate structure, and an interlayer dielectric layer is formed on the isolation layer on the side of the gate structure and covers the source and drain doped regions; wherein, a gate dielectric layer is also formed between the gate structure and the channel structure, and the gate dielectric layer is also located between the gate structure and the top surface of the isolation layer. When the top surface of the buried power rail is flush with the top surface of the isolation layer, the gate dielectric layer is also located between the gate structure and the buried power rail. A source-drain interconnect layer is formed that extends through the interlayer dielectric layer on top of the source-drain doped region and the buried power rail. The source-drain interconnect layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnect layer is in contact with the top surface of the buried power rail.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Also includes: The top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer. A covering dielectric layer located on the top surface of the buried power rail is also formed in the isolation layer. In the step of forming the source-drain interconnect layer, the source-drain interconnect layer penetrates the interlayer dielectric layer on the top of the source-drain doped region, as well as the covering dielectric layer and the interlayer dielectric layer on the top of the buried power rail.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the source-drain interconnect layer includes: forming a source-drain interconnect trench that extends through the source-drain doped region and the top of the buried power rail on the interlayer dielectric layer, the source-drain interconnect trench exposing the top surface of the buried power rail and the source-drain doped region; and filling the source-drain interconnect layer in the source-drain interconnect trench.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The steps of forming the source-drain interconnect trench include: performing main etching on the interlayer dielectric layer on the top of the source-drain doped region and the buried power rail to form an initial interconnect trench, exposing the source-drain doped region; and performing over-etching on the bottom of the initial interconnect trench to expose the top of the buried power rail, thereby forming the source-drain interconnect trench.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, Both the buried power rail and the trench structure extend laterally, and the direction perpendicular to the lateral direction is longitudinal. In the step of forming the source-drain interconnection trench, the source-drain interconnection trench extends along the longitudinal direction, and a dividing layer protruding from the bottom of the source-drain interconnection trench is formed in the source-drain interconnection trench. The dividing layer divides the source-drain interconnection trench located on both sides of the buried power rail along the longitudinal direction. Along the longitudinal direction, the source-drain interconnect layers of adjacent device regions are isolated by the partition layer.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the semiconductor structure further includes: after forming the source-drain interconnect layer, forming a segmentation layer that penetrates a portion of the source-drain interconnect layer located between adjacent device regions, the segmentation layer longitudinally segmenting the source-drain interconnect layer located adjacent to the device regions.

18. The method for forming a semiconductor structure as described in claim 16 or 17, characterized in that, The source-drain interconnect layer located on either side of the segmentation layer is in contact with the buried power rail.

19. The method for forming a semiconductor structure as described in claim 12, characterized in that, The bottom of the source-drain interconnect layer is flush with the top surface of the buried power rail; or, the bottom of the source-drain interconnect layer is lower than the top surface of the buried power rail and higher than the top surface of the substrate.

20. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of providing a substrate includes: providing a substrate, a protrusion discrete on the device region substrate, and a channel structure located on the protrusion; An isolation material layer is formed on the substrate, surrounding the protrusion and covering the channel structure; A trench is formed that extends through the isolation material layer and a portion of the substrate thickness in the power rail region; The buried power rail is formed in the trench, and the top surface of the buried power rail is higher than the top surface of the substrate and lower than or flush with the top surface of the protrusion. A dielectric material layer is formed on the buried power rail to fill the trench; When the top surface of the buried power rail is lower than the top surface of the protrusion, a portion of the dielectric material layer and the insulating material layer are removed, and the remaining insulating material layer is used as an insulating layer. The remaining dielectric material layer on the top surface of the buried power rail is used as a covering dielectric layer. When the top surface of the buried power rail is flush with the top surface of the protrusion, the dielectric material layer and the insulating material layer above the top surface of the buried power rail are removed, and the remaining insulating material layer is used as an insulating layer.

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