Timing path screening method and apparatus

Abstract

The application provides a timing path screening method and device, relates to the technical field of integrated circuits, and comprises the following steps: determining timing paths related to timing logic elements corresponding to each clock port in a first list; calculating clock skews corresponding to each timing path, and determining whether each timing path has a timing violation risk according to the clock skews corresponding to each timing path and a preset clock skew threshold. The application can screen out timing paths having a timing violation risk caused by clock skews, thereby being beneficial to improving the yield of a chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a timing path screening method and device. Background Technology

[0002] In the chip design process, static timing analysis (STA) tools are usually used to check whether the entire chip meets timing requirements in various application scenarios. If there are timing violations in the chip, it may lead to low yield or even failure of the produced chip.

[0003] Clock skew (CS) refers to the difference between different phases of sub-clocks generated by the same clock, which can affect circuit timing to some extent. In practical applications, existing STA tools struggle to calculate the precise value of timing paths with significant clock skew, making it impossible to identify timing paths at risk of timing violations due to clock skew. This prevents engineers from compensating for the relevant timing paths, ultimately impacting chip yield. Summary of the Invention

[0004] This application provides a timing path screening method and device, which can accurately screen out timing paths that have a risk of timing violations due to clock offset, thereby improving chip yield.

[0005] In a first aspect, embodiments of this application provide a time-series path screening method, the method comprising:

[0006] Determine the timing path associated with the timing logic element corresponding to each clock port in the first list;

[0007] Calculate the clock offset corresponding to each of the timing paths;

[0008] Based on the clock offset corresponding to each timing path and the preset clock offset threshold, it is determined whether there is a timing violation risk in each timing path.

[0009] In some embodiments, it also includes:

[0010] Obtain the clock ports corresponding to each clock cycle in the chip under test, and add each clock port to the first list.

[0011] In some embodiments, it also includes:

[0012] The STA tool is used to obtain the clock delay of each clock port corresponding to each clock in the chip under test, and the clock ports whose clock delay is not within the clock offset filtering range corresponding to each clock are added to the first list.

[0013] In some embodiments, it also includes:

[0014] Calculate the average clock delay of each clock port corresponding to each clock, and determine the clock offset filtering range corresponding to each clock based on the calculated average and the preset clock offset threshold.

[0015] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port in the first list includes:

[0016] Find the non-clock input ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-in of each non-clock input port.

[0017] And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-out of each non-clock output port.

[0018] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port in the first list based on the fan-in of each of the non-clock input ports includes:

[0019] Determine the timing logic element The j-th non-clock input port Minimum hold time margin

[0020] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths;

[0021] Among them, sequential logic elements For the i-th clock port of the x-th clock in the first list The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0022] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port in the first list based on the fan-out of each of the non-clock output ports includes:

[0023] Determine the timing logic element The j-th non-clock output port Minimum hold time margin

[0024] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths;

[0025] Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0026] In some embodiments, calculating the clock offset corresponding to each timing path includes:

[0027] According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the clock delay of the x-th clock.

[0028] Determine the input port The k-th fan-in Clock delay relative to the x-th clock And determine the output port The kth fan-out Clock delay relative to the x-th clock

[0029] According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where x, i, j, and k are all positive integers.

[0030] In some embodiments, determining whether each timing path has a timing violation risk based on the clock offset corresponding to each timing path and a preset clock offset threshold includes:

[0031] When the fan-in When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fan-in is determined. The corresponding timing path carries a risk of timing violation.

[0032] And / or, when the fan-out When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fanout is determined. The corresponding timing path has a risk of timing violation.

[0033] In some embodiments, it also includes:

[0034] Add the timing path that has the risk of timing violation to the second list;

[0035] Use the STA tool to determine the actual hold time margin for each timing path in the second list;

[0036] Based on the clock offset corresponding to each timing path in the second list and the actual hold time margin, determine whether each timing path in the second list meets the preset timing conditions.

[0037] In some embodiments, determining whether each timing path in the second list meets preset timing conditions based on the clock offset corresponding to each timing path in the second list and the actual hold time margin includes:

[0038] When there is a first timing path in the second list whose actual hold time margin is less than the preset margin threshold, the clock offset of the first timing path is compensated according to the preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the third list.

[0039] Based on the clock offset corresponding to each first timing path in the third list and the actual hold time margin, determine whether each first timing path in the third list meets the preset timing conditions.

[0040] In some embodiments, determining whether each first timing path in the third list meets preset timing conditions based on the clock offset corresponding to each first timing path in the third list and the actual hold time margin includes:

[0041] Determine the compensation delay value corresponding to each first timing path in the third list;

[0042] Based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters corresponding to each first timing path in the third list, calculate the target hold time margin corresponding to each first timing path in the third list.

[0043] When the target hold time margin is greater than zero, it is determined that the first timing path corresponding to the target hold time margin meets the preset timing conditions. When the target hold time margin is less than or equal to zero, it is determined that the first timing path corresponding to the target hold time margin does not meet the preset timing conditions.

[0044] Secondly, embodiments of this application provide a time-series path screening device, the device comprising:

[0045] The determination module is used to determine the timing path associated with the timing logic element corresponding to each clock port in the first list;

[0046] The calculation module is used to calculate the clock offset corresponding to each of the timing paths;

[0047] The judgment module is used to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the preset clock offset threshold.

[0048] Thirdly, embodiments of this application provide an electronic device, including: at least one processor and a memory;

[0049] The memory stores computer-executed instructions;

[0050] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the timing path screening method as provided in the first aspect.

[0051] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the timing path screening method provided in the first aspect.

[0052] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a computer, implements the timing path screening method provided in the first aspect.

[0053] The timing path screening method and device provided in this application can: determine the timing path related to the timing logic element corresponding to each clock port in the first list, and calculate the clock offset corresponding to each timing path. Based on the clock offset corresponding to each timing path and the preset clock offset threshold, it can determine whether there is a timing violation risk in each timing path. This can accurately screen out timing paths that have a timing violation risk due to clock offset, which is beneficial to improving the yield of the chip. Attached Figure Description

[0054] Figure 1 This is a schematic diagram illustrating the setup and hold times of sequential logic elements in the embodiments of this disclosure;

[0055] Figure 2 This is a schematic diagram of a timing path provided in an embodiment of this application;

[0056] Figure 3 This is a flowchart illustrating the steps of a clock offset screening method provided in an embodiment of this application;

[0057] Figure 4 This is a schematic diagram showing the distribution of all clock delays corresponding to the same clock in an embodiment of this application;

[0058] Figure 5 This is a schematic diagram of the program modules of a clock offset screening device provided in the embodiments of this application;

[0059] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, although the disclosure in this application is described with reference to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0061] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0062] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, to implement the embodiments in a sequence other than those given in the illustrations or descriptions of this application.

[0063] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0064] The term "module" as used in the embodiments of this application refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0065] The clock offset screening method provided in this application embodiment can be applied to various types of chips, such as advanced high-performance digital chips, high-performance central processing units (CPUs), high-performance graphics processing units (GPUs), high-performance artificial intelligence (AI) chips, high-performance baseband chips, etc., and is not limited in this application embodiment.

[0066] In the semiconductor technology field, in the design flow of Application-Specific Integrated Circuits (ASICs) based on standard cell libraries, chip designers typically use hardware description languages ​​to design chips, that is, to model the chip functions, and then use automated design software to synthesize the design code into standard cell circuits. Then, through physical back-end design, the standard cell circuits are converted into graphic data stream (GDS) layouts that can be manufactured under the corresponding process technology, and finally delivered to the foundry to produce the chips.

[0067] In ASIC design based on standard cell libraries, foundries typically provide a Process Design Kit (PDK) in advance, which includes the design of some sequential logic elements and timing characteristic parameters (such as setup time or hold time).

[0068] Optionally, the aforementioned sequential logic elements can be latches, flip-flops (FF), etc.

[0069] A latch is a type of storage unit circuit that is sensitive to pulse levels. It can change its state under the influence of a specific input pulse level. Latching is the process of temporarily storing a signal to maintain a certain level state. In digital circuits, it can record binary digital signals "0" and "1".

[0070] A flip-flop, also called a bistable gate, is a storage component with two stable states. It can record binary digital signals "1" and "0", and its output is determined by the data input at the time specified by the input clock.

[0071] The setup time of a sequential logic element is the shortest time that the data input signal must remain stable before the effective edge of the clock; the hold time is the shortest time that the data input signal must remain stable after the effective edge of the clock.

[0072] Understandably, in an ideal situation, as long as valid data arrives at the same time as the clock's valid edge (before or simultaneously with the clock's valid edge), the sequential logic element can correctly acquire the data; and after (or simultaneously with) the clock's valid edge, even if the data changes, it will not affect the output of the sequential logic element.

[0073] However, in reality, it takes time for the switch to open at the clock edge, and it also takes time for the state of logic gates to change (such as capacitor charging and discharging). Therefore, data acquisition requires a certain amount of time, during which the data cannot change. That is, the data must be "prepared" in advance for a minimum amount of time before the clock edge arrives; this minimum amount of time is the setup time mentioned above. Furthermore, it also takes time for the switch to close at the clock edge. If the data changes during this period, the new data may be passed to the next stage, leading to errors. Therefore, the data must remain unchanged for a certain period of time; that is, after the clock edge arrives, the data must remain unchanged for a minimum amount of time; this minimum amount of time is the hold time mentioned above.

[0074] To better understand the embodiments of this application, please refer to... Figure 1 , Figure 1 This is a schematic diagram showing the setup and hold times of sequential logic elements in the embodiments of this application.

[0075] exist Figure 1 In the setup time, before the rising edge of the clock signal CK arrives, the data signal D must be "prepared" in advance for a minimum amount of time and cannot change. In addition, after the rising edge of the clock signal CK arrives, the data D must still remain unchanged for a minimum amount of time. This minimum amount of time is called the hold time.

[0076] During the chip design process, it is usually necessary to use the STA tool to check whether the entire chip meets the timing requirements in various application scenarios, based on the relevant constraints and guidance documents provided by the semiconductor foundry. That is, to check whether the timing slack is less than 0. If the timing slack is less than 0, it means that there is a timing path with timing violations in the chip.

[0077] To ensure that the manufactured chips meet their functional and performance requirements, it is necessary to ensure that there are no timing violations in the final STA check before the chip design documents are submitted to the semiconductor foundry. Otherwise, the manufactured chips may have a low yield or even fail.

[0078] Clock skew typically refers to the time difference between sub-clocks of different phases generated by the same clock, which affects circuit timing to some extent.

[0079] Although the STA tool has almost eliminated all possible timing paths with violations, the final tape-out results show that some of the failed chips still failed due to clock skew. That is, even though the clock skew has been included in the timing analysis, the STA tool cannot calculate the precise value for timing paths with large clock skew.

[0080] To address the aforementioned technical problems, this application provides a clock skew screening method that can accurately identify timing paths at risk of timing violations due to clock skew, thereby improving chip tape-out yield. For detailed implementation methods, please refer to the following embodiments.

[0081] Understandably, in chip design, the data transmission between the output port of a sequential logic element (such as a register) and the input port of the next sequential logic element via combinational logic elements can be considered a timing path. For a chip, it contains a large number of timing paths, and these timing paths can be used to calculate whether there are timing violations.

[0082] To better understand the embodiments of this application, please refer to... Figure 2 , Figure 2 This is a schematic diagram of a timing path provided in an embodiment of this application. Figure 2 In this type of timing path, the starting point, i.e., the sequential logic element 201 that provides data output, is called the launch cell. The transmission path of its control clock is called the launch clock, and the corresponding clock delay is denoted as T. LCorrespondingly, another sequential logic element 202 is called a capture cell, and the transmission path of its control clock is called the capture clock. The corresponding clock delay is denoted as T. C The data transmission path that passes through combinational logic element 203 is called the data path, and the corresponding data transmission delay is denoted as T. CO Additionally, the clock period of the input clock signal CLK is denoted as T.

[0083] As key parameters for timing checks, the calculation of setup and hold time margins for sequential logic elements determines whether timing path violations exist. The setup and hold time margins are denoted as T, respectively. Slack Setup and T Slack Hold Timing checks are only satisfied when both values ​​are greater than 0. The calculation formula is as follows:

[0084] T Slack Setup =TT CO -(T L -T C ) Formula 1-1

[0085] T Slack Hold =T CO +(T L -T C ) Formula 1-2

[0086] Let the clock offset be denoted as T. CS The calculation formula is as follows:

[0087] T CS =T L -T C Formula 1-3

[0088] Then, from formulas 1-1 and 1-2, we can directly derive:

[0089] T Slack Setup =TT CO -T CS Formula 1-4

[0090] T Slack Hold =T CO +T CS Formula 1-5

[0091] When T CS When ≥0, T Slack Setup With T Slack Hold There will be no timing violations due to clock skew; when T CS When <0, T Slack SetupThere are no timing violations due to clock skew, and T Slack Hold There may be a risk that the value will be less than 0.

[0092] To avoid because of T CS T is negative Slack Hold If a value less than 0 exists, the first step is to identify which timing paths pose a potential risk. In some embodiments, a boundary condition for the check is introduced: a clock skew limit (hereinafter referred to as L). CS Slack Limit (hereinafter referred to as L) S )) and quantization parameter (F P ), where L CS Used to specify which T CS Negative values ​​for L can be considered within a safe range. S Used to specify which T Slack Hold This can be considered a safe range, while F P As a risk coefficient, it is used in feedback T CS For T Slack Hold The values ​​of these three boundary conditions are set based on specific manufacturing processes, project data, and experience. Therefore, Formula 1-5 can be evolved into:

[0093] T Slack Hold Post =T CO +T CS -T P ·|T CS | Formula 1-6

[0094] For those in L CS With L S For timing paths other than those specified, their hold time margin will be recalculated using formulas 1-6, when T Slack Hold Post When the value is negative, it indicates that the timing path is at risk of timing violation.

[0095] Reference Figure 3 , Figure 3 This is a schematic flowchart illustrating the steps of a clock skew screening method provided in an embodiment of this application. In one feasible implementation, the clock skew screening method includes the following steps:

[0096] S301. Determine the timing path associated with the timing logic element corresponding to each clock port in the first list.

[0097] S302. Calculate the clock offset corresponding to each timing path.

[0098] S303. Based on the clock offset corresponding to each timing path and the preset clock offset threshold, determine whether there is a timing violation risk in each timing path.

[0099] In one feasible implementation, before determining the timing path associated with the timing logic element corresponding to each clock port in the first list, each clock port corresponding to each clock in the chip under test can be obtained and each clock port can be added to the first list mentioned above.

[0100] In another feasible implementation, before determining the timing path associated with the timing logic element corresponding to each clock port in the first list, the STA tool can be used to obtain the clock delay of each clock port corresponding to each clock in the chip under test, and clock ports whose clock delay is not within the clock offset filtering range corresponding to each clock can be added to the first list. This allows for preliminary screening of the timing logic elements in the chip under test. CS It may fall in L CS Out-of-range clock delays include:

[0101] 1.1 Obtain all clock delays corresponding to each clock cycle in the chip under test using the STA tool.

[0102] 1.2. Sum the clock delays associated with all clock ports for the same clock x and take the average value Tx. Based on this average value and the above L... CS The clock offset filtering range corresponding to clock x is determined to be [Tx-L]. CS / 2, Tx+L CS / 2].

[0103] Wherein, if clock x has a clock delay greater than Tx+L at some clock port. CS / 2, or less than Tx-L CS / 2, then add the clock port to the first list of to be observed and pass it to the next screening step; if the clock delay of any clock port is greater than or equal to Tx-L CS / 2 and less than or equal to Tx+L CS If the value is 2, then the clock port is ignored.

[0104] To better understand the embodiments of this application, please refer to... Figure 4 , Figure 4 This is a schematic diagram showing the distribution of all clock delays corresponding to the same clock in an embodiment of this application.

[0105] It is understandable that, under the same clock, the distribution of clock delays will follow a normal distribution. Therefore, the clock delay is located at the average value plus or minus L. CS Subsequent screening of clock ports outside of / 2 can effectively reduce the workload of screening.

[0106] In some implementations, step S301 includes:

[0107] Find the non-clock input ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-in of each non-clock input port; and / or find the non-clock output ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-out of each non-clock output port.

[0108] For example, sequential logic elements can be determined. The j-th non-clock input port Minimum hold time margin like If it is less than or equal to the preset margin threshold, then it depends on the input port. Fan-in determines the timing logic element. Related timing paths; among which, sequential logic elements For the i-th clock port of the x-th clock in the first list The sequential logic element it is located in For input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0109] Determine the timing logic element The j-th non-clock output port Minimum hold time margin like If it is less than or equal to the preset margin threshold, then it depends on the output port. Fan-out, determining the timing logic element Related timing paths; among which, For output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0110] In some implementations, steps S302 and S303 can be used to further filter the determined timing path, including:

[0111] 2.1 Determine the i-th clock port of the x-th clock in the first list. The sequential logic element is located and obtain All non-clock input ports.

[0112] in, correspond and It may contain other clock port pins.CK For example, the (i+n)th clock port

[0113] 2.2. Based on sequential logic elements The clock trigger type and clock port The clock delay information is used to determine the clock delay of the x-th clock cycle.

[0114] In some implementations, first determine What type of clock trigger is it? The clock trigger types include rising edge trigger, falling edge trigger, high level trigger, and low level trigger, which are obtained by acquiring... All clock delay information, and then according to Select valid information from the clock trigger types to obtain the corresponding clock delay information for clock x.

[0115] 2.3 Determine the sequential logic elements The j-th non-clock input port Minimum hold time margin

[0116] In some implementations, the input port is obtained. The smaller of the rising-edge triggered hold time margin and the falling-edge triggered hold time margin is taken as its minimum hold time margin.

[0117] In some implementations, if Greater than L S If so, skip that input port. No further inspection will be conducted.

[0118] 2.4, Regarding input port Obtain all its fan-in values ​​and calculate the k-th fan-in value. Clock delay information relative to clock x The method is the same as the steps in 2.2.

[0119] 2.5 Calculate the fan-in The corresponding T CS for if It is a negative number and its absolute value is greater than L. CS Then determine the corresponding timing path. There is a risk of timing violation; otherwise, the check for this path will be skipped.

[0120] In some embodiments, when determining the timing path When there is a risk of timing violation, the timing path can also be... Added to a second list for further observation.

[0121] Among them, fan-in and As timing paths respectively The starting point and the ending point.

[0122] Similarly, determine the output port. The kth fan-out Clock delay relative to the x-th clock cycle And calculate the fan-out The corresponding T CS for if It is a negative number and its absolute value is greater than L. CS Then determine the corresponding timing path. If there is a risk of timing violation, the check for that path will be skipped.

[0123] In some embodiments, when determining the timing path When there is a risk of timing violation, the timing path can also be... Added to the second list above for further observation.

[0124] The timing path screening method provided in this application determines the timing path related to the timing logic element corresponding to each clock port in the first list and calculates the clock offset corresponding to each timing path. Based on the clock offset corresponding to each timing path and the preset clock offset threshold, it can determine whether there is a timing violation risk in each timing path. This can accurately screen out timing paths that have a timing violation risk due to clock offset, which is beneficial to improving the yield of the chip.

[0125] In some implementations, on-chip variation (OCV) is considered to improve the accuracy of the chip's SignOff (S2S) comparison. Due to the influence of OCV, the timing path T... CO T L and T C These are all range values, not constants; their final values ​​depend on the final manufactured chip, taking T into account. Slack Hold At that time, the most pessimistic outcome occurred in T CO T L Minimum and T C In the worst-case scenario, and T Slack Setup Conversely. Therefore, for The input port serves as the endpoint of the timing path, acting as the Capture Clock, with the corresponding clock delay information. For the output port, the maximum value needs to be taken to ensure that all possible worst-case scenarios are covered, while for the output port, the opposite is true. The clock x acts as the Launch Clock, and its clock delay information Then take the minimum value.

[0126] The aforementioned OCV refers to the difference in actual timing delay between two identical cells on a chip, even under the same input signal and load conditions, due to their different locations on the chip, assuming the same manufacturing process. Since on-chip errors directly and negatively impact the timing of the design, their presence becomes a crucial aspect of timing checks.

[0127] In this application, by thoroughly searching for fan-in and fan-out timing logic elements connected to the clock port, it can be ensured that no potentially risky timing paths are missed. This is achieved by setting boundary conditions L. CS and L S We can obtain a reasonable and comprehensive list of risky time-series paths because the results obtained in this search are all the worst-case scenarios.

[0128] In some implementations, the timing paths in the second list can be precisely calculated, and timing paths with potential risks can be further identified.

[0129] In some implementations, the actual hold time margin of timing paths in the second list can be calculated using the STA tool. This is because the second list includes all timing paths in the worst-case scenario. Some timing paths may not need to be checked in STA, or the hold time margin of some timing paths may not be as bad as the results calculated in the screening in the actual simulation results. In this case, some timing paths can be skipped to reduce the workload of checking.

[0130] The specific inspection process is as follows:

[0131] 1) If the timing path does not exist or does not need to be checked, skip it directly;

[0132] 2) If the hold time margin of the timing path is infinite or non-numerical, then skip it directly;

[0133] 3) If the timing path exists and the hold time margin is a valid value, then determine the actual hold time margin in the actual simulation. If the actual hold time margin is greater than the set L... SIf it is, skip directly; otherwise, continue to judge the actual simulated clock offset T after compensating for Common Path Pessimism (CPP). CS Real If the compensated clock offset T CS Real Less than or equal to L CS Then skip it.

[0134] The following more precise calculations are performed on the time-series paths remaining after the above three screening steps:

[0135] Obtain the delay between each node (input and output port pair) in the timing path, such as the delay of registers, the delay of combinational logic modules, line delay, and other segments of delay that constitute the delay of the entire timing path.

[0136] Obtain the Derate value for each delay segment (a factor used to constrain and adjust the delay), restore the path delay without the Derate value, and then obtain the final compensated delay value T using the pre-defined Derate value for compensation. Over Derate ;

[0137] F P Introduced into the hold time margin T Slack Hold In the middle, the processed target retention time margin T is obtained. Slack Hold Post The calculation formula is as follows:

[0138] T Slack Hold Post =T Slack Hold +(T CS Real ·F P +T Over Derate ) Formula 1-7

[0139] If T Slack Hold Post If the value is greater than 0, the timing path is considered to have no risk; otherwise, the timing path is determined to have timing risks caused by clock skew.

[0140] In some implementations, in order to reasonably avoid the aforementioned timing risks before tape-out without significantly altering the original design, it is necessary to redefine the time margin for the timing path during hold-time checks, denoted as T. Path Margin Fixed The formula is as follows:

[0141] T Path Margin Fixed =T Slack Hold +(T CS Real ·T P +T Ovet Derate ) Formula 1-8

[0142] In some implementations, backend designers can modify risky timing paths based on new hold-time margins to ensure that T... Path Margin Fixed T belowSlack Hold It should not be less than 0.

[0143] In this application, the time series path list screened earlier is regressed to the STA tool to obtain a specific and accurate time series report, which is then used to reassess whether the checked time series paths pose a risk, again through boundary condition L. CS To screen, and then through F P The potential timing offset risk is quantified into the hold time margin calculation formula. If the quantified hold time margin is still less than 0, it means that sufficient hold time margin needs to be added to the timing path. In this way, the timing offset risk can be combined into the calculation in the STA tool to ensure that the chip tape-out will not reduce the yield.

[0144] The timing path screening method provided in this application adds timing paths with timing violation risks to a second list, which can filter out some timing paths and reduce the workload of screening. Then, the remaining timing paths are accurately calculated to accurately screen out timing paths with timing violation risks caused by clock offset, thereby helping to improve the yield of the chip.

[0145] Based on the content described in the above embodiments, this disclosure also provides a time-series path screening device, referring to... Figure 5 , Figure 5 This is a schematic diagram of the program modules of a timing path screening device provided in an embodiment of this disclosure. The timing path screening device includes:

[0146] The determination module 501 is used to determine the timing path associated with the timing logic element corresponding to each clock port in the first list.

[0147] The calculation module 502 is used to calculate the clock offset corresponding to each of the timing paths.

[0148] The judgment module 503 is used to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the preset clock offset threshold.

[0149] In one feasible implementation, an acquisition module is also included, for:

[0150] Obtain the clock ports corresponding to each clock cycle in the chip under test, and add each clock port to the first list.

[0151] In one feasible implementation, an acquisition module is also included, for:

[0152] The STA tool is used to obtain the clock delay of each clock port corresponding to each clock in the chip under test, and the clock ports whose clock delay is not within the clock offset filtering range corresponding to each clock are added to the first list.

[0153] In one feasible implementation, the computing module is further used for:

[0154] Calculate the average clock delay of each clock port corresponding to each clock, and determine the clock offset filtering range corresponding to each clock based on the calculated average and the preset clock offset threshold.

[0155] In one feasible implementation, the determining module 501 is used for:

[0156] Find the non-clock input ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-in of each non-clock input port.

[0157] And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-out of each non-clock output port.

[0158] In one feasible implementation, the determining module 501 is specifically used for:

[0159] Determine the timing logic element The j-th non-clock input port Minimum hold time margin

[0160] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths;

[0161] Among them, sequential logic elements For the i-th clock port of the x-th clock in the first list The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0162] In one feasible implementation, the determining module 501 is specifically used for:

[0163] Determine the timing logic element The j-th non-clock output port Minimum hold time margin

[0164] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths;

[0165] Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0166] In one feasible implementation, the computing module 502 is used for:

[0167] According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the clock delay of the x-th clock.

[0168] Determine the input port The k-th fan-in Clock delay relative to the x-th clock And determine the output port The kth fan-out Clock delay relative to the x-th clock

[0169] According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where x, i, j, and k are all positive integers.

[0170] In one feasible implementation, the determination module 503 is used for:

[0171] When the fan-in When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fan-in is determined. The corresponding timing path carries a risk of timing violation.

[0172] And / or, when the fan-out When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fanout is determined. The corresponding timing path has a risk of timing violation.

[0173] In one feasible implementation, a filtering module is also included, for:

[0174] Add the timing path that has the risk of timing violation to the second list;

[0175] Use the STA tool to determine the actual hold time margin for each timing path in the second list;

[0176] Based on the clock offset corresponding to each timing path in the second list and the actual hold time margin, determine whether each timing path in the second list meets the preset timing conditions.

[0177] In one feasible implementation, the above-mentioned filtering module is specifically used for:

[0178] When there is a first timing path in the second list whose actual hold time margin is less than the preset margin threshold, the clock offset of the first timing path is compensated according to the preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the third list.

[0179] Based on the clock offset corresponding to each first timing path in the third list and the actual hold time margin, determine whether each first timing path in the third list meets the preset timing conditions.

[0180] In one feasible implementation, the above-mentioned filtering module is specifically used for:

[0181] Determine the compensation delay value corresponding to each first timing path in the third list;

[0182] Based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters corresponding to each first timing path in the third list, calculate the target hold time margin corresponding to each first timing path in the third list.

[0183] When the target hold time margin is greater than zero, it is determined that the first timing path corresponding to the target hold time margin meets the preset timing conditions. When the target hold time margin is less than or equal to zero, it is determined that the first timing path corresponding to the target hold time margin does not meet the preset timing conditions.

[0184] It should be noted that the specific execution of the determining module 501, the calculation module 502, and the judgment module 503 in this embodiment can be found in the [reference needed]. Figure 3 The relevant content in the illustrated embodiments will not be repeated here.

[0185] The timing path screening device provided in this application determines the timing path related to the timing logic element corresponding to each clock port in the first list, and calculates the clock offset corresponding to each timing path. Based on the clock offset corresponding to each timing path and the preset clock offset threshold, it can determine whether there is a timing violation risk in each timing path. This can accurately screen out timing paths that have a timing violation risk due to clock offset, which is beneficial to improving the yield of the chip.

[0186] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the timing path screening method described in the above embodiments, which will not be repeated here.

[0187] To better understand the embodiments of this disclosure, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0188] like Figure 6 As shown, the electronic device 60 of this embodiment includes: a processor 601 and a memory 602; wherein:

[0189] Memory 602 is used to store instructions executed by the computer;

[0190] The processor 601 is used to execute computer execution instructions stored in the memory to implement the various steps in the timing path screening method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0191] Alternatively, the memory 602 can be either standalone or integrated with the processor 601.

[0192] When the memory 602 is set up independently, the device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0193] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the computer executes the computer-executable instructions, it implements the various steps in the timing path screening method described in the above embodiments. This embodiment will not repeat the details here.

[0194] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer program product, including a computer program. When a computer executes the computer program, it can implement the various steps in the timing path screening method described in the above embodiments, which will not be repeated here.

[0195] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0196] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0197] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0198] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A time-series path screening method, characterized in that, The method includes: Determine the timing path associated with the timing logic element corresponding to each clock port in the first list; Calculate the clock offset corresponding to each of the timing paths; Based on the clock offset corresponding to each timing path and the preset clock offset threshold, determine whether there is a timing violation risk in each timing path; The clock delay of each clock port corresponding to each clock in the chip under test is obtained using the Static Timing Analysis (STA) tool, and clock ports whose clock delay is not within the clock offset filtering range corresponding to each clock are added to the first list. The determination of the timing path associated with the timing logic element corresponding to each clock port in the first list includes: Find the non-clock input ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-in of each non-clock input port. And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-out of each non-clock output port. The step of determining the timing path associated with the timing logic element corresponding to each clock port in the first list based on the fan-in of each of the non-clock input ports includes: Determine the timing logic element The One non-clock input port Minimum hold time margin ; If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths; Among them, sequential logic elements For the first list of The clock of the first hour clock ports The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; , All are positive integers; The step of determining the timing path related to the timing logic element corresponding to each clock port in the first list based on the fan-out of each of the non-clock output ports includes: Determine the timing logic element The One non-clock output port Minimum hold time margin ; If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths; Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; The calculation of the clock offset corresponding to each timing path includes: According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the first... Clock delay of one clock cycle ; Determine the input port The Fan-in Relative to the first Clock delay of one clock cycle and determine the output port The A fan-shaped fan Relative to the first Clock delay of one clock cycle ; According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where, , , All are positive integers; The step of determining whether each timing path has a timing violation risk based on the clock offset corresponding to each timing path and a preset clock offset threshold includes: When the fan-in When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fan-in is determined. The corresponding timing path carries a risk of timing violation. And / or, when fanning out When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fanout is determined. The corresponding timing path has a risk of timing violation.

2. The method according to claim 1, characterized in that, Also includes: Obtain the clock ports corresponding to each clock cycle in the chip under test, and add each clock port to the first list.

3. The method according to claim 1, characterized in that, Also includes: Calculate the average clock delay of each clock port corresponding to each clock, and determine the clock offset filtering range corresponding to each clock based on the calculated average and the preset clock offset threshold.

4. The method according to claim 1, characterized in that, Also includes: Add the timing path that has the risk of timing violation to the second list; Use the STA tool to determine the actual hold time margin for each timing path in the second list; Based on the clock offset corresponding to each timing path in the second list and the actual hold time margin, determine whether each timing path in the second list meets the preset timing conditions.

5. The method according to claim 4, characterized in that, The step of determining whether each timing path in the second list meets the preset timing conditions based on the clock offset corresponding to each timing path in the second list and the actual hold time margin includes: When there is a first timing path in the second list whose actual hold time margin is less than the preset margin threshold, the clock offset of the first timing path is compensated according to the preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the third list. Based on the clock offset corresponding to each first timing path in the third list and the actual hold time margin, determine whether each first timing path in the third list meets the preset timing conditions.

6. The method according to claim 5, characterized in that, The step of determining whether each first timing path in the third list meets the preset timing conditions based on the clock offset corresponding to each first timing path in the third list and the actual hold time margin includes: Determine the compensation delay value corresponding to each first timing path in the third list; Based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters corresponding to each first timing path in the third list, calculate the target hold time margin corresponding to each first timing path in the third list. When the target hold time margin is greater than zero, it is determined that the first timing path corresponding to the target hold time margin meets the preset timing conditions. When the target hold time margin is less than or equal to zero, it is determined that the first timing path corresponding to the target hold time margin does not meet the preset timing conditions.

7. A time-series path screening device, characterized in that, The device includes: The determination module is used to determine the timing path associated with the timing logic element corresponding to each clock port in the first list; wherein, the clock delay of each clock port corresponding to each clock in the chip under test is obtained by using the Static Timing Analysis (STA) tool, and clock ports whose clock delay is not within the clock offset filtering range corresponding to each clock are added to the first list. The calculation module is used to calculate the clock offset corresponding to each of the timing paths; The judgment module is used to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the preset clock offset threshold. The determining module is specifically used to find the non-clock input ports of the sequential logic elements corresponding to each clock port in the first list, and to determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-in of each non-clock input port. And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port in the first list, and determine the timing path related to the sequential logic elements corresponding to each clock port in the first list based on the fan-out of each non-clock output port. The determining module is specifically used to determine sequential logic elements. The One non-clock input port Minimum hold time margin ; If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths; Among them, sequential logic elements For the first list of The clock of the first hour clock ports The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; , All are positive integers; The determining module is specifically used to determine the timing logic element. The One non-clock output port Minimum hold time margin ; If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths; Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; The calculation module is specifically used to calculate based on the timing logic elements. The clock trigger type, and the clock port The clock delay information is used to determine the first... Clock delay of one clock cycle ; Determine the input port The Fan-in Relative to the first Clock delay of one clock cycle and determine the output port The A fan-shaped fan Relative to the first Clock delay of one clock cycle ; According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where, , , All are positive integers; The judgment module is specifically used when the fan-in When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fan-in is determined. The corresponding timing path carries a risk of timing violation. And / or, when fanning out When the clock offset of the corresponding timing path is negative and its absolute value is greater than the preset clock offset threshold, the fanout is determined. The corresponding timing path has a risk of timing violation.

8. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the timing path screening method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, implement the timing path screening method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a computer, it implements the timing path screening method according to any one of claims 1 to 6.

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