Time-series path screening methods and equipment

Abstract

This application provides a timing path screening method and apparatus, relating to the field of integrated circuit technology. The method includes: acquiring each clock port corresponding to each clock cycle in the chip under test, and determining the timing paths associated with the timing logic elements corresponding to each clock port; calculating the clock offset corresponding to each timing path; using a ST (Scheduling and Timing) tool to determine the actual hold time margin of each timing path; and determining whether each timing path has a timing violation risk based on the clock offset and the actual hold time margin. This application can accurately screen out timing paths with timing violation risks due to clock offsets, thereby improving chip yield.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a timing path screening method and device. Background Technology

[0002] In the chip design process, static timing analysis (STA) tools are usually used to check whether the entire chip meets timing requirements in various application scenarios. If there are timing violations in the chip, it may lead to low yield or even failure of the produced chip.

[0003] Clock skew (CS) refers to the difference between different phases of sub-clocks generated by the same clock, which can affect circuit timing to some extent. In practical applications, existing STA tools struggle to calculate the precise value of timing paths with significant clock skew, making it impossible to identify timing paths at risk of timing violations due to clock skew. This prevents engineers from compensating for the relevant timing paths, ultimately impacting chip yield. Summary of the Invention

[0004] This application provides a timing path screening method and device, which can accurately screen out timing paths that have a risk of timing violations due to clock offset, thereby improving chip yield.

[0005] In a first aspect, embodiments of this application provide a time-series path screening method, the method comprising:

[0006] Obtain the clock ports corresponding to each clock in the chip under test, and determine the timing paths associated with the timing logic elements corresponding to each clock port;

[0007] Calculate the clock offset corresponding to each of the timing paths;

[0008] The actual hold time margin of each timing path is determined using the STA tool. Based on the clock offset corresponding to each timing path and the actual hold time margin, it is determined whether there is a timing violation risk in each timing path.

[0009] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port includes:

[0010] Find the non-clock input ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-in of each non-clock input port.

[0011] And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-out of each non-clock output port.

[0012] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port based on the fan-in of each of the non-clock input ports includes:

[0013] Determine the timing logic element The j-th non-clock input port Minimum hold time margin

[0014] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths;

[0015] Among them, sequential logic elements For the i-th clock port of the x-th clock. The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0016] In some embodiments, determining the timing path associated with the timing logic element corresponding to each clock port based on the fan-out of each of the non-clock output ports includes:

[0017] Determine the timing logic element The j-th non-clock output port Minimum hold time margin

[0018] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths;

[0019] Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0020] In some embodiments, calculating the clock offset corresponding to each timing path includes:

[0021] According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the clock delay of the x-th clock.

[0022] Determine the input port The k-th fan-in Clock delay relative to the x-th clock And determine the output port The kth fan-out Clock delay relative to the x-th clock

[0023] According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where x, i, j, and k are all positive integers.

[0024] In some embodiments, determining whether there is a timing violation risk for each timing path based on the clock offset corresponding to each timing path and the actual hold time margin includes:

[0025] When there is a first timing path in each timing path whose actual hold time margin is less than the preset margin threshold, the clock offset of the first timing path is compensated according to the preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the first list.

[0026] Based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin, determine whether there is a timing violation risk for each first timing path in the first list.

[0027] In some embodiments, determining whether each first timing path in the first list has a timing violation risk based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin includes:

[0028] Determine the compensation delay value corresponding to each first timing path in the first list;

[0029] Based on the actual hold time margin, compensation delay value, compensation clock offset and preset quantization parameters of each first timing path in the first list, calculate the target hold time margin corresponding to each first timing path in the first list.

[0030] When the target hold time margin is greater than zero, it is determined that the first timing path corresponding to the target hold time margin has no timing violation risk. When the target hold time margin is less than or equal to zero, it is determined that the first timing path corresponding to the target hold time margin has a timing violation risk.

[0031] Secondly, embodiments of this application provide a time-series path screening device, the device comprising:

[0032] The determination module is used to obtain each clock port corresponding to each clock in the chip under test, and determine the timing path related to the timing logic element corresponding to each clock port;

[0033] The calculation module is used to calculate the clock offset corresponding to each of the timing paths;

[0034] The judgment module is used to determine the actual hold time margin of each timing path using the STA tool, and to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin.

[0035] Thirdly, embodiments of this application provide an electronic device, including: at least one processor and a memory;

[0036] The memory stores computer-executed instructions;

[0037] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the timing path screening method as provided in the first aspect.

[0038] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the timing path screening method provided in the first aspect.

[0039] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a computer, implements the timing path screening method provided in the first aspect.

[0040] The timing path screening method and device provided in this application can: acquire each clock port corresponding to each clock in the chip under test, determine the timing path related to the timing logic element corresponding to each clock port, calculate the clock offset corresponding to each timing path, determine the actual hold time margin of each timing path using the STA tool, and determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin. This can accurately screen out timing paths that have a timing violation risk due to clock offset, thereby helping to improve the yield of the chip. Attached Figure Description

[0041] Figure 1 This is a schematic diagram illustrating the setup and hold times of sequential logic elements in the embodiments of this disclosure;

[0042] Figure 2 This is a schematic diagram of a timing path provided in an embodiment of this application;

[0043] Figure 3 This is a flowchart illustrating the steps of a clock offset screening method provided in an embodiment of this application;

[0044] Figure 4 This is a schematic diagram of the program modules of a clock offset screening device provided in the embodiments of this application;

[0045] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, although the disclosure in this application is described with reference to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0047] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0048] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, to implement the embodiments in a sequence other than those given in the illustrations or descriptions of this application.

[0049] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0050] The term "module" as used in the embodiments of this application refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0051] The clock offset screening method provided in this application embodiment can be applied to various types of chips, such as advanced high-performance digital chips, high-performance central processing units (CPUs), high-performance graphics processing units (GPUs), high-performance artificial intelligence (AI) chips, high-performance baseband chips, etc., and is not limited in this application embodiment.

[0052] In the semiconductor technology field, in the design flow of Application Specific Integrated Circuits (ASICs) based on standard cell libraries, chip designers typically use hardware description languages ​​to design chips, that is, to model the chip functions, and then use automated design software to synthesize the design code into standard cell circuits. Then, through physical back-end design, the standard cell circuits are converted into graphic data stream (GDS) layouts that can be manufactured under the corresponding process technology, and finally delivered to the foundry to produce the chips.

[0053] When performing ASIC design based on standard cell libraries, foundries typically provide a Process Design Kit (PDK) in advance, which includes the design of some sequential logic elements and timing characteristic parameters (such as setup time or hold time).

[0054] Optionally, the aforementioned sequential logic elements can be latches, flip-flops (FF), etc.

[0055] A latch is a type of storage unit circuit that is sensitive to pulse levels. It can change its state under the influence of a specific input pulse level. Latching is the process of temporarily storing a signal to maintain a certain level state. In digital circuits, it can record binary digital signals "0" and "1".

[0056] A flip-flop, also called a bistable gate, is a storage component with two stable states. It can record binary digital signals "1" and "0", and its output is determined by the data input at the time specified by the input clock.

[0057] The setup time of a sequential logic element is the shortest time that the data input signal must remain stable before the effective edge of the clock; the hold time is the shortest time that the data input signal must remain stable after the effective edge of the clock.

[0058] Understandably, in an ideal situation, as long as valid data arrives at the same time as the clock's valid edge (before or simultaneously with the clock's valid edge), the sequential logic element can correctly acquire the data; and after (or simultaneously with) the clock's valid edge, even if the data changes, it will not affect the output of the sequential logic element.

[0059] However, in reality, it takes time for the switch to open at the clock edge, and it also takes time for the state of logic gates to change (such as capacitor charging and discharging). Therefore, data acquisition requires a certain amount of time, during which the data cannot change. That is, the data must be "prepared" in advance for a minimum amount of time before the clock edge arrives; this minimum amount of time is the setup time mentioned above. Additionally, it also takes time for the switch to close at the clock edge. If the data changes during this period, the new data may be passed to the next stage, leading to errors. Therefore, the data must remain unchanged for a certain period of time; that is, after the clock edge arrives, the data must remain unchanged for a minimum amount of time; this minimum amount of time is the hold time mentioned above.

[0060] To better understand the embodiments of this application, please refer to... Figure 1 , Figure 1 This is a schematic diagram showing the setup and hold times of sequential logic elements in the embodiments of this application.

[0061] exist Figure 1In the setup time, before the rising edge of the clock signal CK arrives, the data signal D must be "prepared" in advance for a minimum amount of time and cannot change. In addition, after the rising edge of the clock signal CK arrives, the data D must still remain unchanged for a minimum amount of time. This minimum amount of time is called the hold time.

[0062] During the chip design process, it is usually necessary to use the STA tool to check whether the entire chip meets the timing requirements in various application scenarios, based on the relevant constraints and guidance documents provided by the semiconductor foundry. That is, to check whether the timing slack is less than 0. If the timing slack is less than 0, it means that there is a timing path with timing violations in the chip.

[0063] To ensure that the manufactured chips meet their functional and performance requirements, it is necessary to ensure that there are no timing violations in the final STA check before the chip design documents are submitted to the semiconductor foundry. Otherwise, the manufactured chips may have a low yield or even fail.

[0064] Clock skew typically refers to the time difference between sub-clocks of different phases generated by the same clock, which affects circuit timing to some extent.

[0065] Although the STA tool has almost eliminated all possible timing paths with violations, the final tape-out results show that some of the failed chips still failed due to clock skew. That is, even though the clock skew has been included in the timing analysis, the STA tool cannot calculate the precise value for timing paths with large clock skew.

[0066] To address the aforementioned technical problems, this application provides a clock skew screening method that can accurately identify timing paths at risk of timing violations due to clock skew, thereby improving chip tape-out yield. For detailed implementation methods, please refer to the following embodiments.

[0067] Understandably, in chip design, the data transmission between the output port of a sequential logic element (such as a register) and the input port of the next sequential logic element via combinational logic elements can be considered a timing path. For a chip, it contains a large number of timing paths, and these timing paths can be used to calculate whether there are timing violations.

[0068] To better understand the embodiments of this application, please refer to... Figure 2 , Figure 2 This is a schematic diagram of a timing path provided in an embodiment of this application. Figure 2In this type of timing path, the starting point, i.e., the sequential logic element 201 that provides data output, is called the launch cell. The transmission path of its control clock is called the launch clock, and the corresponding clock delay is denoted as T. L Correspondingly, another sequential logic element 202 is called a capture cell, and the transmission path of its control clock is called the capture clock. The corresponding clock delay is denoted as T. C The data transmission path that passes through combinational logic element 203 is called the data path, and the corresponding data transmission delay is denoted as T. CO Additionally, the clock period of the input clock signal CLK is denoted as T.

[0069] As key parameters for timing checks, the calculation of setup and hold time margins for sequential logic elements determines whether timing path violations exist. The setup and hold time margins are denoted as T, respectively. Slack Setup and T Slack Hold Timing checks are only satisfied when both values ​​are greater than 0. The calculation formula is as follows:

[0070] T Slack Setup =TT CO -(T L -T C ) Formula 1-1

[0071] T Slack Hold =T CO +(T L -T C ) Formula 1-2

[0072] Let the clock offset be denoted as T. CS The calculation formula is as follows:

[0073] T CS =T L -T C Formula 1-3

[0074] Then, from formulas 1-1 and 1-2, we can directly derive:

[0075] T Slack Setup =TT CO -T CS Formula 1-4

[0076] T Slack Hold =TCO +T CS Formula 1-5

[0077] When T CS When ≥0, T Slack Setup With T Slack Hold There will be no timing violations due to clock skew; when T CS When <0, T Slack Setup There are no timing violations due to clock skew, and T Slack Hold There may be a risk that the value will be less than 0.

[0078] To avoid because of T CS T is negative Slack Hold If a value less than 0 exists, the first step is to identify which timing paths pose a potential risk. In some embodiments, a boundary condition for the check is introduced: a clock skew limit (hereinafter referred to as L). CS Slack Limit (hereinafter referred to as L) S )) and quantization parameter (F P ), where L CS Used to specify which T CS Negative values ​​for L can be considered within a safe range. S Used to specify which T Slack Hold This can be considered a safe range, while F P As a risk coefficient, it is used in feedback T CS For T Slack Hold The values ​​of these three boundary conditions are set based on specific manufacturing processes, project data, and experience. Therefore, Formula 1-5 can be evolved into:

[0079] T Slack Hold Post =T CO +T CS -F P ·|T CS | Formula 1-6

[0080] For those in L CS With L S For timing paths other than those specified, their hold time margin will be recalculated using formulas 1-6, when T Slack Hold Post When the value is negative, it indicates that the timing path is at risk of timing violation.

[0081] Reference Figure 3 , Figure 3 This is a schematic flowchart illustrating the steps of a clock skew screening method provided in an embodiment of this application. In one feasible implementation, the clock skew screening method includes the following steps:

[0082] S301. Obtain each clock port corresponding to each clock in the chip under test, and determine the timing path related to the timing logic element corresponding to each clock port.

[0083] S303. Calculate the clock offset corresponding to each timing path.

[0084] S304. Use the Static Timing Analysis (STA) tool to determine the actual hold time margin of each timing path, and determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin.

[0085] In some embodiments, step S301 includes:

[0086] Find the non-clock input ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-in of each non-clock input port; and / or find the non-clock output ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-out of each non-clock output port.

[0087] For example, sequential logic elements can be determined. The j-th non-clock input port Minimum hold time margin like If it is less than or equal to a preset margin threshold, then according to the input port Fan-in determines the timing logic element. Related timing paths; among which, For the i-th clock port of the x-th clock. The sequential logic element it is located in For input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0088] Determine the timing logic element The j-th non-clock output port Minimum hold time margin like If it is less than or equal to the preset margin threshold, then it depends on the output port. The fan-out, confirmed with Related timing paths; among which, For output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0089] In one feasible implementation, step S301 specifically includes:

[0090] 1.1 Obtain the clock ports corresponding to each clock cycle in the chip under test.

[0091] 1.2 Determine the i-th clock port of the x-th clock. The sequential logic element is located and obtain All non-clock input ports.

[0092] in, correspond and It may contain other clock port pins. CK For example, the (i+n)th clock port

[0093] 1.3. Based on sequential logic elements The clock trigger type and clock port The clock delay information is used to determine the clock delay of the x-th clock cycle.

[0094] In some implementations, first determine What type of clock trigger is it? The clock trigger types include rising edge trigger, falling edge trigger, high level trigger, and low level trigger, which are obtained by acquiring... All clock delay information, and then according to Select valid information from the clock trigger types to obtain the corresponding clock delay information for clock x.

[0095] 1.4 Determine the sequential logic elements The j-th non-clock input port Minimum hold time margin

[0096] In some implementations, the input port is obtained. The smaller of the rising-edge triggered hold time margin and the falling-edge triggered hold time margin is taken as its minimum hold time margin.

[0097] 1.5. For input ports Obtain all its fan-in values ​​and calculate the k-th fan-in value. Clock delay information relative to clock x The method is the same as the steps in 1.3.

[0098] In some implementations, if Greater than L S If so, skip the input port. No further investigation will be conducted. input port Obtain all its fan-in values ​​and calculate the k-th fan-in value. Clock delay information relative to clock x

[0099] 1.6 Calculate the fan-in The corresponding T CS for

[0100] Optional, if It is a negative number and its absolute value is greater than L. CS Then for this time-series path Perform further checks; otherwise, skip the check for that path.

[0101] Among them, fan-in and As timing paths respectively The starting point and the ending point.

[0102] Similarly, determine the output port. The kth fan-out Clock delay relative to the x-th clock cycle And calculate the fan-out The corresponding T CS for

[0103] Optional, if It is a negative number and its absolute value is greater than L. CS Then for this time-series path Perform further checks; otherwise, skip the check for that path.

[0104] In some implementations, on-chip variation (OCV) is considered to improve the accuracy of silicon-to-signoff (S2S) comparisons. Due to OCV, the timing path T... CO T L and T CThese are all range values, not constants; their final values ​​depend on the final manufactured chip, taking T into account. Slack Hold At that time, the most pessimistic outcome occurred in T CO T L Minimum and T C In the worst-case scenario, and T Slack Setup Conversely. Therefore, for The input port serves as the endpoint of the timing path, acting as the capture clock, along with the corresponding clock delay information. For the output port, the maximum value needs to be taken to ensure that all possible worst-case scenarios are covered, while for the output port, the opposite is true. The clock x acts as the launch clock, and its clock delay information... Then take the minimum value.

[0105] The aforementioned OCV refers to the difference in actual timing delay between two identical cells on a chip, even under the same input signal and load conditions, due to their different locations on the chip, assuming the same manufacturing process. Since on-chip errors directly and negatively impact the timing of the design, their presence becomes a crucial aspect of timing checks.

[0106] In this application, by thoroughly searching for fan-in and fan-out timing logic elements connected to the clock port, it can be ensured that no potentially risky timing paths are missed. This is achieved by setting boundary conditions L. CS and L S We can obtain a reasonable and comprehensive list of risky time-series paths because the results obtained in this search are all the worst-case scenarios.

[0107] In some implementations, the actual hold time margin of each of the above timing paths can be calculated using the STA tool. This is because some timing paths may not need to be checked in STA, or the hold time margin of some timing paths may not be as bad as the results calculated in the screening in the actual simulation results. In this case, some timing paths can be skipped to reduce the workload of checking.

[0108] The specific inspection process is as follows:

[0109] 1) If the timing path does not exist or does not need to be checked, skip it directly;

[0110] 2) If the hold time margin of the timing path is infinite or non-numerical, then skip it directly;

[0111] 3) If the timing path exists and the hold time margin is a valid value, then determine the actual hold time margin in the actual simulation. If the actual hold time margin is greater than the set L... S If it is, skip directly; otherwise, continue to judge the actual simulated clock offset T after compensating for Common Path Pessimism (CPP). CS Real If the compensated clock offset T CS Real Less than or equal to L CS Then skip directly. For example, when there is an actual hold time margin in each of the timing paths that is less than the preset margin threshold L. S When the first timing path is selected, the clock offset of the first timing path is compensated according to a preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the first list.

[0112] The timing paths remaining in the first list after the above three screening steps are further filtered to identify those with a risk of timing violations, including:

[0113] Determine the compensation delay value corresponding to each first timing path in the first list; calculate the target hold time margin corresponding to each first timing path in the first list based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters; when the target hold time margin is greater than zero, determine that the first timing path corresponding to the target hold time margin has no timing violation risk; when the target hold time margin is less than or equal to zero, determine that the first timing path corresponding to the target hold time margin has a timing violation risk.

[0114] For example, the timing paths in the first list can be calculated more precisely as follows:

[0115] Obtain the delay between each node (input and output port pair) in the timing path, such as the delay of registers, the delay of combinational logic modules, line delay, and other delay segments that constitute the delay of the entire timing path.

[0116] Obtain the Derate value for each delay segment (a factor used to constrain and adjust the delay), restore the path delay without the Derate value, and then obtain the final compensated delay value T using the pre-defined Derate value for compensation. Over Derate ;

[0117] F P Introduced into the hold time margin T Slack HoldIn the middle, the processed target retention time margin T is obtained. Slack Hold Post The calculation formula is as follows:

[0118] T Slack Hold Oost =T Slack Hold +(T CS Real ·F P +T Over Derate ) Formula 1-7 If T Slack Hold Post If the value is greater than 0, the timing path is considered to have no risk; otherwise, the timing path is determined to have timing risks caused by clock skew.

[0119] In some implementations, in order to reasonably avoid the aforementioned timing risks before tape-out without significantly altering the original design, it is necessary to redefine the time margin for the timing path during hold-time checks, denoted as T. Path Margin Fixed The formula is as follows:

[0120] T Path Margin Fixed =T Slack Hold +(T CS Real ·F P +T Over Derate ) Formula 1-8 In some implementations, backend designers can modify risky timing paths based on new hold-time margins to ensure that T... Path Margin Fixed T below Slack Hold It should not be less than 0.

[0121] In this application, the time series path list screened earlier is regressed to the STA tool to obtain a specific and accurate time series report, which is then used to reassess whether the checked time series paths pose a risk, again through boundary condition L. CS To screen, and then through F PThe potential timing offset risk is quantified into the hold time margin calculation formula. If the quantified hold time margin is still less than 0, it means that sufficient hold time margin needs to be added to the timing path. In this way, the timing offset risk can be combined into the calculation in the STA tool to ensure that the chip tape-out will not reduce the yield.

[0122] The timing path screening method provided in this application obtains each clock port corresponding to each clock in the chip under test, determines the timing path related to the timing logic element corresponding to each clock port, calculates the clock offset corresponding to each timing path, uses the STA tool to determine the actual hold time margin of each timing path, and determines whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin. This can accurately screen out timing paths that have a timing violation risk due to clock offset, thereby helping to improve the yield of the chip.

[0123] Based on the content described in the above embodiments, this disclosure also provides a time-series path screening device, referring to... Figure 4 , Figure 4 This is a schematic diagram of the program modules of a timing path screening device provided in an embodiment of this disclosure. The timing path screening device includes:

[0124] The determination module 401 is used to obtain each clock port corresponding to each clock in the chip under test, and determine the timing path related to the timing logic element corresponding to each clock port.

[0125] The calculation module 402 is used to calculate the clock offset corresponding to each of the timing paths.

[0126] The judgment module 403 is used to determine the actual hold time margin of each timing path using the STA tool, and to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin.

[0127] In one feasible implementation, the determining module 401 is specifically used for:

[0128] Find the non-clock input ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-in of each non-clock input port.

[0129] And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-out of each non-clock output port.

[0130] In one feasible implementation, the determining module 401 is specifically used for:

[0131] Determine the timing logic element The j-th non-clock input port Minimum hold time margin

[0132] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the input port The fan-in determines the relationship with the timing logic element. Related timing paths;

[0133] Among them, sequential logic elements For the i-th clock port of the x-th clock. The minimum hold time margin of the sequential logic element in question For the input port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin; x, i, and j are all positive integers.

[0134] In one feasible implementation, the determining module 401 is specifically used for:

[0135] Determine the timing logic element The j-th non-clock output port Minimum hold time margin

[0136] If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths;

[0137] Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

[0138] In one feasible implementation, the computing module 402 is specifically used for:

[0139] According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the clock delay of the x-th clock.

[0140] Determine the input port The k-th fan-in Clock delay relative to the x-th clock And determine the output port The kth fan-out Clock delay relative to the x-th clock

[0141] According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where x, i, j, and k are all positive integers.

[0142] In one feasible implementation, the determination module 403 is specifically used for:

[0143] When there is a first timing path in each timing path whose actual hold time margin is less than the preset margin threshold, the clock offset of the first timing path is compensated according to the preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the first list.

[0144] Based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin, determine whether there is a timing violation risk for each first timing path in the first list.

[0145] In one feasible implementation, the determination module 403 is specifically used for:

[0146] Determine the compensation delay value corresponding to each first timing path in the first list;

[0147] Based on the actual hold time margin, compensation delay value, compensation clock offset and preset quantization parameters of each first timing path in the first list, calculate the target hold time margin corresponding to each first timing path in the first list.

[0148] When the target hold time margin is greater than zero, it is determined that the first timing path corresponding to the target hold time margin has no timing violation risk. When the target hold time margin is less than or equal to zero, it is determined that the first timing path corresponding to the target hold time margin has a timing violation risk.

[0149] It should be noted that the specific execution of the determining module 401, the calculation module 402, and the judgment module 403 in this embodiment can be found in the [reference needed]. Figure 3The relevant content in the illustrated embodiments will not be repeated here.

[0150] The timing path screening device provided in this application obtains each clock port corresponding to each clock in the chip under test, determines the timing path related to the timing logic element corresponding to each clock port, calculates the clock offset corresponding to each timing path, uses the STA tool to determine the actual hold time margin of each timing path, and determines whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin. This can accurately screen out timing paths that have a timing violation risk due to clock offset, thereby helping to improve the yield of the chip.

[0151] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the timing path screening method described in the above embodiments, which will not be repeated here.

[0152] To better understand the embodiments of this disclosure, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0153] like Figure 5 As shown, the electronic device 50 of this embodiment includes: a processor 501 and a memory 502; wherein:

[0154] Memory 502 is used to store instructions executed by the computer;

[0155] The processor 501 is used to execute computer execution instructions stored in the memory to implement the various steps in the timing path screening method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0156] Alternatively, the memory 502 can be either standalone or integrated with the processor 501.

[0157] When the memory 502 is set up independently, the device also includes a bus 503 for connecting the memory 502 and the processor 501.

[0158] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When a computer executes the computer-executable instructions, it implements the various steps in the timing path screening method described in the above embodiments. This embodiment will not repeat the details here.

[0159] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer program product, including a computer program. When a computer executes the computer program, it can implement the various steps in the timing path screening method described in the above embodiments, which will not be repeated here.

[0160] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0161] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0162] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A timing path screening method, characterized by, The method includes: Obtain the clock ports corresponding to each clock in the chip under test, and determine the timing paths associated with the timing logic elements corresponding to each clock port; Calculate the clock offset corresponding to each of the timing paths; The actual hold time margin of each timing path is determined using the Static Timing Analysis (STA) tool. Based on the clock offset corresponding to each timing path and the actual hold time margin, it is determined whether there is a timing violation risk in each timing path. The step of determining whether each timing path has a timing violation risk based on the clock offset corresponding to each timing path and the actual hold time margin includes: When there is a first timing path in each timing path whose actual hold time margin is less than a preset margin threshold, the clock offset of the first timing path is compensated according to a preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the first list; based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin, it is determined whether there is a timing violation risk in each first timing path in the first list; The step of determining whether each first timing path in the first list has a timing violation risk based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin includes: Determine the compensation delay value corresponding to each first timing path in the first list; calculate the target hold time margin corresponding to each first timing path in the first list based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters; when the target hold time margin is greater than zero, determine that the first timing path corresponding to the target hold time margin has no timing violation risk; when the target hold time margin is less than or equal to zero, determine that the first timing path corresponding to the target hold time margin has a timing violation risk.

2. The method of claim 1, wherein, The determination of the timing path associated with the timing logic element corresponding to each clock port includes: Find the non-clock input ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-in of each non-clock input port. And / or, respectively find the non-clock output ports of the sequential logic elements corresponding to each clock port, and determine the timing path related to the sequential logic elements corresponding to each clock port based on the fan-out of each non-clock output port.

3. The method of claim 2, wherein, The step of determining the timing path associated with the timing logic element corresponding to each clock port based on the fan-in of each of the non-clock input ports includes: Determining sequential logic elements jth non-clock input port of the flip flop minimum hold time margin of the flip flop ; If the minimum hold time margin is less than or equal to a preset margin threshold, then a timing path related to the sequential logic element is determined according to the fan-in of the input port . wherein the timing logic element is the ith clock port of the xth clock wherein the timing logic element is the minimum hold time margin of the input port is the minimum of the rising edge triggered hold time margin and the falling edge triggered hold time margin of the input port; x, i, j are positive integers.

4. The method of claim 3, wherein, The step of determining the timing path associated with the timing logic element corresponding to each clock port based on the fan-out of each non-clock output port includes: determining the timing logic element jth non-clock output port of the timing logic element minimum hold time margin of the timing logic element ; If the minimum holding time margin If it is less than or equal to a preset margin threshold, then according to the output port... The fan-out is determined in relation to the timing logic element. Related timing paths; Wherein, the minimum hold time margin For the output port The minimum of the rising edge trigger hold time margin and the falling edge trigger hold time margin.

5. The method according to claim 4, characterized in that, The calculation of the clock offset corresponding to each timing path includes: According to the timing logic element The clock trigger type, and the clock port The clock delay information is used to determine the clock delay of the x-th clock. ; Determine the input port The k-th fan-in Clock delay relative to the x-th clock and determine the output port The kth fan-out Clock delay relative to the x-th clock ; According to the clock delay With the clock delay Determine the fan-in The clock offset of the corresponding timing path, based on the clock delay. With the clock delay Determine the fan-out The clock offset of the corresponding timing path; where x, i, j, and k are all positive integers.

6. A time-series path screening device, characterized in that, The device includes: The determination module is used to obtain each clock port corresponding to each clock in the chip under test, and determine the timing path related to the timing logic element corresponding to each clock port; The calculation module is used to calculate the clock offset corresponding to each of the timing paths; The judgment module is used to determine the actual hold time margin of each timing path using the STA tool, and to determine whether there is a timing violation risk in each timing path based on the clock offset corresponding to each timing path and the actual hold time margin. The step of determining whether each timing path has a timing violation risk based on the clock offset corresponding to each timing path and the actual hold time margin includes: When there is a first timing path in each timing path whose actual hold time margin is less than a preset margin threshold, the clock offset of the first timing path is compensated according to a preset compensation method, and the first timing path whose compensated clock offset is greater than the preset clock offset threshold is added to the first list; based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin, it is determined whether there is a timing violation risk in each first timing path in the first list; The step of determining whether each first timing path in the first list has a timing violation risk based on the clock offset corresponding to each first timing path in the first list and the actual hold time margin includes: Determine the compensation delay value corresponding to each first timing path in the first list; calculate the target hold time margin corresponding to each first timing path in the first list based on the actual hold time margin, compensation delay value, compensated clock offset, and preset quantization parameters; when the target hold time margin is greater than zero, determine that the first timing path corresponding to the target hold time margin has no timing violation risk; when the target hold time margin is less than or equal to zero, determine that the first timing path corresponding to the target hold time margin has a timing violation risk.

7. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the timing path screening method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, implement the timing path screening method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a computer, it implements the timing path screening method according to any one of claims 1 to 5.

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