Synchronization circuit based on clock phase adjustment
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGSHA TACHYON MICROELECTRONICS CO LTD
- Filing Date
- 2022-09-20
- Publication Date
- 2026-07-03
Smart Images
Figure CN115459768B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a synchronization circuit based on clock phase adjustment. Background Technology
[0002] Multi-chip synchronization technology is widely used in systems that require defined time relationships, such as communications, radar, and distributed data acquisition, for time coordination between multiple chips or subsystems. System-level synchronization generally uses a high-precision clock source or a homogeneous pulse signal as a reference signal sysref. The reference signal is distributed to each subsystem with a defined delay. Within each subsystem, the local clock is synchronized using the reference signal sysref, thereby synchronizing all subsystems to the same reference signal sysref.
[0003] In existing technologies, the main method to synchronize the local clock to the reference signal sysref is to use the reference signal sysref to force the clock signal phase to zero. The advantage of this method is that the implementation circuit is simple, and only an analog circuit needs to be designed to clear the phase. The disadvantage is that this scheme has high requirements for the reference signal sysref. Skew and jitter of sysref will cause the loss of clock edges. Summary of the Invention
[0004] This invention provides a synchronization circuit based on clock phase adjustment to solve the problem that existing synchronization methods have high requirements for reference signals and are prone to clock edge loss.
[0005] To achieve the above objectives, this invention provides a synchronization circuit based on clock phase adjustment, comprising: a clock divider circuit for generating a divided clock signal from an input system clock; a phase detection circuit connected to the clock divider circuit for obtaining a phase offset value based on an input synchronization reference signal and the divided clock signal; a phase adjustment circuit connected to the clock divider circuit and the phase detection circuit for adjusting the phase of the input divided clock signal based on the phase offset value to obtain a phase-adjusted divided clock signal; and a synchronizer circuit connected to the phase adjustment circuit for obtaining a local synchronization reference signal based on the phase-adjusted divided clock signal and the synchronization reference signal.
[0006] Optionally, the clock divider circuit divides the system clock to obtain the required n-divided clock signal, where n=2. N N is an integer.
[0007] Optionally, the clock divider circuit divides the system clock to obtain N+1 divided clock signals, where the i-th divided clock signal is 2. i-1Frequency-divided clock signals, i = 1, 2, ..., N+1.
[0008] Optionally, the phase detection circuit detects the phase relationship between the synchronization reference signal and the frequency division clock signal, and obtains the n-bit phase offset value based on the phase relationship.
[0009] Optionally, the phase detection circuit acquires the phase offset value multiple times in half a system clock cycle, and performs an arithmetic average of the multiple acquisition results to obtain the final phase offset value.
[0010] Optionally, the phase adjustment circuit shifts the phase of the input clock divider signal by the phase shift value to obtain the phase-adjusted divider clock signal synchronized with the synchronization reference signal.
[0011] Optionally, the phase adjustment circuit adjusts the phase based on the phase offset value in steps of half a cycle of the system clock, from 0 to 2. N -1.5 cycles of 2 N By switching between phases, the frequency-divided clock signal after phase adjustment is obtained and synchronized with the synchronization reference signal.
[0012] Optionally, the synchronizer circuit samples the synchronization reference signal according to the phase-adjusted frequency-divided clock signal to obtain the local synchronization reference signal.
[0013] Optionally, the synchronizer circuit may also determine whether a phase shift has occurred based on the phase relationship between the adjusted frequency-divided clock signal and the synchronization reference signal, and return a set of control words to the phase adjustment circuit based on the phase shift.
[0014] Optionally, the phase adjustment circuit further adjusts the phase of the frequency division clock signal according to the control word and the phase offset value to resynchronize the phase.
[0015] The beneficial effects of this invention are as follows: As can be seen from the above description, the synchronization circuit based on clock phase adjustment provided by the embodiments of this invention includes: a clock divider circuit for generating a divided clock signal from the input system clock; a phase detection circuit connected to the clock divider circuit for obtaining a phase offset value based on the input synchronization reference signal and the divided clock signal; a phase adjustment circuit connected to the clock divider circuit and the phase detection circuit for adjusting the phase of the input divided clock signal based on the phase offset value to obtain the phase-adjusted divided clock signal; and a synchronizer circuit connected to the phase adjustment circuit for obtaining a local synchronization reference signal based on the phase-adjusted divided clock signal and the synchronization reference signal. This provides a multi-chip synchronization method based on clock phase adjustment, which can be applied to synchronize a local clock to a reference signal, adjust the clock phase quickly and in real time according to the phase relationship between the reference signal and the divided clock, and not lose the sampling edge of the clock during the adjustment process. It can be applied to integrated circuits with high sampling accuracy requirements. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the synchronization circuit based on clock phase adjustment in an embodiment of the present invention;
[0018] Figure 2 This is a schematic diagram of another synchronization circuit based on clock phase adjustment in an embodiment of the present invention;
[0019] Figure 3 This is a schematic diagram of the phase of the 4-division clock signal and the synchronization reference signal in an embodiment of the present invention;
[0020] Figure 4 This is a schematic diagram of the frequency-divided clock signal after phase adjustment in an embodiment of the present invention;
[0021] Figure 5 This is a schematic diagram illustrating the phase relationship between the pre-synchronization reference signal and the local synchronization reference signal in an embodiment of the present invention;
[0022] Figure 6 This is a schematic diagram illustrating the phase relationship between the synchronized reference signal and the local synchronized reference signal in an embodiment of the present invention. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0024] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0025] This invention provides a synchronization circuit based on clock phase adjustment, such as... Figure 1 As shown, the synchronization circuit includes: a clock divider circuit 10, a phase detection circuit 11, a phase adjustment circuit 12, and a synchronizer circuit 13. The clock divider circuit 10 generates a divided clock signal from the input system clock. The phase detection circuit 11, connected to the clock divider circuit 10, obtains a phase offset value based on the input synchronization reference signal and the divided clock signal. The phase adjustment circuit 12, connected to both the clock divider circuit 10 and the phase detection circuit 11, adjusts the phase of the input divided clock signal based on the phase offset value to obtain a phase-adjusted divided clock signal. The synchronizer circuit 13, connected to the phase adjustment circuit 12, obtains a local synchronization reference signal based on the phase-adjusted divided clock signal and the synchronization reference signal, ensuring no loss of clock sampling edges and improving sampling accuracy and precision. This can be applied to integrated circuits with high sampling accuracy requirements.
[0026] Specifically, such as Figure 2 As shown, the clock divider circuit 10 divides the system clock system_clk to obtain the required n-divided clock signals clk_div1, clk_div2, ..., clk_divn, where n = 2. N N is an integer, corresponding to a total of N+1 frequency-divided clock signals, where the i-th frequency-divided clock signal is 2. i-1Frequency-divided clock signals, i = 1, 2, ..., N+1. Taking a 4-divided clock signal as an example, the clock divider circuit 10 outputs three divided clock signals: clk_div1 (divided by 1), clk_div2 (divided by 2), and clk_div4 (divided by 4). The phase relationship between the three is as follows: Figure 3 As shown in the figure. The 1-division clock clk_div1 is the same as the system clock system_clk.
[0027] Phase detection circuit 11 detects the phase relationship between the synchronization reference signal sysref and the frequency-divided clock signals clk_div1, clk_div2, ..., clk_divn, and obtains a phase offset value M of n bits based on the phase relationship. n is the number of frequency-divided clocks. The phase offset value M characterizes the phase difference between the synchronization reference signal sysref and the frequency-divided clocks. Taking a 4-divided clock as an example, the clock frequency divider circuit 10 generates three frequency-divided clocks clk_div1, clk_div2, and clk_div4. The phase relationship between the synchronization reference signal sysref and the frequency-divided clocks is as follows: Figure 3 As shown, the phase detection circuit 11 obtains an n-bit phase offset value M, where n = 3, based on the relationship between the synchronization reference signal sysref and the frequency divider clock.
[0028] In this embodiment of the invention, the phase detection circuit 11 also acquires the phase offset value multiple times, using half a system clock cycle (system_clk) as the unit, and performs an arithmetic average of the multiple acquisition results to obtain the final phase offset value. That is, the final phase offset value Ma = (M1 + M2 + ... + Mm) / m, where Mi is the phase offset value of the i-th acquisition, and m is the total number of data acquisitions.
[0029] In this embodiment of the invention, the phase adjustment circuit 12 offsets the phase of the input clock divider signal by the phase offset value M, obtaining the phase-adjusted divider clock signals clk_div1_adjusted, clk_div2_adjusted, ..., clk_divn_adjusted, synchronized with the synchronization reference signal. Specifically, the phase adjustment circuit 12 adjusts the phase of the input clock divider signal by half a cycle of the system clock, from 0 to 2... N -1.5 cycles of 2 N By switching between phases, the frequency-divided clock signal after phase adjustment is obtained and synchronized with the synchronization reference signal.
[0030] like Figure 4As shown, taking a 4-division clock as an example, phase adjustment can switch between eight phases: 0, 1, 2, 3, 4, 5, 6, and 7. Here, 111 indicates that the divided clock signals clk_div1, clk_div2, and clk_div4 are all 1, with a corresponding phase offset value M of 0, requiring no adjustment; 011 indicates a phase offset value M of 1; 101 indicates a phase offset value M of 2; 001 indicates a phase offset value M of 1; 110 indicates a phase offset value M of 4; 010 indicates a phase offset value M of 5; 100 indicates a phase offset value M of 6; and 000 indicates a phase offset value M of 7. The phase adjustment circuit 12 adjusts the clock divided signals according to the phase offset value M at the synchronization point to obtain the phase-adjusted divided clock signals clk_div1_adjusted, clk_div2_adjusted, and clk_div4_adjusted, synchronized with the synchronization reference signal.
[0031] Synchronizer circuit 13 obtains a local synchronization reference signal based on the phase-adjusted frequency-divided clock signal and the synchronization reference signal. Synchronizer circuit 13 obtains a local synchronization reference signal sync based on the phase-adjusted frequency-divided clock signals clk_div1_adjusted, clk_div2_adjusted, ..., clk_divn_adjusted and the synchronization reference signal sysref.
[0032] Taking a 4-division clock as an example, the 1-division clock clk_div1 is divided to obtain two clocks clk_div2 and clk_div4. These three clocks form an input clock combination: clk_div1 (1-division), clk_div2 (2-division), and clk_div4 (4-division). In the phase detection circuit 11, the synchronization reference signal sysref simultaneously samples this clock combination to obtain a 3-bit phase offset value M. Assuming this 3-bit sampled data is 110, the rising edge of the synchronization reference signal sysref is within half a clk_div1 clock cycle of phase 4. According to... Figure 2 Similarly, it can be seen that the frequency divider clock clk_div4 and sysref are 4 phases apart. By delaying clk_div4 by 4 phases in unit3, the phase synchronization between clk_div4 and sysref can be achieved, thereby realizing multi-chip synchronization based on sysref.
[0033] In this embodiment of the invention, the synchronizer circuit 13 also tracks the phase relationship between the adjusted frequency divider clock phase and the reference signal sysref in real time, determines whether a phase shift has occurred based on the phase relationship between the adjusted frequency divider clock signal and the synchronization reference signal, and returns a set of control words CTRL to the phase adjustment circuit 12 based on the phase shift situation.
[0034] If the phase relationship between the frequency-divided clock signal and the synchronization reference signal shifts, the phase adjustment circuit 12 further adjusts the phase of the frequency-divided clock signal according to the control word and the phase shift value to resynchronize the phase. If the frequency-divided clock signal and the synchronization reference signal are in phase, i.e., no shift has occurred,
[0035] The synchronizer circuit 13 then outputs a local synchronization reference signal sync, which keeps the synchronization reference signal sysref and the frequency divider clock synchronized.
[0036] For an example simulation using a 4-division clock, see [link to simulation]. Figure 5 and Figure 6 ,in, Figure 5 The phase relationship between the pre-synchronization reference signal sysref and the local synchronization reference signal sync is given. Figure 6 The figure shows the phase relationship between the synchronization reference signal `sysref` and the local synchronization reference signal `sync` output by synchronizer circuit 13 after phase synchronization. `clk_div4_sync` is the 4-division clock after synchronization. Points A and B are the two points that need to be synchronized. Before synchronization, point A is at 120.98949ns and 426.41562mV, and point B is at 121.80301ns and 615.7426mV. After synchronization, point A is at 370.9899ns and 505.26389mV, and point B is at 371.01563ns and 515.77296mV. After synchronization, the x-axis difference is 25.723328ps, and the y-axis difference is 10.509mV, which improves the synchronization accuracy. As can be seen from the figure, the sampling edge of the clock is not lost, which can be applied to integrated circuits with high sampling accuracy requirements.
[0037] The synchronization circuit based on clock phase adjustment in this embodiment of the invention includes: a clock divider circuit for generating a divided clock signal from an input system clock; a phase detection circuit connected to the clock divider circuit for obtaining a phase offset value based on an input synchronization reference signal and the divided clock signal; a phase adjustment circuit connected to the clock divider circuit and the phase detection circuit for adjusting the phase of the input divided clock signal based on the phase offset value to obtain a phase-adjusted divided clock signal; and a synchronizer circuit connected to the phase adjustment circuit for obtaining a local synchronization reference signal based on the phase-adjusted divided clock signal and the synchronization reference signal. This circuit can adjust the clock phase quickly and in real time according to the phase relationship between the reference signal and the divided clock, without losing the clock sampling edge, and can be applied to integrated circuits with high sampling accuracy requirements.
[0038] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of this application as described above, which are not provided in detail for the sake of brevity.
[0039] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the embodiments of this invention. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this invention should be included within the protection scope of this application.
Claims
1. A clock phase adjustment based synchronization circuit, characterized in that, The synchronization circuit includes: A clock divider circuit is used to generate a divided clock signal from the input system clock. A phase detection circuit, connected to the clock divider circuit, is used to obtain a phase offset value based on the input synchronization reference signal and the divided clock signal; A phase adjustment circuit, connected to the clock divider circuit and the phase detection circuit, is used to adjust the phase of the input divided clock signal according to the phase offset value to obtain the phase-adjusted divided clock signal. A synchronizer circuit, connected to the phase adjustment circuit, is used to obtain a local synchronization reference signal based on the phase-adjusted frequency-divided clock signal and the synchronization reference signal. The phase adjustment circuit adjusts the phase by half a cycle of the system clock based on the phase offset value, from 0 to... Half-cycle Switching between phases, the frequency-divided clock signal with phase adjustment is obtained and synchronized with the synchronization reference signal; The synchronizer circuit also determines whether a phase shift has occurred based on the phase relationship between the adjusted frequency-divided clock signal and the synchronization reference signal, and returns a set of control words to the phase adjustment circuit based on the phase shift situation.
2. The synchronization circuit of claim 1, wherein, The clock divider circuit divides the system clock to obtain the required n-divided clock signal. N is an integer.
3. The synchronization circuit of claim 2, wherein, The clock frequency dividing circuit divides the system clock to obtain N+1 frequency-divided clock signals, wherein the i-th frequency-divided clock signal is the frequency-divided clock signal, i=1, 2, …, N+1.
4. The synchronization circuit as described in claim 3, characterized in that, The phase detection circuit detects the phase relationship between the synchronization reference signal and the frequency division clock signal, and obtains the n-bit phase offset value based on the phase relationship.
5. The synchronization circuit of claim 4, wherein, The phase detection circuit acquires the phase offset value multiple times in half a system clock cycle, and performs an arithmetic average of the multiple acquisition results to obtain the final phase offset value.
6. The synchronization circuit as described in claim 3, characterized in that, The phase adjustment circuit shifts the phase of the input clock division signal by the phase shift value to obtain the phase-adjusted clock signal that is synchronized with the synchronization reference signal.
7. The synchronization circuit of claim 1, wherein, The synchronizer circuit samples the synchronization reference signal according to the phase-adjusted frequency-divided clock signal to obtain the local synchronization reference signal.
8. The synchronization circuit of claim 1, wherein, The phase adjustment circuit further adjusts the phase of the frequency division clock signal according to the control word and the phase offset value in order to resynchronize the phase.