Bit error rate measurement device and bit error rate measurement method

Abstract

The present invention provides a bit error rate measuring device, which detects bit errors of input data returned and received from a test object accompanying the sending of a test signal through an error detector, and comprises: a log recording unit, which records log data of state transitions of each channel based on signal exchange under a prescribed communication standard between the test object and the test object when the test object is transitioned to a LOOPBACK state; and a display unit, which displays the recorded log data of the state transitions of each channel in a time series.

Description

Technical Field

[0001] The present invention relates to a bit error rate measurement device and a bit error rate measurement method, which transmit a known waveform as a test signal to a device under test while causing the device under test to transition to a state where a signal waveform returns, and measure the bit error rate of input data returned and received from the device under test accompanying the transmission of the test signal. Background Art

[0002] In the past, for example, as disclosed in the following patent document 1, a bit error rate measurement device is known that includes a device that sends a test signal of a known waveform containing fixed data to a device under test, compares the measured signal returned and received from the device under test along with the sending of the test signal with a reference signal serving as a benchmark in bit units, and measures the bit error rate (BER: Bit Error Rate).

[0003] Furthermore, for example, as disclosed in the following patent document 2, as such a bit error rate measurement device, there is known a device having the function of recording log data including a transition destination of the link state, a time when the transition occurs, a trigger of the transition, and error information each time a link state transition occurs in a link state management mechanism.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2007-274474

[0005] Patent Document 2: Japanese Patent Application Publication No. 2017-098615

[0006] However, the following method is usually adopted, that is, when testing a receiver as a test object under the standards of a high-speed serial bus such as PCIe (Peripheral Component Interconnect Express) and USB (Universal Serial Bus), after executing signal exchange to transition the receiver to a test-specific signal return mode (LOOPBACK), a known waveform for testing is input and the bit error rate of the returned signal is confirmed.

[0007] Furthermore, in the test of a high-speed serial bus, if there is a function capable of outputting the log data of the signal exchange to a bit error rate measurement device, it is useful for debugging and can clarify in which state of the signal exchange a failure occurs.

[0008] Furthermore, the USB3.2 standard released in recent years newly stipulates a x2 mode for communicating in dual channels. In the signal exchange in this dual channel mode, it is necessary to exchange signals in each channel 0 and channel 1. At this time, for example, the standard defines that even if the state transition condition for entering the next state is satisfied in channel 1 (channel 0), channel 1 (channel 0) will not transition to the next state until channel 0 (channel 1) satisfies the state transition condition.

[0009] However, the bit error rate measurement device disclosed in the above-mentioned patent document 2 is limited to the function of displaying the timeline of state transition, and cannot simultaneously record the log data of state transition based on signal exchange of multiple channels. In addition, it is not possible to display in the log whether the state transition conditions between multiple channels are satisfied. Therefore, in the conventional bit error rate measurement device, there is a problem that it is difficult to analyze the failure cause in the signal exchange of multiple channels. Summary of the invention

[0010] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a bit error rate measurement device and a bit error rate measurement method capable of simultaneously recording or displaying log data of state transitions based on signal exchange of multiple channels.

[0011] In order to achieve the above-mentioned object, the bit error rate measurement device of scheme 1 of the present invention comprises: a waveform generator 2, which transmits a test signal of a known waveform to the object under test W in a state where the object under test W is transitioned to a state where the signal waveform under a prescribed communication standard is returned; and an error detector 3, which detects a bit error of input data returned and received from the object under test accompanying the transmission of the test signal. The bit error rate measurement device 1 is characterized in that the prescribed communication standard is a standard for communication in a plurality of channels, and the bit error rate measurement device 1 comprises:

[0012] The log recording unit 19 records log data of the state transition of each channel when the object under test is transitioned to the state in which the signal waveform returns.

[0013] The bit error rate measurement device according to solution 2 of the present invention is characterized in that, in the bit error rate measurement device of solution 1,

[0014] The log data includes log data indicating a state in which the autonomous channel satisfies a state transition condition for entering a next state and waits for other channels to satisfy the state transition condition.

[0015] The bit error rate measurement device according to solution 3 of the present invention is characterized in that, in the bit error rate measurement device of solution 1 or 2, it comprises:

[0016] The display unit 21 displays the log data of the state transition of each channel recorded in the log recording unit 19 in a time series.

[0017] The bit error rate measurement device according to solution 4 of the present invention is characterized in that in any one of the bit error rate measurement devices of solutions 1 to 3,

[0018] The communication standard is a high-speed serial bus communication standard.

[0019] In the bit error rate measurement method of the bit error rate measurement device described in scheme 5 of the present invention: the bit error rate measurement device comprises: a waveform generator 2, which sends a test signal of a known waveform to the object under test W while causing the object under test W to transition to a state in which a signal waveform under a prescribed communication standard is returned; and an error detector 3, which detects bit errors in input data returned and received from the object under test accompanying the sending of the test signal, wherein the prescribed communication standard is a standard for communication in multiple channels, and the bit error rate measurement method of the bit error rate measurement device is characterized in that it comprises the following steps:

[0020] The log recording unit 19 provided in the error detector records log data of the state transition of each channel when the object under test is transitioned to the state in which the signal waveform returns.

[0021] The bit error rate measurement method described in scheme 6 of the present invention is characterized in that, in the bit error rate measurement method of scheme 5,

[0022] The log data includes log data indicating a state in which the autonomous channel satisfies a state transition condition for entering a next state and waits for other channels to satisfy the state transition condition.

[0023] The bit error rate measurement method described in scheme 7 of the present invention is characterized in that, in the bit error rate measurement method of scheme 5 or 6, it includes the following steps:

[0024] The log data of the state transition of each channel recorded in the log recording unit 19 is displayed on the display unit 21 in a time series.

[0025] The bit error rate measurement method described in scheme 8 of the present invention is characterized in that in any one of the bit error rate measurement methods in schemes 5 to 7,

[0026] The communication standard is a high-speed serial bus communication standard.

[0027] Effects of the Invention

[0028] According to the present invention, the log data of the state transition based on the signal handshake of multiple channels can be recorded or displayed at the same time. When the standards of multiple channels are tested, the user can easily determine in which channel and in which state the cause of the signal handshake failure occurs. As a result, the user can determine in which state and in which channel there is a problem, so the HSB device can be debugged very effectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a block diagram of the bit error rate measurement device involved in the present invention.

[0030] Figure 2 The flowchart shows a method of performing signal exchange in a dual-channel mode between the bit error rate measurement device and a device under test and displaying a log.

[0031] Figure 3 This is a diagram showing an example of a transition pattern when the bit error rate measurement device according to the present invention successfully exchanges signals with the object under test in a dual-channel mode.

[0032] Figure 4 This is a diagram showing a display example of a log when signal exchange is successful in channel 0 of the bit error rate measurement device according to the present invention.

[0033] Figure 5 This is a diagram showing a display example of a log when signal exchange is successful in channel 1 of the bit error rate measurement device according to the present invention.

[0034] Figure 6 This is a diagram showing a display example of a log when a handshake fails in channel 0 of the bit error rate measurement device according to the present invention.

[0035] Figure 7 This is a diagram showing a display example of a log when a handshake fails in channel 1 of the bit error rate measurement device according to the present invention. DETAILED DESCRIPTION

[0036] Hereinafter, a mode for carrying out the present invention will be described in detail with reference to the drawings.

[0037] The present invention relates to a bit error rate measurement device and a bit error rate measurement method, in which a device equipped with a link training state machine (LTSSM: Link Training & Status State Machine) as a link state management mechanism for managing link states is set as a device under test, and when the device under test is transitioned to a measurement mode in which a signal waveform returns (LOOPBACK), a test signal of a known waveform is sent to the device under test, and the bit error rate of input data returned and received from the device under test accompanying the transmission of the test signal is measured. In addition, the LTSSM exists in the physical layer and transitions by observing the signal received by the physical layer.

[0038] like Figure 1 As shown, the bit error rate measurement device 1 of the present embodiment is roughly constructed to include a waveform generator 2 and an error detector 3, and has the following functions, namely, it is equipped with a sequence for transitioning the link state of the LTSSM of the object under test W to the LOOPBACK (loopback) state, and before a measurement mode in which a known waveform signal is input to the object under test W and the bit error rate is measured, for multiple channels of a specified communication standard (such as PCIe, USB, etc. HSB), the log data of the state transition of each channel based on signal exchange (including the log data of the state of waiting for other channels to meet the state transition conditions) is simultaneously recorded and displayed.

[0039] In addition, the following description will be given by taking as an example a case where the communication is in accordance with the USB 3.2 standard which stipulates a dual channel mode in which communication is performed in channel 0 and channel 1.

[0040] The object under test W is equipped with LTSSM (Wa) for managing the link status of channel 0 and LTSSM (Wb) for managing the link status of channel 1. During the signal exchange training mode in the dual-channel mode before measuring the bit error rate, it is connected to the bit error rate measurement device 1 via a test fixture not shown in the figure, and the transmission of the LFPS (Low Frequency Periodic Signaling) signal is started when the connection is detected.

[0041] The waveform generator 2 generates a waveform to be transmitted to the object under test W, and includes a first waveform generating section 11 and a second waveform generating section 12 .

[0042] The first waveform generating unit 11 is arranged to correspond to channel 0, and in a training mode for transitioning the LTSSM (Wa) of the object W to be measured to a LOOPBACK state, generates a training waveform signal of channel 0 based on LTSSM16a through the control of the control unit 22 described later.

[0043] When the first waveform generating unit 11 is in the measurement mode of the jitter tolerance test of the object under test W in the state where the object under test W is transitioning to the LOOPBACK state, a waveform signal of channel 0 of a known waveform input to the object under test W is generated under the control of the control unit 22 described later (composed of a pseudo-random binary sequence of "0", "1" based on the NRZ signal, a CP (Compliance pattern: test code type) of the waveform specified by the standard).

[0044] The second waveform generating unit 12 is arranged to correspond to channel 1, and in a training mode for transitioning the LTSSM (Wb) of the object W under test to a LOOPBACK state, generates a training waveform signal of channel 1 based on LTSSM17a under the control of a control unit 22 described later.

[0045] When the second waveform generating unit 12 is in the measurement mode of the object W, it generates a waveform signal of channel 1 of a known waveform input to the object W (CP of a waveform defined by the same standard as the waveform signal of channel 0) under the control of the control unit 22 described later.

[0046] The error detector 3 detects a waveform signal sent from the object under test W, and includes a first waveform detection unit 13, a second waveform detection unit 14, an error detection unit 15, a first link state management unit 16, a second link state management unit 17, a time generation unit 18, a log recording unit 19, a storage unit 20, a display unit 21 and a control unit 22.

[0047] The first waveform detection unit 13 is configured to correspond to channel 0. In the training mode, the training waveform signal of channel 0 sent from the object under test W is detected according to the transition of the state of the LTSSM (Wa) of the object under test W in accordance with the signal exchange based on the training waveform signal of channel 0 sent from the first waveform generating unit 11 of the waveform generator 2.

[0048] In the measurement mode, when the waveform signal of channel 0 generated by the first waveform generating unit 11 of the waveform generator 2 is input to the object W under test, the first waveform detecting unit 13 detects the waveform signal of channel 0 returned from the object W under test and input accordingly.

[0049] The second waveform detection unit 14 is configured to correspond to channel 1, and in training mode, detects the training waveform signal of channel 1 sent from the object under test W based on the transition of the state of the LTSSM (Wb) of the object under test W according to the signal exchange based on the training waveform signal of channel 1 sent from the second waveform generating unit 12 of the waveform generator 2.

[0050] When the waveform signal of channel 1 generated by the second waveform generating section 12 of the waveform generator 2 is input to the object W under test, the second waveform detecting section 14 detects the waveform signal of channel 1 returned from the object W under test and input in the measurement mode.

[0051] When the error detection unit 15 is in the measurement mode in which the object under test W is transitioning to the LOOPBACK state, the error detection unit 15 compares the test signals of known waveforms generated by the first waveform generating unit 11 and the second waveform generating unit 12 of the waveform generator 2, i.e., the waveform signals of channel 0 and channel 1, with the waveform signals of channel 0 and channel 1 returned from the object under test W along with the transmission of the waveform signals of channel 0 and channel 1 and detected by the first waveform detection unit 13 and the second waveform detection unit 14, to detect bit errors.

[0052] The first link state management unit 16 has an LTSSM 16a having the same or equivalent mechanism as the LTSSM (Wa) mounted on the object under test W, and operates according to the standard of the I / O interface used (USB3.2 in this example). At this time, the following state is defined, that is, even if the state transition condition for entering the next state is satisfied in channel 0 but before channel 1 satisfies the state transition condition, the state transition condition is not made to transition to the next state, waiting for other channels to satisfy the state transition condition. For example, when the state transition condition from POLLING_ACTIVE to POLLING_CONFIGURATION is defined as "receiving normal TS1OS or TS2OS 8 times in a row", when both channel 0 and channel 1 meet the state transition condition, it is possible to enter the next state. And, when the transition condition from POLLING_CONFIGURATION to POLLING_IDLE is defined as "receiving normal TS2OS 8 times in a row and receiving TS2 16 times", when both channel 0 and channel 1 meet the state transition condition, it is possible to enter the next state.

[0053] The first link state management unit 16 transitions the link state of channel 0 in the same manner as the LTSSM (Wa) of the device W based on the signal communicated with the device W, and can identify the current link state of the LTSSM (Wa) in the device W. Thus, various information such as the LTSSM value, link speed, presence or absence of loopback, transition waveform of LTSSM, channel number for identifying the channel, link number, occurrence time or number of occurrences of the waveform signal, emphasis, and adjustment value of the equalizer on the receiving side can be obtained for channel 0.

[0054] The second link state management unit 17 includes an LTSSM 17a having the same or equivalent mechanism as the LTSSM (Wb) mounted on the device under test W, and operates in accordance with the standard of the I / O interface used (USB 3.2 in this example) in the same manner as the first link state management unit 16. At this time, a state is defined in which, in the same manner as the first link state management unit 16, even if the state transition condition for entering the next state is satisfied in channel 1 but before channel 0 satisfies the state transition condition, the state transition condition is not made to make channel 1 transit to the next state until the other channels satisfy the state transition condition.

[0055] The second link state management unit 17, like the first link state management unit 16, transitions the link state of the channel 1 in the same manner as the LTSSM (Wb) of the device W based on the signal communicated with the device W, and can recognize the current link state of the LTSSM (Wa) in the device W. Thus, various information similar to that of the first link state management unit 16 can be obtained with respect to the channel 1.

[0056] Furthermore, the first link state management unit 16 and the second link state management unit 17 recognize the link states of the other party's channels and exchange various information corresponding to the link states.

[0057] The time generating unit 18 generates the current time, and outputs the generated time information to the log recording unit 18 .

[0058] The log recording unit 19 records, based on the moment information generated by the moment generating unit 18, the log information of each channel including the LTSSM value or link speed of channel 0 and channel 1 managed by the first link status management unit 16 and the second link status management unit 17 through the signal exchange in the dual-channel mode in USB3.2, which is a communication standard for making the LTSSM (Wa, Wb) of the object under test W transition to the LOOPBACK state, and the log information of the measurement result including the bit error rate detected by the error detection unit 15 in the measurement mode.

[0059] In addition, as log information recorded in the log recording unit 19 during the transition of LTSSM16a, 17a, there are, for example, LTSSM value, link speed, presence or absence of loopback, LTSSM transition waveform, channel number, link number, occurrence time or number of occurrences of the waveform signal, emphasis, and adjustment value of the equalizer on the receiving side.

[0060] The storage unit 20 stores the log information recorded by the log recording unit 19 under the control of the control unit 22. For example, the transition destination of the link state, the occurrence time of the transition, the trigger of the transition, the error information, etc. are stored in the storage unit 20 as log information for each channel (channel 0, channel 1) according to the transition of the LTSSM 16a and 17a.

[0061] The display unit 21 is controlled by the control unit 22 to Figures 4 to 7 The display mode shown displays the log information recorded by the log recording unit 19 or the log information stored in the storage unit 20 on the display screen 21a. In addition, the display unit 21 displays a setting screen related to the bit error rate measurement or a measurement result including error information detected by the error detection unit 15 and recorded in the log recording unit 19, etc., under the control of the control unit 22 based on the operation of the operating unit (not shown).

[0062] The control unit 22 centrally controls the components of the waveform generator 2 and the error detector 3 when performing signal exchange with the object under test W in the dual channel mode or measuring a bit error rate.

[0063] Specifically, in the training mode, the control unit 22 instructs the first waveform generating unit 11 and the second waveform generating unit 12 to generate the training waveform signals of channel 0 and channel 1 to be generated next according to the current link states of LTSSM16a of the first link state management unit 16 and LTSSM17a of the second link state management unit 17.

[0064] Furthermore, in the measurement mode, the control unit 22 instructs the first waveform generating unit 11 and the second waveform generating unit 12 to generate waveform signals of channel 0 and channel 1 .

[0065] The control unit 22 controls writing of the log information recorded in the log recording unit 19 to the storage unit 20 or reading of the log information stored in the storage unit 20 , and controls display of the log information on the display screen 21 a of the display unit 21 .

[0066] Next, refer to Figure 2 The flowchart of FIG. 1 illustrates a method of performing signal exchange in a dual-channel mode between the bit error rate measurement device 1 configured as above and the object under test W and displaying log data.

[0067] Since the interface of the signal output section of the bit error rate measurement device 1 is different from the interface of the signal receiving section of the device under test W, the bit error rate measurement device 1 and the device under test W are connected via a test fixture used for conversion to make the interfaces consistent ( Figure 2 ST1).

[0068] If the object under test W detects the connection between the test fixture and the bit error rate measurement device 1, the transmission of the LFPS signal as a training waveform signal begins ( Figure 2 ST2).

[0069] The bit error rate measurement device 1 transitions to the POLLING_LFPS state by receiving the LFPS signal transmitted from the object under test W as a trigger, and starts transmitting the LFPS signal as a training waveform signal ( Figure 2 ST3).

[0070] The object under test W transitions to the next state by receiving the LFPS signal sent from the bit error rate measurement device 1, and sends a training waveform signal corresponding to the next state ( Figure 2 ST4).

[0071] Then, the object under test W and the bit error rate measurement device 1 exchange signals in the dual-channel mode, and the training waveform signals defined in each state are sent to each other in channel 0 and channel 1 to transition the state. The LTSSM (Wa, Wb) of the object under test W finally transitions to the LOOPBACK_ACTIVE state ( Figure 2 ST5).

[0072] Specifically, when the dual-channel signal exchange between the bit error rate measurement device 1 and the object under test W is successful, Figure 3 As shown, the object under test W transmits the waveform defined in each state (the waveform associated with the state in 1:1) in the order of LFPS SCD1 / SCD2→LBPM CAP / RDY→END OFLBPM→TSEQ→TS1→TS2→LOOPBACK to perform state transition. Figure 3 As shown, the bit error rate measurement device 1 transmits a waveform defined in each state as the state of the object under test W transitions to perform state transition.

[0073] Then, when the two-channel signal exchange between the object under test W and the bit error rate measurement device 1 transitions to the LOOPBACK_ACTIVE state, the bit error rate measurement device 1 displays the log data of the state transition of its own channel 0 and channel 1 on the display screen 21a of the display unit 21 ( Figure 2 ST6).

[0074] Specifically, when the signal exchange of the dual-channel mode based on channel 0 and channel 1 of the bit error rate measurement device 1 is successful, Figure 4 and Figure 5 The display method shown displays the state transition log data of each channel 0 and channel 1 in a time series configuration on the display screen 21a. At this time, in addition to the state transition log data, the display screen 21a also displays the state log data indicating that the autonomous channel meets the state transition condition and waits for other channels to meet the state transition condition ( Figure 4 "POLLING_CONFIGURATION(Waiting for other lane)" surrounded by slashes, Figure 5 The POLLING_ACTIVE(Waiting for other lane) and POLLING_IDLE(Waiting for otherlane) are surrounded by slashes.

[0075] according to Figure 4 and Figure 5 The log data of the state transition first uses the signal exchange of channel 0 based on the low-speed signal, and the state transitions in the order of INITIAL→DETECT_ACTIVE→POLLING_LFPS_SCD1→POLLING_LFPS_PLUS→POLLING_LFPS_ENDSCD→POLLING_PORT_MATCH→POLLING_PORT_CONFIG_READY→POLLING_PORT_ENDLBPM.

[0076] Next, the signal exchange between channel 0 and channel 1 is performed using high-speed signals, and after channel 0 transitions to the POLLING_RXEQ state, channel 1 transitions to the POLLING_RXEQ state. Then, after channel 1 transitions to the POLLING_ACTIVE state, channel 0 transitions to the POLLING_ACTIVE state.

[0077] Then, if the signal handshake in POLLING_ACTIVE of channel 1 is completed, it waits until the signal handshake in POLLING_ACTIVE of channel 0 is completed. Then, if the signal handshake in POLLING_ACTIVE of channel 0 is completed, after channel 1 transitions to the POLLING_CONFIGURATION state, channel 0 transitions to the POLLING_CONFIGURATION state.

[0078] Then, if the signal handshake in POLLING_CONFIGURATION of channel 0 is completed, wait until the signal handshake in POLLING_CONFIGURATION of channel 1 is completed.

[0079] Then, if the signal exchange in POLLING_CONFIGURATION of channel 1 is completed, channel 0 and channel 1 transition to the POLLING_IDLE state. Next, after the signal exchange in POLLING_IDLE of channel 1 is completed, wait until the signal exchange in POLLING_IDLE of channel 0 is completed. Then, if the signal exchange in POLLING_IDLE of channel 0 is completed, channel 0 and channel 1 transition to the LOOPBACK_ACTIVE state, and the signal exchange in dual-channel mode is successful.

[0080] In contrast, when the signal exchange in the dual-channel mode based on channel 0 and channel 1 of the bit error rate measurement device 1 fails, Figure 6 and Figure 7 The display method shown displays the state transition log data of each channel 0 and channel 1 in a time series configuration on the display screen 21a. At this time, in addition to the state transition log data, the display screen 21a also displays the state log data indicating that the autonomous channel meets the state transition condition and waits for other channels to meet the state transition condition ( Figure 7 The POLLING_ACTIVE (Waiting for other lane) surrounded by slashes).

[0081] according to Figure 6 and Figure 7 The log data of the state transition, with Figure 4 Similarly, first, through the signal exchange of channel 0 based on the low-speed signal, the state transitions in the order of INITIAL→DETECT_ACTIVE→POLLING_LFPS_SCD1→POLLING_LFPS_PLUS→POLLING_LFPS_ENDSCD→POLLING_PORT_MATCH→POLLING_PORT_CONFIG_READY→POLLING_PORT_ENDLBPM.

[0082] Then, the signal exchange between channel 0 and channel 1 is performed by the high-speed signal, and after channel 0 transitions to the POLLING_RXEQ state, channel 1 transitions to the POLLING_RXEQ state. Then, after channel 1 transitions to the POLLING_ACTIVE state, channel 0 transitions to the POLLING_ACTIVE state.

[0083] Then, after the signal handshake in POLLING_ACTIVE of channel 1 is completed, the signal handshake in POLLING_ACTIVE of channel 0 is waited until the signal handshake in POLLING_ACTIVE of channel 0 is completed. Then, the signal handshake in POLLING_ACTIVE of channel 0 is timed out before the signal handshake in POLLING_ACTIVE of channel 0 is completed and the state transitions to INITIAL, and the dual-channel signal handshake ends in failure.

[0084] In addition, Figures 4 to 7 In , Time[ns] indicates the elapsed time, Delta Time indicates the retention time of the state, State indicates the name of the state, and Speed[GT / s] indicates the signal name or speed. Figures 4 to 7 The diagram shows the state transition log data of channel 0 and channel 1 respectively. Figure 4 and Figure 5 The log data of the state transition of channel 0 and channel 1 when the dual-channel signal exchange is successful is displayed together in a time series on a display screen 21a of the display unit 21. Figure 6 and Figure 7 The log data of the state transition of channel 0 and channel 1 when the two-channel signal exchange fails is displayed together in time series on one display screen 21 a of the display unit 21 .

[0085] Thus, according to this embodiment, the function of simultaneously recording the log data of signal exchanges of multiple channels in the prescribed communication standard (PCIe, USB, etc. HSB), and at the same time displaying the recorded log data of state transition. In addition, the function of defining the state of waiting for other channels to meet the state transition condition (the state in which the autonomous channel meets the state transition condition for entering the next state and waits for other channels to meet the state transition condition) and displaying the log data including the state of waiting for the other channels to meet the state transition condition, in addition to the log data of the state transition of each channel.

[0086] Thus, when testing the standards of multiple channels, the user can easily identify in which channel and in which state the cause of the handshake failure occurs. As a result, the user can identify in which channel the problem occurs in a certain state (for example, the problem occurs in a channel other than the long-waiting channel according to the state), thereby enabling very efficient debugging of HSB devices.

[0087] The above describes the preferred embodiments of the bit error rate measurement device and the bit error rate measurement method according to the present invention, but the present invention is not limited to the description and drawings based on the embodiments. That is, it is obvious that other embodiments, examples, and application technologies implemented by those skilled in the art according to the embodiments are all included in the scope of the present invention.

[0088] Explanation of symbols

[0089] 1-bit error rate measuring device, 2-waveform generator, 11-first waveform generating unit, 12-second waveform generating unit, 3-error detector, 13-first waveform detecting unit, 14-second waveform detecting unit, 15-error detecting unit, 16-first link status management unit, 16a-LTSSM, 17-second link status management unit, 17a-LTSSM, 18-time generating unit, 19-log recording unit, 20-storage unit, 21-display unit, 21a-display screen, 22-control unit, W-object under test, Wa, Wb-LTSSM.

Claims

1. A bit error rate measurement device (1), comprising: A waveform generator (2) sends a test signal of a known waveform to the object under test (W) when the object under test (W) is in a signal waveform return mode under a prescribed communication standard; and An error detector (3) detects bit errors in input data returned and received from the object under test accompanying the transmission of the test signal, wherein the bit error rate measurement device (1) is characterized in that: The prescribed communication standard is a standard for communication in a plurality of channels, and the bit error rate measurement device (1) comprises: A log recording unit (19) records log data of the state transition of each channel when the object under test is transitioned to the state in which the signal waveform returns, wherein when one channel satisfies a state transition condition for entering a next state and waits to enter the next state before another channel satisfies the state transition condition, the log recording unit (19) records the waiting state of the one channel, and The object under test (W) and the bit error rate measurement device (1) include the same link training state machine.

2. The bit error rate measurement device according to claim 1, It is characterized in that have: The display unit (21) displays the log data of the state transition of each channel recorded in the log recording unit (19) in a time series.

3. The bit error rate measurement device according to claim 1 or 2, It is characterized in that The communication standard is a high-speed serial bus communication standard.

4. A bit error rate measurement method of a bit error rate measurement device, the bit error rate measurement device comprising: A waveform generator (2) sends a test signal of a known waveform to the object under test (W) when the object under test (W) is in a signal waveform return mode under a prescribed communication standard; and an error detector (3) for detecting bit errors in input data received and returned from the device under test in response to the transmission of the test signal, The specified communication standard is a standard for communicating in multiple channels, and the bit error rate measurement method is characterized by comprising the following steps: A log recording unit (19) provided in the error detector records log data of state transition of each channel when the object under test is transitioned to a state where the signal waveform returns. The steps of recording log data include: When one channel satisfies a state transition condition for entering a next state and waits to enter the next state before another channel satisfies the state transition condition, recording data indicating the waiting state of the one channel, and The object under test (W) and the bit error rate measurement device (1) include the same link training state machine.

5. The bit error rate measurement method according to claim 4, It is characterized in that The steps include: The log data of the state transition of each channel recorded in the log recording unit (19) is displayed on the display unit (21) in a time series.

6. The bit error rate measurement method according to claim 4 or 5, It is characterized in that The communication standard is a high-speed serial bus communication standard.

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