Resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage

Abstract

The present invention provides a silicon-controlled rectifier structure with high holding voltage and low trigger voltage, comprising a P-type substrate, on which adjacent N-wells and P-wells are formed; a first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, a second shallow trench isolation is provided on the N-well, and a first N-type ion implantation layer and a first P-type ion implantation layer are sequentially formed from the first shallow trench isolation to the N-well between the second shallow trench isolation; a first connection structure is provided on the first N-type ion implantation layer for leading out an anode; a second P-type ion implantation layer is formed across the junction of the N-well and the P-type substrate on the P-type substrate, and a gate is formed on the N-well between the second shallow trench isolation and the second P-type ion implantation layer. The present invention can adjust the trigger voltage by changing the value of RC; has a higher holding voltage, and adjusts the holding voltage by changing the width of the transition region; has higher latch-up resistance.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a resistor-capacitor coupled silicon-controlled rectifier structure with high holding voltage and low trigger voltage. Background Art

[0002] With the development of integrated circuits, the operating voltage is getting lower and lower, and the ability of on-chip ESD (low capacitance electrostatic) protection is increasingly difficult to meet the demand, and the risk of latch-up is gradually increasing. With the continuous reduction of manufacturing processes, the thickness of the gate oxide layer of transistors is getting thinner and thinner, and the gate oxide breakdown voltage and operating voltage are constantly decreasing. In addition, the rate of decrease of the chip operating voltage is lower than the rate of decrease of the gate oxide breakdown voltage and the source-drain breakdown voltage of the transistor. Therefore, when performing ESD design, a 10% safety margin must be considered, resulting in the ESD design window becoming narrower and narrower, and the selectable ESD solutions are extremely limited. Silicon-controlled rectifiers (SCRs) are the most robust ESD protection devices per unit area, and can be regarded as a positive feedback loop composed of two parasitic transistors PNP and NPN. Its IV (current-voltage) characteristics show obvious hysteresis characteristics, and the holding voltage is often very low, which is very easy to cause latch-up effects.

[0003] GGNMOS (grounded NMOS tube) uses the junction breakdown voltage of N-type implanted ions and P-well to trigger, and has a relatively low trigger voltage. Studies have shown that embedding GGNMOS into SCR can effectively reduce the trigger voltage, and this new structure is named low trigger voltage silicon controlled rectifier (LVTSCR). GGNMOS accelerates the triggering process of LVTSCR, but the strong hysteresis of SCR causes the maintenance voltage of LVTSCR to be still very low, facing a high risk of latch-up. Therefore, by introducing an N-type or P-type crossover region at the contact between the N-well and P-well junctions, the modified lateral silicon controlled rectifier (MLSCR) formed can also reduce the trigger voltage of SCR. In addition, the crossover region in MLSCR provides an ESD shunt path, which can reduce the ESD current of the parasitic SCR path in the body, thereby increasing the maintenance voltage of MLSCR, but the trigger voltage of MLSCR may be higher than the breakdown voltage of gate oxide under low voltage operation, which is still not enough to protect the internal circuit from failure.

[0004] In order to solve the above problems, a new type of silicon-controlled rectifier structure with adjustable low trigger voltage and high holding voltage is needed. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a resistor-capacitor coupled silicon-controlled rectifier structure with high holding voltage and low trigger voltage, which is used to solve the problem that the low-capacitance electrostatic design window in the prior art is becoming narrower and narrower, and the selectable low-capacitance electrostatic solutions are extremely limited; the current-voltage characteristics of the silicon-controlled rectifier show obvious hysteresis characteristics, and the holding voltage is often very low, which is very likely to cause the latch effect problem.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a resistor-capacitor coupled silicon-controlled rectifier structure with high holding voltage and low trigger voltage, comprising:

[0007] A P-type substrate having an N-well and a P-well adjacent to each other formed thereon;

[0008] A first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, a second shallow trench isolation is provided on the N-well, and a first N-type ion implantation layer and a first P-type ion implantation layer arranged at intervals are sequentially formed on the N-well from the first shallow trench isolation to the second shallow trench isolation;

[0009] A first connection structure is provided on the first N-type ion implantation layer for extracting the anode;

[0010] A second P-type ion implantation layer is formed on the P-type substrate, spanning the boundary between the N-well and the P-type substrate, and a gate is formed on the N-well isolated from the second shallow trench to the second P-type ion implantation layer;

[0011] A second connection structure for electrically connecting the gate and the second P-type ion implantation layer is formed;

[0012] A fifth shallow trench isolation is provided at the junction of the P-well and the P-type substrate, and a third shallow trench isolation, a second N-type ion implantation layer, a fourth shallow trench isolation, and a third P-type ion implantation layer are sequentially provided on the P-well from the second P-type ion implantation layer to the fifth shallow trench isolation;

[0013] A third connection structure for connecting the second N-type ion implantation layer and the third P-type ion implantation layer is provided on the second N-type ion implantation layer and the third P-type ion implantation layer, and is used for leading out a cathode.

[0014] Preferably, the P-type substrate is a silicon substrate.

[0015] Preferably, the second P-type ion implantation layer is located in an area equal to that of the N-well and the P-well.

[0016] Preferably, the ions doped in the N-well are boron ions.

[0017] Preferably, the ions doped in the N-well are boron ions.

[0018] Preferably, the ions doped in the N-well are boron ions.

[0019] Preferably, the ions doped in the first N-type ion implantation layer and the second N-type ion implantation layer are both arsenic ions.

[0020] Preferably, the ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

[0021] Preferably, the gate is made of doped polysilicon.

[0022] As described above, the resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage of the present invention has the following beneficial effects:

[0023] Due to the coupling effect of the well resistance Rp and the gate capacitance C, the trigger voltage of the structure of the present invention is lower, and the trigger voltage can be adjusted by changing the value of RC; since the P-type ion implantation layer of the anode is floating, it is equivalent to a reverse-biased diode connected in series, and the current needs to turn on the reverse-biased diode to turn on the silicon-controlled rectifier path, so it has a higher holding voltage, and the holding voltage can be adjusted by changing the width of the transition zone; the lower trigger voltage and higher holding voltage make the new structure have higher latch resistance; the original layout area is not changed, and it has certain process compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of the structure of a silicon-controlled rectifier of the present invention;

[0025] Figure 2 Shown is a schematic diagram of the parasitic circuit of the silicon-controlled rectifier structure of the present invention.

[0026] Reference numerals:

[0027] P-type substrate-01

[0028] N-well-02

[0029] P-well-03

[0030] First shallow trench isolation-04

[0031] Second shallow trench isolation-05

[0032] The third shallow trench isolation-06

[0033] Fourth Shallow Trench Isolation-07

[0034] Fifth Shallow Trench Isolation-08

[0035] The first N-type ion implantation layer-09

[0036] The first P-type ion implantation layer-10

[0037] Gate-11

[0038] The second P-type ion implantation layer-12

[0039] The second N-type ion implantation layer-13

[0040] The third P-type ion implantation layer-14

[0041] First connection structure-15

[0042] Second connection structure-16

[0043] Third connection structure-17 DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figure 1 The present invention provides a resistor-capacitor coupled silicon-controlled rectifier structure with high holding voltage and low trigger voltage, comprising:

[0046] A P-type substrate 01, on which adjacent N-well 02 and P-well 03 are formed;

[0047] A first shallow trench isolation 04 is provided at the junction of the N-well 02 and the P-type substrate 01, a second shallow trench isolation 05 is provided on the N-well 02, and a first N-type ion implantation layer 09 and a first P-type ion implantation layer 10 are sequentially formed in the N-well 02 between the first shallow trench isolation 04 and the second shallow trench isolation 05;

[0048] In an embodiment of the present invention, the P-type substrate 01 is a silicon substrate, and an N-well 02 and a P-well 03 can be first formed on the silicon substrate by ion implantation, and then a groove for forming a shallow trench isolation (STI) is formed on the substrate by photolithography and etching, and then an insulating material is deposited and polished in the groove to form a shallow trench isolation structure.

[0049] A first connection structure 15 is provided on the first N-type ion implantation layer 09 for extracting the anode;

[0050] In the embodiment of the present invention, after the device is manufactured by the front-end process, the devices are interconnected by the back-end process to form the first connection structure 15. Specifically, an interlayer dielectric layer can be deposited on the device after the ion implantation by chemical vapor deposition, and the material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole connected to the first N-type ion implantation layer 09, and then the contact hole is filled with a conductive material, and the filling material can be tungsten (W), and the interconnection can be Al.

[0051] A second P-type ion implantation layer 12 is formed on the P-type substrate 01, spanning the boundary between the N-well 02 and the P-type substrate 01. A gate 11 is formed on the N-well 02 between the second shallow trench isolation 05 and the second P-type ion implantation layer 12.

[0052] A second connection structure 16 for electrically connecting the gate 11 and the second P-type ion implantation layer 12 is formed;

[0053] In the embodiment of the present invention, after the device is manufactured by the front-end process, the devices are interconnected by the back-end process to form the second connection structure 16. Specifically, an interlayer dielectric layer can be deposited on the device after the ion implantation by chemical vapor deposition, and the material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole communicating with the gate 11 and the second P-type ion implantation layer 12, and then the contact hole is filled with a conductive material, and the filling material can be tungsten (W), and the interconnection can be Al.

[0054] In the embodiment of the present invention, the second P-type ion implantation layer 12 is located in the N-well 02 and the P-well 03 with the same area.

[0055] A fifth shallow trench isolation 08 is provided at the junction of the P-type well 03 and the P-type substrate 01, and a third shallow trench isolation 06, a second N-type ion implantation layer 13, a fourth shallow trench isolation 07, and a third P-type ion implantation layer 14 are provided in sequence in the P-type well 03 from the second P-type ion implantation layer 12 to the fifth shallow trench isolation 08;

[0056] A third connection structure 17 for connecting the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14 is provided on the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14 to lead out a cathode.

[0057] In the embodiment of the present invention, after the device is manufactured by the front-end process, the devices are interconnected by the back-end process to form the third connection structure 17. Specifically, an interlayer dielectric layer can be deposited on the device after the ion implantation by chemical vapor deposition, and the material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole connected to the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14, and then the contact hole is filled with a conductive material, and the filling material can be tungsten (W), and the interconnection can be Al.

[0058] See also Figure 2 That is to say, the embodiment of the present invention embeds the RC circuit composed of the well resistor Rp and the gate capacitor C into the LVTSCR structure. The values ​​of the well resistor Rp and the gate capacitor C are mainly determined by the doping concentration of the P well and the thickness of the local field oxide; the P-type ion implantation layer of the anode is in a floating state, and the gate is connected to the P-type ion implantation layer across the gate through a metal interconnect, which is equivalent to generating a P-well resistor. Due to the RC coupling effect, the trigger voltage of the new structure is reduced; the floating P-type ion implantation layer of the anode is equivalent to introducing a reverse-biased PIN (diode) junction, which will result in more hole-electron pairs being required to maintain the opening of the reverse PIN junction. The holding voltage can be controlled by adjusting the width value of the transition zone in the PIN junction.

[0059] In an embodiment of the present invention, the ions doped in the N-well 02 are boron ions.

[0060] In an embodiment of the present invention, the ions doped in the N-well 02 are boron ions.

[0061] In an embodiment of the present invention, the ions doped in the N-well 02 are boron ions.

[0062] In the embodiment of the present invention, the ions doped in the first N-type ion implantation layer 09 and the second N-type ion implantation layer 13 are both arsenic ions.

[0063] In the embodiment of the present invention, the ions doped in the first P-type ion implantation layer 10 , the second P-type ion implantation layer 12 , and the third P-type ion implantation layer 14 are all boron ions.

[0064] In the embodiment of the present invention, the material of the gate 11 is doped polysilicon.

[0065] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0066] In summary, due to the coupling effect of the well resistance Rp and the gate capacitance C, the trigger voltage of the structure of the present invention is lower, and the trigger voltage can be adjusted by changing the value of RC; because the P-type ion implantation layer of the anode is floating, it is equivalent to a reverse-biased diode in series, and the current needs to turn on the reverse-biased diode to turn on the silicon-controlled rectifier path, so it has a higher holding voltage, and the holding voltage can be adjusted by changing the width of the transition zone; the lower trigger voltage and higher holding voltage make the new structure have higher latch resistance; the original layout area is not changed, and it has certain process compatibility. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage, characterized in that: include: A P-type substrate having an N-well and a P-well adjacent to each other formed thereon; A first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, a second shallow trench isolation is provided on the N-well, and a first N-type ion implantation layer and a first P-type ion implantation layer arranged at intervals are sequentially formed on the N-well from the first shallow trench isolation to the second shallow trench isolation; A first connection structure is provided on the first N-type ion implantation layer for extracting the anode; A second P-type ion implantation layer is formed on the P-type substrate, spanning the boundary between the N-well and the P-type substrate, and a gate is formed on the N-well isolated from the second shallow trench to the second P-type ion implantation layer; A second connection structure for electrically connecting the gate and the second P-type ion implantation layer is formed; A fifth shallow trench isolation is provided at the junction of the P-well and the P-type substrate, and a third shallow trench isolation, a second N-type ion implantation layer, a fourth shallow trench isolation, and a third P-type ion implantation layer are sequentially provided on the P-well from the second P-type ion implantation layer to the fifth shallow trench isolation; A third connection structure for connecting the second N-type ion implantation layer and the third P-type ion implantation layer is provided on the second N-type ion implantation layer and the third P-type ion implantation layer, and is used to lead out a cathode; An RC circuit consisting of a well resistor Rp and a gate capacitor C is embedded in the structure, wherein the values ​​of the well resistor Rp and the gate capacitor C are determined by the doping concentration of the P well and the thickness of the local field oxide; the P-type ion implantation layer of the anode is in a floating state, and the gate is connected to the P-type ion implantation layer across it through a metal interconnect, which is equivalent to generating a well resistor Rp.

2. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The P-type substrate is a silicon substrate.

3. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The second P-type ion implantation layer is located in an area equal to that of the N-well and the P-well.

4. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The ions doped in the N-well are boron ions.

5. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The ions doped in the P-well are phosphorus ions.

6. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The ions doped in the first N-type ion implantation layer and the second N-type ion implantation layer are both arsenic ions.

7. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

8. The resistor-capacitor coupled silicon controlled rectifier structure with high holding voltage and low trigger voltage according to claim 1, characterized in that: The gate is made of doped polysilicon.

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