Digital signal output circuit and digital signal output device

Abstract

The application provides a digital signal output circuit and a digital signal output device, and belongs to the technical field of digital circuits. The digital signal output circuit comprises a digital gating delay module, an inverting module and an output module; the input end of the digital gating delay module is connected with a clock signal and an input signal; the output end of the digital gating delay module is connected with the input end of the inverting module; the digital gating delay module is used for selecting the clock signal and sampling the input signal according to the selected clock signal, and sending a delay signal obtained by sampling to the inverting module; the output end of the inverting module is connected with the input end of the output module; the inverting module is used for generating a control signal for the output module based on the delay signal; and the output module is used for generating and outputting a digital signal with a jump time meeting a preset requirement according to the control signal. The application can keep the output digital signal in a preset range.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, and more specifically, to a digital signal output circuit and a digital signal output device. Background Technology

[0002] In digital circuits, in order to meet the actual signal output requirements, a digital signal output circuit is usually set up to output digital signals. The jump time of the output digital signal is usually within a preset range.

[0003] In existing technologies, a transmitting circuit is typically used to generate an inverted control signal, which in turn controls the generation of digital signals.

[0004] However, if other loads are added to the circuit due to actual working reasons, the magnitude of the inverted control signal generated by the transmitting circuit may be affected, which in turn affects the jump time of the output digital signal. For example, it may exceed the preset range, resulting in the obtained digital signal not meeting the actual requirements. Summary of the Invention

[0005] The purpose of this application is to provide a digital signal output circuit and a digital signal output device that can keep the output digital signal within a preset range.

[0006] The embodiments of this application are implemented as follows:

[0007] One aspect of this application provides a digital signal output circuit, including: a digital gating delay module, an inverting module, and an output module;

[0008] The input terminal of the digital strobe delay module is connected to the clock signal and the input signal. The output terminal of the digital strobe delay module is connected to the input terminal of the inverting module. The digital strobe delay module is used to select the input clock signal, sample the input signal according to the selected clock signal, and send the sampled delay signal to the inverting module.

[0009] The output terminal of the inverting module is connected to the input terminal of the output module. The inverting module is used to generate control signals for the output module based on the delayed signal.

[0010] The output module is used to generate and output digital signals with jump times that meet preset requirements based on the control signals.

[0011] Optionally, the digital gating delay module includes: a gating device and a trigger;

[0012] The selector's input terminal is connected to a clock signal, its control terminal is connected to a selection signal, and its output terminal is connected to the second input terminal of a flip-flop. The selector is used to select the clock signal through the selection signal to obtain the target clock signal, and then send the target clock signal to the flip-flop.

[0013] The first input terminal of the flip-flop is connected to the input signal, and the output terminal of the flip-flop is connected to the input terminal of the inverting module. The flip-flop is used to sample the input signal according to the target clock signal and obtain a delay signal, and then send the delay signal to the inverting module.

[0014] Optionally, the inverting module includes: a first inverter, a second inverter, a first switching transistor, a second switching transistor, a first output terminal, and a second output terminal;

[0015] The input terminal of the first inverter is connected to the output terminal of the digital gating delay module, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the control terminal of the first inverter is connected to the second terminal of the first switching transistor.

[0016] The input terminal of the second inverter is also connected to the second output terminal, the output terminal of the second inverter is connected to the first output terminal, and the control terminal of the second inverter is connected to the second terminal of the second switching transistor.

[0017] The first terminal of the first switch and the first terminal of the second switch are respectively connected to the first power supply terminal, and the third terminal of the first switch is connected to the third terminal of the second switch.

[0018] Optionally, the output module includes: a first resistor, a second resistor, a first switch, a second switch, a load capacitor, and a digital signal output terminal;

[0019] The first end of the first resistor is connected to the second power supply end, and the second end of the first resistor is connected to the first end of the first switch.

[0020] The first end of the second resistor is grounded, and the second end of the second resistor is connected to the second end of the second switch.

[0021] The second end of the first resistor, the first end of the second resistor, the first end of the load capacitor, and the digital signal output terminal are respectively connected, and the second end of the load capacitor is grounded.

[0022] The control terminal of the first switch is connected to the first output terminal of the inverting module, and the control terminal of the second switch is connected to the second output terminal of the inverting module.

[0023] Optionally, at the same time, the first switch and the second switch are in different on / off states.

[0024] Optionally, the digital signal output circuit may further include: a delay clock generation module;

[0025] The input terminal of the delayed clock generation module is connected to the initial clock signal, and the output terminal of the delayed clock generation module is connected to the input terminal of the digital strobe delay module. The delayed clock generation module is used to perform delay processing on the initial clock signal and generate a clock signal with delay.

[0026] Optionally, the delayed clock generation module includes: multiple delay units connected in series;

[0027] Each delay unit is used to output clock signals with different delays.

[0028] Optionally, the delay unit includes: multiple delay units and multiple delay control switches;

[0029] Each delay unit is connected in series, and each delay unit corresponds to a delay control switch. The first end of each delay control switch is connected to the input end of the delay unit, and the second end of each delay control switch is connected to the output end of the corresponding delay unit.

[0030] In another aspect of the embodiments of this application, a digital signal output device is provided, which includes a plurality of digital signal output circuits and an output determination unit;

[0031] The digital signal output circuits are connected in parallel to each other, and the output terminals of each digital signal output circuit are connected to the output determination unit.

[0032] The output determination unit is used to determine the jump time of the digital signal output by each digital signal output circuit according to the required parameters of each digital signal output circuit.

[0033] Optionally, the required parameters include: the capacitance of the load capacitor, the resistance of the first resistor, and the delay of the clock signal.

[0034] The beneficial effects of the embodiments of this application include:

[0035] In the digital signal output circuit and digital signal output device provided in this application embodiment, the input clock signal can be selected by a digital gating delay module, and the input signal is sampled according to the selected clock signal. The sampled delay signal is sent to the inverting module, which generates a control signal for the output module based on the delay signal. This causes the output module to generate and output a digital signal with a jump time that meets preset requirements according to the control signal. The digital gating delay module allows for the selection of the clock signal, thereby adjusting the sampling of the input signal and adjusting the delay signal. Based on the delay signal, a corresponding control signal and a digital signal that meets the requirements can be obtained. Since the selection of the clock signal is controllable, the obtained delay signal is a delay signal that meets the requirements. Therefore, both the control signal and the digital signal obtained can meet the preset requirements; that is, the obtained digital signal can be kept within a preset range. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the overall structure of the digital signal output circuit provided in the embodiments of this application;

[0038] Figure 2 A schematic diagram of the structure of the digital gating delay module of the digital signal output circuit provided in the embodiments of this application;

[0039] Figure 3 This is a schematic diagram of the structure of the inverting module of the digital signal output circuit provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of the structure of the output module of the digital signal output circuit provided in the embodiments of this application;

[0041] Figure 5 A schematic diagram of the delay clock generation module of the digital signal output circuit provided in the embodiments of this application;

[0042] Figure 6 This is a schematic diagram of the delay unit of the digital signal output circuit provided in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the structure of the digital signal output device provided in the embodiments of this application.

[0044] Icons: 10 - Digital signal output circuit; 20 - Output determination unit; 100 - Digital gating delay module; 110 - Gating device; 120 - Trigger; 200 - Inverting module; 300 - Output module; 400 - Delay clock generation module; 410 - Delay unit; V1 - First inverter; V2 - Second inverter; V3 - Delay unit; M1 - First switch; M2 - Second switch; O1 - First output terminal; O2 - Second output terminal; O3 - Digital signal output terminal; VDD1 - First power supply terminal; VDD2 - Second power supply terminal; S1 - First switch; S2 - Second switch; S3 - Delay control switch; R1 - First resistor; R2 - Second resistor; C - Load capacitor. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0048] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0049] In existing technologies, a transmitting circuit is typically used to generate an inverted control signal, which in turn controls the generation of digital signals.

[0050] The input to the transmitting circuit is a fixed input signal. Therefore, if other loads are added to the circuit during actual operation, the magnitude of the inverted control signal generated by the transmitting circuit may be affected, which in turn affects the jump time of the output digital signal.

[0051] To address the aforementioned problems in the prior art, this application provides a digital signal output circuit, the specific structure and connection relationships of which will be explained in detail below.

[0052] Figure 1 Please refer to the overall structural diagram of the digital signal output circuit provided in the embodiments of this application. Figure 1 The digital signal output circuit includes: a digital gating delay module 100, an inverting module 200, and an output module 300;

[0053] The input terminal of the digital strobe delay module 100 is connected to a clock signal and an input signal. The output terminal of the digital strobe delay module 100 is connected to the input terminal of the inverting module 200. The digital strobe delay module 100 is used to select the input clock signal, sample the input signal according to the selected clock signal, and send the sampled delayed signal to the inverting module.

[0054] Optionally, the digital strobe delay module 100 can be a module that adjusts the input signal to obtain a delay signal by selecting a clock, or it can be a module composed of multiple pre-configured integrated circuits.

[0055] The output terminal of the inverting module 200 is connected to the input terminal of the output module 300. The inverting module 200 is used to generate a control signal for the output module 300 based on the delay signal.

[0056] The inverting module 200 can be a circuit that implements inversion. After obtaining the delayed signal, the control signal can be obtained by inverting the delayed signal. Furthermore, the inverting module 200 can have two different output terminals for outputting different control signals.

[0057] The output module 300 is used to generate and output a digital signal with a jump time that meets preset requirements based on the control signal.

[0058] The output module 300 can specifically be an output circuit, which may include two switches. The control signal output by the inverting module 200 controls the corresponding switches to generate the output control signal.

[0059] The working principle of the above digital signal output circuit will be explained in detail below:

[0060] First, the digital strobe delay module 100 selects one of the clock signals to sample the input signal, thereby obtaining a delay signal. Then, the digital strobe delay module 100 sends the delay signal to the inverting module 200, which converts the delay signal into a control signal and controls the output module 300 based on the control signal, so that the output module 300 generates a digital signal based on the control signal.

[0061] In a digital signal output circuit provided in this application embodiment, a digital gating delay module can select the input clock signal and sample the input signal according to the selected clock signal. The sampled delayed signal is then sent to an inverting module, which generates a control signal for the output module based on the delayed signal. This causes the output module to generate and output a digital signal with a jump time that meets preset requirements. The digital gating delay module allows for the selection of the clock signal, thereby adjusting the sampling of the input signal and thus adjusting the delayed signal. Based on the delayed signal, a corresponding control signal and a digital signal that meets the requirements can be obtained. Since the selection of the clock signal is controllable, the obtained delayed signal is a delayed signal that meets the requirements. Therefore, both the control signal and the digital signal obtained can meet the preset requirements; that is, the obtained digital signal can be kept within a preset range.

[0062] The following section will explain the specific structure and connection relationship of the digital gating delay module of the digital signal output circuit.

[0063] Figure 2 Please refer to the schematic diagram of the digital gating delay module of the digital signal output circuit provided in the embodiments of this application. Figure 2 The digital gating delay module 100 includes: a gating device 110 and a trigger 120;

[0064] The input terminal of the selector 110 is connected to a clock signal, the control terminal of the selector 110 is connected to a selection signal, and the output terminal of the selector 110 is connected to the second input terminal of the flip-flop. The selector 110 is used to select the clock signal through the selection signal to obtain the target clock signal and send the target clock signal to the flip-flop. The first input terminal of the flip-flop 120 is connected to an input signal, and the output terminal of the flip-flop 120 is connected to the input terminal of the inverting module 200. The flip-flop 120 is used to sample the input signal according to the target clock signal and obtain a delay signal, and send the delay signal to the inverting module 200.

[0065] Optionally, the selector 110 can receive multiple input clock signals, such as 12 different clock signals. The control terminal of the selector 110 can select the clock signal through the input selection signal. Specifically, the selection signal can be a multi-bit digital signal. Different values ​​are used to select different clock signals. Finally, the selector 110 outputs the selected target clock signal to the flip-flop 120.

[0066] Optionally, the flip-flop 120 can be a D-type flip-flop. The input signal connected to the first input terminal of the flip-flop 120 can be sampled according to the target clock signal to obtain the corresponding delay signal. The delay signal can be sent to the inverting module 200 through the output terminal of the flip-flop 120.

[0067] For example, if there are 12 clock signals, and the selector 110 can select 8 clock signals, then the corresponding selection signal can be to select from these 8 clock signals. Different clock signals can have different delays. For example, the first clock signal is delayed by one cycle and the second clock signal is delayed by two cycles. When the first clock signal is used as the target clock signal, the resulting delayed signal is also a signal delayed by one delay cycle. Correspondingly, when the second clock signal is used as the target clock signal, the resulting delayed signal is also a signal delayed by two delay cycles.

[0068] The following section will explain the specific structure and connection relationship of the inverting module of this digital signal output circuit.

[0069] Figure 3 Please refer to the schematic diagram of the inverting module of the digital signal output circuit provided in the embodiment of this application. Figure 3 The inverter module 200 includes: a first inverter V1, a second inverter V2, a first switch M1, a second switch M2, a first output terminal O1, and a second output terminal O2.

[0070] The input terminal of the first inverter V1 is connected to the output terminal of the digital gating delay module 100, the output terminal of the first inverter V1 is connected to the input terminal of the second inverter V2, and the control terminal of the first inverter V1 is connected to the second terminal of the first switch M1. The input terminal of the second inverter V2 is also connected to the second output terminal O2, the output terminal of the second inverter V2 is connected to the first output terminal O1, and the control terminal of the second inverter V2 is connected to the second terminal of the second switch M2. The first terminal of the first switch M1 and the first terminal of the second switch M2 are respectively connected to the first power supply terminal VDD1, and the third terminal of the first switch M1 is connected to the third terminal of the second switch M2.

[0071] It should be noted that the current of the inverter can be controlled by the first switch M1 and the second switch M2. Specifically, the first switch M1 controls the current of the first inverter V1, and the second switch M2 controls the current of the second inverter V2. By controlling the current, the rise time of the inverter edge can be controlled, thereby obtaining the corresponding output.

[0072] Optionally, the first switch M1 and the second switch M2 can be NMOS transistors or PMOS transistors, and can be set according to the actual circuit structure, without specific restrictions here; the first inverter V1 and the second inverter V2 can be inverted according to the electrical signal input during operation. For example, when the aforementioned delay signal is input, the delay signal can be inverted.

[0073] The first output terminal O1 and the second output terminal O2 can be two ports with completely opposite output control signals. The control signal can also be a digital signal used to control the switch. For example, when the control signal is 1, the switch is closed, and when the control signal is 0, the switch is opened.

[0074] The following section will explain the specific structure and connection relationship of the output module of this digital signal output circuit.

[0075] Figure 4 Please refer to the schematic diagram of the output module of the digital signal output circuit provided in the embodiments of this application. Figure 4 The output module 300 includes: a first resistor R1, a second resistor R2, a first switch S1, a second switch S2, a load capacitor C, and a digital signal output terminal O3.

[0076] The first end of the first resistor R1 is connected to the second power supply terminal VDD2, and the second end of the first resistor R1 is connected to the first end of the first switch S1; the first end of the second resistor R2 is grounded, and the second end of the second resistor R2 is connected to the second end of the second switch S2; the second end of the first resistor R1, the first end of the second resistor R2, the first end of the load capacitor C, and the digital signal output terminal O3 are respectively connected, and the second end of the load capacitor C is grounded; the control terminal of the first switch S1 is connected to the first output terminal O1 of the inverting module 200, and the control terminal of the second switch S2 is connected to the second output terminal O2 of the inverting module 200.

[0077] Optionally, at the same time, the first switch S1 and the second switch S2 are in different open / closed states.

[0078] It should be noted that in state 1, when the first switch S1 is closed and the second switch S2 is open, the equivalent circuit is as follows: the first end of the first resistor R1 is connected to the second power supply terminal VDD2, the second end of the first resistor R1 is connected to the first end of the load capacitor C and the digital signal output terminal O3 respectively; the second end of the load capacitor C is grounded.

[0079] State 2: When the first switch S1 is open and the second switch S2 is closed, the equivalent circuit is as follows: the first end of the second resistor R2 is grounded, and the second end of the second resistor R2 is connected to the first end of the load capacitor C and the digital signal output terminal O3 respectively; the second end of the load capacitor C is grounded.

[0080] During operation, the high and low levels of the output digital signal can be generated by switching between state 1 and state 2.

[0081] The following section will explain the specific structure and connection relationship of the delay clock generation module of the digital signal output circuit.

[0082] Figure 5 For a schematic diagram of the delay clock generation module of the digital signal output circuit provided in this application embodiment, please refer to... Figure 5 The digital signal output circuit also includes: a delay clock generation module 400; the input terminal of the delay clock generation module 400 is connected to the initial clock signal, and the output terminal of the delay clock generation module 400 is connected to the input terminal of the digital strobe delay module 100. The delay clock generation module 400 is used to perform delay processing on the initial clock signal and generate a clock signal with delay.

[0083] Optionally, the delayed clock generation module 400 includes: a plurality of delay units 410 connected in series; each delay unit 410 is used to output clock signals with different delays.

[0084] Each delay unit 410 can delay the clock by one cycle to obtain different clock signals. A corresponding number of clock signals can be obtained by setting a corresponding number of delay units 410.

[0085] For example, if there are 12 clock delay units 410, a clock signal can be obtained after each delay of the initial clock signal, and thus 12 clock signals can be obtained in this way.

[0086] The following section will explain the specific structure and connection relationship of the delay unit of this digital signal output circuit.

[0087] Figure 6 Please refer to the schematic diagram of the delay unit of the digital signal output circuit provided in the embodiment of this application. Figure 6The delay unit 410 includes: multiple delay units V3 and multiple delay control switches S3; each delay unit V3 is connected in series, each delay unit V3 corresponds to a delay control switch S3, the first end of each delay control switch S3 is connected to the input end of the delay unit 410, and the second end of each delay control switch S3 is connected to the output end of the corresponding delay unit V3.

[0088] Optionally, a controllable delay clock circuit can be obtained by generating clock signals with different delay times for the on / off control of multiple delay control switches S3. Since the clock delay is controllable, the subsequently obtained delay signal, control signal, and final output digital signal are all controllable signals, and the obtained digital signal can be kept within a preset range.

[0089] The signal controlling each delay control switch S3 can also be a multi-digit digital signal. Different values ​​control different numbers of delay control switches S3 to open or close, thereby realizing the control of the delay clock.

[0090] The above method allows for the determination of digital signal output using digital circuits, thus avoiding the energy consumption caused by analog circuits and saving energy consumed during circuit operation.

[0091] The specific structure and connection relationships of this digital signal output device will be explained in detail below.

[0092] Figure 7 Please refer to the schematic diagram of the digital signal output device provided in the embodiments of this application. Figure 7 The digital signal output device includes multiple digital signal output circuits 10 and an output determination unit 20; the digital signal output circuits 10 are connected in parallel with each other, and the output terminal of each digital signal output circuit 10 is connected to the output determination unit 20; the output determination unit 20 is used to determine the jump time of the digital signal output by each digital signal output circuit 10 according to the required parameters of each digital signal output circuit 10.

[0093] Optionally, the required parameters include: the capacitance of the load capacitor, the resistance of the first resistor, and the delay of the clock signal.

[0094] The jump time refers to the time it takes for the output digital signal to jump from a high level to a low level or from a low level to a high level. The output determination unit 20 can specifically be a processor with processing capabilities, capable of calculating the output waveform based on relevant parameters in the circuit.

[0095] It should be noted that the output module 300 in the digital signal output circuit 10 may include a charging state and a discharging state. It should also be noted that in this embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2 are equal. Therefore, in the charging state, the second power supply terminal VDD2 charges the load capacitor through the first resistor R1, and in the discharging state, ground discharges to the load capacitor C through the second capacitor R2. Since R1 = R2, the resistance value will be represented by R1 in subsequent calculations. The charging and discharging times can be expressed as V(t) = Vdd2 × (1 - e^(-t / t)). -t / ta ), where ta=R1×C.

[0096] If there are eight digital signal output circuits 10, and the clock signal delays corresponding to different digital signal output circuits 10 are 1 cycle, 2 cycles, 3 cycles, 4 cycles, 5 cycles, 6 cycles, 7 cycles, and 8 cycles respectively, then the following calculation formula can be used as the expression formula for the output digital signal:

[0097]

[0098] Where 1.1 can be the value of VDD2, e is the natural constant, ta is the product of R1 and C mentioned above, t is time, ft is the number of periods, and delta1-delta7 corresponds to the displacement length.

[0099] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A digital signal output circuit, characterized in that, include: Digital strobe delay module, inverting module, and output module; The input terminal of the digital strobe delay module is connected to a clock signal and an input signal. The output terminal of the digital strobe delay module is connected to the input terminal of the inverting module. The digital strobe delay module is used to select the input clock signal, sample the input signal according to the selected clock signal, and send the sampled delay signal to the inverting module. The output terminal of the inverting module is connected to the input terminal of the output module, and the inverting module is used to generate a control signal for the output module based on the delay signal; The output module is used to generate and output a digital signal whose jump time meets preset requirements according to the control signal; The digital gating delay module includes: a gating device and a trigger; The input terminal of the selector is connected to the clock signal, the control terminal of the selector is connected to the selection signal, and the output terminal of the selector is connected to the second input terminal of the flip-flop. The selector is used to select the clock signal through the selection signal to obtain a target clock signal, and send the target clock signal to the flip-flop. The first input terminal of the flip-flop is connected to the input signal, and the output terminal of the flip-flop is connected to the input terminal of the inverting module. The flip-flop is used to sample the input signal according to the target clock signal and obtain a delay signal, and send the delay signal to the inverting module.

2. The digital signal output circuit as described in claim 1, characterized in that, The inverter module includes: a first inverter, a second inverter, a first switching transistor, a second switching transistor, a first output terminal, and a second output terminal; The input terminal of the first inverter is connected to the output terminal of the digital gating delay module, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the control terminal of the first inverter is connected to the second terminal of the first switching transistor. The input terminal of the second inverter is also connected to the second output terminal, the output terminal of the second inverter is connected to the first output terminal, and the control terminal of the second inverter is connected to the second terminal of the second switching transistor. The first end of the first switch and the first end of the second switch are respectively connected to the first power supply terminal, and the third end of the first switch is connected to the third end of the second switch.

3. The digital signal output circuit as described in claim 2, characterized in that, The output module includes: a first resistor, a second resistor, a first switch, a second switch, a load capacitor, and a digital signal output terminal; The first end of the first resistor is connected to the second power supply end, and the second end of the first resistor is connected to the first end of the first switch; The first end of the second resistor is grounded, and the second end of the second resistor is connected to the second end of the second switch; The second end of the first resistor, the first end of the second resistor, the first end of the load capacitor, and the digital signal output terminal are respectively connected, and the second end of the load capacitor is grounded; The control terminal of the first switch is connected to the first output terminal of the inverter module, and the control terminal of the second switch is connected to the second output terminal of the inverter module.

4. The digital signal output circuit as described in claim 3, characterized in that, At the same time, the first switch and the second switch are in different on / off states.

5. The digital signal output circuit as described in claim 1, characterized in that, The digital signal output circuit further includes: a delay clock generation module; The input terminal of the delayed clock generation module is connected to the initial clock signal, and the output terminal of the delayed clock generation module is connected to the input terminal of the digital strobe delay module. The delayed clock generation module is used to perform delay processing on the initial clock signal and generate a clock signal with delay.

6. The digital signal output circuit as described in claim 5, characterized in that, The delayed clock generation module includes: multiple delay units connected in series; Each delay unit is used to output clock signals with different delays.

7. The digital signal output circuit as described in claim 6, characterized in that, The delay unit includes: multiple delay units and multiple delay control switches; Each of the delay units is connected in series, and each delay unit corresponds to a delay control switch. The first end of each delay control switch is connected to the input end of the delay unit, and the second end of each delay control switch is connected to the output end of the corresponding delay unit.

8. A digital signal output device, characterized in that, The digital signal output device includes a plurality of digital signal output circuits as described in any one of claims 1-7 and an output determination unit; Each of the digital signal output circuits is connected in parallel with each other, and the output terminal of each of the digital signal output circuits is connected to the output determining unit. The output determination unit is used to determine the jump time of the digital signal output by each digital signal output circuit according to the required parameters of each digital signal output circuit.

9. The digital signal output device as described in claim 8, characterized in that, The required parameters include: the capacitance of the load capacitor, the resistance of the first resistor, and the delay of the clock signal.

Images