Memory storage devices and storage systems

Abstract

The application relates to a memory storage device and a storage system, which comprises a host connection interface, a memory module, a memory controller, an LED driving circuit and a memory interface, the memory controller comprises a memory control circuit, the memory control circuit is connected with the memory module through the memory interface, the LED driving circuit is connected with the memory control circuit and an LED display screen respectively, the memory control circuit receives a control instruction sent by an external host, reads a logical-to-physical mapping table from the memory module, and counts the value of a logical address in the logical-to-physical mapping table, the memory control circuit generates a corresponding level control signal according to the statistical value corresponding to the value of the logical address and sends the level control signal to the LED driving circuit, and the LED driving circuit drives a corresponding area in the LED display screen to emit light display according to the corresponding level control signal, and the memory storage device greatly improves the capacity visualization effect in the use process.

Description

Technical Field

[0001] This application relates to the field of memory, specifically to a memory storage device and a storage system. Background Technology

[0002] With the widespread application of NAND Flash in the memory field, more and more electronic products and memory devices are using NAND Flash as a storage medium, such as USB flash drives, memory cards, SSDs, etc. It has advantages such as vibration resistance, low power consumption and long-term storage.

[0003] However, currently, when using NAND flash products, the only way to check the used capacity is through the connected computer. It is impossible to directly know the capacity usage of the NAND flash product from its appearance, resulting in extremely poor visualization. Summary of the Invention

[0004] In view of this, this application provides a memory storage device and a storage system that enables the user to directly see the used capacity and remaining available capacity of the memory storage device from its appearance during use, greatly improving the capacity visualization effect during the use of the memory storage device.

[0005] A memory storage device, wherein an LED display screen is disposed on the outer surface of the memory storage device, the memory storage device comprising:

[0006] Host connection interface, used for coupling with external host;

[0007] Memory module;

[0008] The memory controller includes a memory control circuit, an LED driver circuit, and a memory interface. The memory control circuit is electrically connected to the memory module through the memory interface, and the LED driver circuit is electrically connected to both the memory control circuit and the LED display screen.

[0009] The memory control circuit is used to receive control commands sent by an external host through the host connection interface, read the logic-to-entity mapping table from the memory module according to the control commands, and count the values ​​of the logic addresses in the logic-to-entity mapping table.

[0010] The memory control circuit is also used to generate a corresponding level control signal based on the statistical value corresponding to the value of the logical address and send it to the LED driver circuit. The level control signal is proportional to the magnitude of the statistical value.

[0011] The LED driver circuit is also used to drive the corresponding area in the LED display screen to emit light according to the corresponding level control signal.

[0012] In one embodiment, the memory storage device further includes a buffer memory, which is electrically connected to the memory control circuit.

[0013] Buffer memory is used to temporarily store data and control commands from an external host or data from a memory module.

[0014] In one embodiment, the control command includes a power-on command;

[0015] The memory control circuit is also used to receive power-on commands sent by an external host through the host connection interface, and read the logic-to-entity mapping table from the memory module into the buffer memory according to the power-on command, so as to obtain the initial statistical value corresponding to the value of the logical address in the logic-to-entity mapping table.

[0016] The memory control circuit is also used to generate corresponding level control signals based on the initial statistical values, and send the level control signals to the LED driver circuit to drive the corresponding area in the LED display screen to emit light and display.

[0017] In one embodiment, the control instructions include a data write instruction or a data erase instruction;

[0018] The memory control circuit is also used to write data into the memory module according to a data write instruction or to erase data from the memory module according to a data erase instruction;

[0019] After executing the data write instruction or data erase instruction, the memory control circuit is also used to read the logic-to-entity mapping table into the buffer memory in order to obtain the real-time statistical value corresponding to the value of the logical address in the logic-to-entity mapping table.

[0020] The memory control circuit is also used to generate corresponding level control signals based on real-time statistical values, and send the level control signals to the LED driver circuit to drive the corresponding area in the LED display screen to emit light.

[0021] In one embodiment, the data consists of multiple segments of preset length.

[0022] During the execution of data write instructions or data erase instructions, the memory control circuit is also used to obtain the change in the physical address occupied by the data of the preset length after each preset length of data write or erase is completed, and update the segmented statistical value corresponding to the value of the logical address.

[0023] The memory control circuit is also used to generate corresponding level control signals based on segmented statistical values, and send the corresponding level signals to the LED driver circuit to drive the corresponding area in the LED display screen to emit light and display.

[0024] In one embodiment, the memory control circuit is used to receive formatting control instructions sent by an external host through a host connection interface, and modify the value of the corresponding logical address in the logical-to-entity mapping table to zero according to the formatting control instructions;

[0025] The memory control circuit is also used to generate a clear level control signal and send it to the LED driver circuit when the value of the logical address is zero.

[0026] The LED driver circuit is also used to drive the LED display screen to emit light according to the zero-level control signal.

[0027] In one embodiment, the memory control circuit is also used to calculate the percentage of the statistical value corresponding to the value of the logical address to the entire logic-to-entity mapping table, and send the percentage to the logic-to-entity mapping table for recording;

[0028] The memory control circuit is also used to generate a prompt level signal and send it to the LED driver circuit when the percentage is greater than a preset percentage threshold.

[0029] The LED driver circuit is also used to drive the corresponding area in the LED display screen to flash according to the prompt level signal.

[0030] In one embodiment, the memory control circuit is used to receive a sleep control command sent by an external host to reduce power consumption to a preset state through a host connection interface, calculate the percentage of the statistical value corresponding to the value of the logical address to the entire logic-to-entity mapping table according to the sleep control command, send the percentage to the logic-to-entity mapping table or buffer memory for recording, and control the memory module to enter a sleep state.

[0031] The memory control circuit is also used to generate a corresponding sleep level signal according to the sleep control command and send it to the LED driver circuit;

[0032] The LED driver circuit is also used to drive the LED display screen to reduce its preset display power state according to the sleep level signal.

[0033] In one embodiment, the memory control circuit is used to receive a wake-up control command sent by an external host through a host connection interface, and read a percentage from the logic-to-entity mapping table according to the wake-up control command;

[0034] The memory control circuit is also used to generate a corresponding wake-up level control signal based on the percentage and send it to the LED driver circuit;

[0035] The LED driver circuit is also used to drive the corresponding area in the LED display screen to emit light according to the wake-up level control signal.

[0036] In one embodiment, during the process of counting the values ​​of logical addresses in the logical-to-entity mapping table, the memory control circuit is also used to read the values ​​of logical addresses in the logical-to-entity mapping table, divide the values ​​of logical addresses into logical address values ​​of fixed equal spaces according to the rated capacity value marked by the memory storage device, read the logical-to-entity mapping table of the logical addresses of the aforementioned fixed equal spaces, and verify whether the data in the physical address mapped by the logical address is valid data.

[0037] If so, the memory control circuit is also used to determine whether the physical unit or the programmed unit corresponding to the logical address value is a valid unit.

[0038] If not, the memory control circuit is also used to perform virtual write operations on the physical address mapped by the logical address, and to perform data read operations after the virtual write operation to verify whether the data is correct.

[0039] When the verification data is correct, the memory control circuit is also used to determine whether the physical unit or the programmed unit corresponding to the logical address value is a valid unit; when the verification data is incorrect, the memory control circuit is also used to determine whether the physical unit or the programmed unit corresponding to the logical address value is an invalid unit.

[0040] In one embodiment, the memory storage device has a cuboid structure, and an LED display screen is disposed around the periphery of the memory storage device.

[0041] In one embodiment, the LED display screen is provided with a light-transmitting protective layer.

[0042] In addition, a storage system is provided, including a host and the aforementioned memory storage device.

[0043] The aforementioned memory storage device has an LED display screen mounted on its outer surface. The memory storage device includes: a host connection interface for coupling with an external host; a memory module; and a memory controller, including a memory control circuit, an LED driver circuit, and a memory interface. The memory control circuit is electrically connected to the memory module via the memory interface, and the LED driver circuit is electrically connected to both the memory control circuit and the LED display screen. The memory control circuit receives control commands from the external host via the host connection interface, reads a logic-to-entity mapping table from the memory module according to the control commands, and calculates the values ​​of logical addresses in the logic-to-entity mapping table to obtain the statistical values ​​corresponding to the logical addresses. Simultaneously, the memory control circuit generates corresponding level control signals based on these statistical values ​​and sends them to the LED driver circuit. The LED driver circuit further generates corresponding level control signals based on these level control signals. The level control signal drives the corresponding area in the LED display screen to emit light. Since this statistical value corresponds to the actual storage capacity of the memory module, and the level of the control signal is proportional to the magnitude of the statistical value, it is clear that the area of ​​the light-emitting display in the LED display screen is proportional to the actual storage capacity. In other words, the memory storage device reads the logic-to-entity mapping table from the memory module, then counts the logical address values ​​in the logic-to-entity mapping table to generate the corresponding level control signal and sends it to the LED driver circuit, so that the LED driver circuit drives the corresponding area in the LED display screen to emit light. Ultimately, during the use of the memory storage device, the used capacity of the memory storage device can be directly determined from the appearance, i.e., the light-emitting display area in the LED display screen, greatly improving the capacity visualization effect during the use of the memory storage device. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a structural block diagram of a memory storage device provided in an embodiment of this application;

[0046] Figure 2 This is a schematic diagram of a memory management module provided in an embodiment of this application;

[0047] Figure 3 This is a structural block diagram of another memory storage device provided in an embodiment of this application;

[0048] Figure 4This is a schematic flowchart of a method for mapping statistical logic of a memory control circuit to logical address values ​​in an entity mapping table, provided in an embodiment of this application.

[0049] Figure 5 This is a schematic diagram of the structure of a memory storage device provided in an embodiment of this application. Detailed Implementation

[0050] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, the following embodiments and their technical features can be combined with each other unless otherwise specified.

[0051] like Figure 1 As shown, a memory storage device 100 is provided. An LED display screen 140 is provided on the outer surface of the memory storage device 100. The memory storage device 100 includes: a host connection interface 110, a memory module 120 and a memory controller 130.

[0052] The host connection interface 110 is used for coupling with an external host; the memory controller 130 includes a memory control circuit 132, an LED driver circuit 134, and a memory interface 136. Furthermore, the memory control circuit 132 is electrically connected to the memory module 120 via the memory interface 136, and the memory control circuit 132 is electrically connected to the LED driver circuit 134.

[0053] The LED driver circuit 134 is electrically connected to the LED display screen 140, and the LED driver circuit 134 is used to drive the LED display screen 140 to display.

[0054] The LED driver circuit 134 is monitored and controlled by the memory control circuit 132.

[0055] In one embodiment, the external host can be any type of computer system. For example, the external host can be a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, game console, digital camera, or other electronic systems. The memory storage device 100 is used to store data from the external host. For example, the memory storage device 100 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage devices. The external host can be electrically connected to the memory storage device 100 via a Serial Advanced Technology Attachment (SATA) interface, a High-Speed ​​Peripheral Component Connector (PCI Express) interface, a Universal Serial Bus (USB) interface, or other types of connection interfaces. Therefore, the external host can store data to and / or read data from the memory storage device 100.

[0056] In one embodiment, the host connection interface 110 is electrically connected to the memory control circuit 132 and is used to receive and identify instructions and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 132 through the host connection interface 110. In this embodiment, the host connection interface 110 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto; the host connection interface 110 may also be compatible with PATA, IEEE 1394, PCI Express, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0057] In one embodiment, the host connection interface 110 may be packaged in a chip with the memory controller 130, or the host connection interface 110 may be disposed outside a chip containing the memory controller 130.

[0058] In one embodiment, the memory control circuit 132 is used to receive control commands sent by an external host through the host connection interface 110, and the memory control circuit 132 manages the memory module 120 or the memory storage device 100 according to the control commands.

[0059] In one embodiment, the control commands include power-on commands, data read / write commands, and data erase commands. Specifically, the power-on command refers to the external host recognizing the memory storage device 100, commonly known as "disk recognition." The write command stores data from the external host to the memory storage device 100, and the read command reads data from the memory storage device 100 to the external host.

[0060] In one embodiment, the control instructions further include a data erasure instruction. Specifically, the data erasure instruction erases the data in the memory module 120. Preferably, the memory control circuit 132 executes the data erasure instruction by marking the data in the memory module 120 as invalid data, rather than erasing the data. In other words, the memory module 120 still stores data, but the data in the memory module 120 is invalid data. When these memory modules 120 storing invalid data are subsequently needed, the invalid data is erased first, and then new data is written to these memory modules 120. The purpose of this is to prevent leakage current in the memory module 120, effectively improving the lifespan of the memory module 122 or the memory storage device 100, since the memory module 120 stores data (even invalid data).

[0061] Among them, the control instructions mentioned above are multiple logic gates or control instructions implemented in hardware or firmware.

[0062] In one embodiment, the memory control circuit 132 is used to control the overall operation of the memory controller 130. Specifically, the memory control circuit 132 can acquire multiple control instructions, and these control instructions are executed when the memory storage device 100 is operating to perform operations such as writing, reading, and erasing data. These control instructions include data read or write control instructions. Specifically, a data read instruction reads data from the memory module 120 to an external host; a data write instruction writes data from the external host to the memory module 120.

[0063] In one embodiment, the control instructions of the memory control circuit 132 are operated in firmware form. For example, the memory control circuit 132 has a microprocessor unit and a read-only memory, and the control instructions are burned into this read-only memory. When the memory storage device 100 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0064] In one embodiment, the control instructions of the memory control circuit 132 may also be stored in the form of program code in a specific area of ​​the memory module 120. Furthermore, the memory control circuit 132 includes a microprocessor unit, a read-only memory (ROM), and a random access memory (RAM). Specifically, the ROM has a boot code, and when the memory controller 130 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the memory module 120 into the RAM of the memory control circuit 132. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0065] In another embodiment, the control instructions of the memory control circuit 132 can also be operated in hardware.

[0066] In one embodiment, the memory control circuit 132 may also issue other types of instruction sequences to the memory module 120 to instruct the execution of corresponding operations.

[0067] In one embodiment, the memory interface 136 is electrically connected to the memory control circuit 132 and is used to access the memory module 120. That is, data to be written to the memory module 120 is converted to a format acceptable to the memory module 120 via the memory interface 136. Specifically, if the memory control circuit 132 needs to access the memory module 120, the memory interface 136 transmits a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence instructing data to be written, a read instruction sequence instructing data to be read, an erase instruction sequence instructing data to be erased, and corresponding instruction sequences for instructing various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated, for example, by the memory control circuit 132 and transmitted to the memory module 120 via the memory interface 136. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include a read identifier, memory address, and other information.

[0068] Among them, such as Figure 2 As shown, the memory module 120 includes multiple physical units 301(0) to 301(A). Each physical unit includes multiple storage cells for non-volatile data storage. For example, a physical unit may include one or more physical blocks. Each physical block may include multiple physical programming units. A physical programming unit may include one or more physical pages. Multiple storage cells in a physical programming unit can be programmed simultaneously to store data. Furthermore, all storage cells in a physical block can be erased simultaneously.

[0069] Among them, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a memory management module provided in one embodiment of this application. The memory control circuit 132 can configure multiple logic units 302(0)--302(B) to map physical units 301(0)--301(A). For example, a logic unit consists of one or more logic addresses. The mapping relationship between logic units and physical units can be recorded in a logic-to-physical mapping table. For example, when an access instruction is received from an external host, the memory control circuit 132 can access data into the physical unit according to the corresponding logic-to-physical mapping table.

[0070] In one embodiment, the memory control circuit 132 accesses data stored in the memory module 120 via logical addresses (LBAs). Therefore, each of the logic units 302(0) to 302(B) refers to a logical address. However, in another exemplary embodiment, each of the logic units 302(0) to 302(B) may also consist of multiple consecutive (e.g., consecutively numbered) logical addresses.

[0071] The memory control circuit 132 records the mapping relationship between logic units and physical units (also known as logic-to-physical mapping relationship) in at least one logic-to-physical mapping table. When an external host wants to read data from or write data to the memory storage device 100, the memory control circuit 132 can perform data access for the memory module 120 according to this logic-to-physical mapping table.

[0072] In one embodiment, the memory module 120 is used to store data written by an external host. The memory module 120 may include a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a Multi Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0073] In one embodiment, the memory control circuit 132 is used to receive control commands sent by an external host through the host connection interface 110, read the logic-to-entity mapping table from the memory module 120 according to the control commands, and count the values ​​of the logical addresses in the logic-to-entity mapping table, that is, to obtain the statistical value corresponding to the value of the logical address, which corresponds to the actual storage capacity of the memory module 120.

[0074] For example, if the memory storage device 100 is labeled with a capacity of 60GB and is page-mapped, then the logical address value included in the memory storage device 100 is 60 * 1024 * 1024 * 2 = 125829120, meaning there are 125829120 logical-to-physical (entity) relationships in the memory storage device 100. Preferably, the statistical value of the logical address value in the manufactured memory storage device 100 should be less than or equal to the value of 125829120. If the statistical value of the logical address value of the memory storage device 100 is greater than the value of 125829120, it indicates that the capacity of the memory storage device 100 or the memory module 120 is inaccurate. This is because logical addresses exceeding the logical address value of the memory storage device 100 are mapped to non-existent physical addresses (here, physical address refers to physical entity pages).

[0075] Furthermore, when the host is a computer, although the capacity of the memory storage device 100 can be obtained through a monitor connected to the computer, this method of obtaining the capacity of the memory storage device 100 is done through the file management system of the memory storage device 100. The aforementioned memory control circuit 132 obtains the actual storage capacity of the memory module 120 by statistically mapping the values ​​of logical addresses in the entity mapping table, and then obtaining the statistical values ​​corresponding to the logical address values. This process does not require obtaining the actual capacity of the memory storage device 100 through its file management system. Compared to obtaining the capacity of the memory storage device 100 through the file management system, this method makes obtaining the actual capacity of the memory storage device 100 more accurate and less prone to false capacity readings.

[0076] Furthermore, in one embodiment, the memory control circuit 130 is also used to generate a corresponding level control signal based on the statistical value corresponding to the logical address value and send it to the LED driving circuit 134. The LED driving circuit 134 drives the corresponding area in the LED display screen 140 to emit light according to the corresponding level control signal. Since the statistical value corresponds to the actual storage capacity of the memory module 120, and the level control signal is proportional to the magnitude of the statistical value, it is obvious that the area of ​​the light-emitting display area in the LED display screen 140 is proportional to the actual storage capacity. This allows the memory storage device 100 to directly determine its used capacity from the appearance of the light-emitting display area in the LED display screen 140 during use, greatly improving the visualization effect of the memory storage device 100's capacity during use.

[0077] In this embodiment, the memory control circuit 132 receives control commands sent by an external host through a host connection interface. Based on the control commands, it reads the logic-to-entity mapping table from the memory module 120 and counts the values ​​of the logical addresses in the logic-to-entity mapping table to obtain the statistical values ​​corresponding to the logical address values. At this time, the memory control circuit 132 also generates a corresponding level control signal based on the statistical value and sends it to the LED driver circuit 134. The LED driver circuit 134 then drives the corresponding area in the LED display screen 140 to emit light according to the corresponding level control signal. Since the statistical value corresponds to the actual storage capacity of the memory module 120, and the level of the control signal is proportional to the magnitude of the statistical value, it is obvious that the LED display... The area of ​​the light-emitting display area in the LED display screen 140 is proportional to the actual storage capacity. In other words, the memory storage device 100 reads the logic-to-entity mapping table from the memory module 120, and then counts the values ​​of the logic addresses in the logic-to-entity mapping table to generate corresponding level control signals and send them to the LED driver circuit 134. This causes the LED driver circuit 134 to drive the corresponding area in the LED display screen 140 to emit light. Ultimately, during the use of the memory storage device 100, the used capacity of the memory storage device 100 can be directly determined from the appearance of the light-emitting display area in the LED display screen 140, which greatly improves the capacity visualization effect during the use of the memory storage device 100.

[0078] In one embodiment, such as Figure 3 As shown, Figure 3 This is a structural block diagram of another memory storage device provided in an embodiment of this application. The memory storage device 100 further includes a buffer memory 150, which is electrically connected to the memory control circuit 132. The buffer memory 150 is electrically connected to the memory control circuit 132 and is used to temporarily store data and control instructions from an external host or data from the memory module 120. Preferably, the buffer memory 150 is DRAM.

[0079] In one embodiment, when the control command is a power-on command, the memory control circuit 132 receives the power-on command sent by the external host through the host connection interface. Based on the power-on command, it reads the logic-to-entity mapping table from the memory module 120 into the buffer memory 150 to obtain the initial statistical value corresponding to the logical address value in the logic-to-entity mapping table. The memory control circuit 132 is also used to generate a corresponding level control signal based on the corresponding initial statistical value and send the level control signal to the LED driver circuit 134 to drive the corresponding area in the LED display screen 140 to emit light. The area of ​​light emission is proportional to the initial used capacity. That is, once the memory storage device 100 is successfully connected to the host, the initial used capacity of the memory storage device 100 can be directly determined from the appearance, i.e., the light emission area in the LED display screen 140, without needing to obtain the capacity of the memory storage device 100 through the host's display screen. This greatly improves the visualization effect of the memory storage device 100's capacity during use, especially when the host is a mobile terminal such as a mobile phone.

[0080] Furthermore, in one embodiment, the control instructions include a data write instruction or a data erase instruction; the memory control circuit 132 is also used to write data into the memory module 120 according to the data write instruction or erase data from the memory module 120 according to the data erase instruction.

[0081] After executing the data write instruction or data erase instruction, the memory control circuit 132 is also used to read the logic-to-entity mapping table into the buffer memory 150 to obtain the real-time statistical value corresponding to the value of the logical address in the logic-to-entity mapping table.

[0082] Specifically, after executing the data write or data erase instruction, the memory control circuit 132 updates the value of the corresponding logical address according to the change in the data stored in the physical address, thereby obtaining the real-time statistical value corresponding to the logical address value, and finally obtaining the actual storage capacity of the memory module in real time based on the real-time statistical value. For example, data written to the physical address is marked with "0", and data erased from the physical address is marked with "1". When subsequently obtaining the value of the logical address, the capacity of the memory storage device 100 after executing the data write or data erase instruction can be calculated by counting the number of "0"s.

[0083] The memory control circuit 132 is also used to generate a corresponding level control signal based on real-time statistical values, and send the level control signal to the LED driver circuit 134 to drive the corresponding area in the LED display screen 140 to emit light and display. This makes the capacity visualization effect of the memory storage device 100 during use better.

[0084] In one embodiment, after executing each data write or data erase instruction, the memory control circuit 132 updates the value of the corresponding logical address based on the changes in the data stored in the physical address, thereby obtaining the actual storage capacity of the memory module in real time. This further improves the capacity visualization effect during the use of the memory storage device 100.

[0085] In one embodiment, the data consists of multiple segments of preset length. During the execution of a data write instruction or a data erase instruction, the memory control circuit 132 is further configured to obtain the change in the physical address occupied by the preset length of data after each preset length of data has been written or erased, and update the segmented statistical value corresponding to the value of the logical address. The memory control circuit 132 is also configured to generate a corresponding level control signal based on the segmented statistical value, and send the corresponding level signal to the LED driver circuit 134 to drive the corresponding area in the LED display screen 140 to emit light and display.

[0086] In this embodiment, when the data volume is large, i.e., when it contains multiple segments of data of a preset length, the segmented statistical value corresponding to the value of the logical address is updated by obtaining the change in the physical address occupied by the data of the preset length after each preset length of data is written or erased. Then, a corresponding level control signal is generated according to the segmented statistical value, and the corresponding level signal is sent to the LED driver circuit 134 to drive the corresponding area in the LED display screen 140 to emit light. Since the segmented statistical value corresponds to the storage capacity occupied by each segment of data of the preset length in the memory module 120, and the level control signal is proportional to the size of the statistical value, the corresponding area in the LED display screen 140 is proportional to the storage capacity occupied by each segment of data of the preset length in the memory module 120. When the preset length of data is written or erased, the corresponding area in the LED display screen 140 changes, further improving the capacity visualization effect during the use of the memory storage device 100.

[0087] Furthermore, in one embodiment, during the process of the memory control circuit 132 calculating the value of the logical address in the entity mapping table, it is also used to perform the following steps:

[0088] Step S11: Read the value of the logical address in the logical-to-entity mapping table, and divide the value of the logical address into multiple fixed equal-division logical address value units according to the rated capacity value marked by the memory storage device.

[0089] For example, taking the aforementioned 60GB memory storage device 100 as an example, its mapping method is page mapping. Therefore, the logical address value of the memory storage device 100 is 60 * 1024 * 1024 * 2 = 125829120. Dividing the 60GB memory storage device 100 into 60 parts, each part contains a logical address value of 1024 * 1024 * 2 = 2097152. Therefore, the 60GB will be divided into 60 spaces (Gap) using 2097152 logical addresses.

[0090] Step S12: The memory control circuit reads a logical address value unit of a fixed equally divided space and verifies whether the data in the physical address mapped to each logical address in the logical address value unit is valid data. If yes, proceed to step S13; otherwise, proceed to step S14.

[0091] Step S13: The entity unit or entity programmable unit corresponding to the physical address mapped by the logical address is a valid unit.

[0092] Step S14: Perform a virtual write operation on the physical address mapped to the logical address, and then perform a data read operation after the virtual write operation to verify whether the data is correct. If it is correct, proceed to step S13; otherwise, proceed to step S15.

[0093] Step S15: The entity unit or entity programmable unit corresponding to the physical address mapped by the logical address is an invalid unit.

[0094] Preferably, step S11 further includes selecting the fixed equally divided space using a binary search method. This can speed up the verification of whether the entity unit or entity programmable unit corresponding to the physical address mapped by the logical address is a valid unit.

[0095] For example, the 60G memory storage device 100 is divided into 60 parts, each with a fixed equal space (Gap) of 1G. Initially, the smallest Gap 1 is selected, followed by the 64G Gap 60. If Gap 60 is an invalid cell, the process jumps to Gap 30. If it is valid, the process jumps to Gap 45 for verification. If it is invalid, the process jumps to Gap 30 for verification, and so on. This process is used to quickly verify whether the physical cell or physical programmable cell corresponding to the logical address is a valid cell.

[0096] In one embodiment, the memory control circuit 132 is used to receive a formatting control command sent by an external host through a host connection interface, and modify the value of the corresponding logical address in the logical-to-entity mapping table to zero according to the formatting control command.

[0097] The memory control circuit 132 is also used to generate a clear level control signal and send it to the LED driver circuit 134 when the value of the logic address is zero.

[0098] The LED driver circuit 134 is also used to drive the LED display screen 140 to emit light according to the zero-level control signal.

[0099] In this embodiment, after executing the formatting control command, the memory control circuit 132 can generate a clear level control signal and send it to the LED driver circuit 134, so that the LED driver circuit 134 drives the LED display screen 140 to emit light according to the clear level control signal. When the memory module 120 is empty, it can perform a unique light emission display, such as changing the color or frequency of the light emission display, which can further improve the visualization effect of the entire memory storage device 100 during use.

[0100] In one embodiment, the memory control circuit 132 is also used to calculate the percentage of the statistical value corresponding to the value of the logical address to the entire logic-to-entity mapping table, and send the percentage to the logic-to-entity mapping table or the buffer memory for recording.

[0101] The memory control circuit 132 is also used to generate a prompt level signal and send it to the LED driver circuit 134 when the percentage is greater than a preset percentage threshold.

[0102] The LED driver circuit 134 is also used to drive the corresponding area in the LED display screen 140 to flash according to the prompt level signal.

[0103] In this embodiment, by calculating the percentage of the statistical value corresponding to the logical address value to the entire logical-to-entity mapping table, and sending the percentage to the logical-to-entity mapping table for recording, the memory control circuit 132 can generate a prompt level signal and send it to the LED driver circuit 134 when the percentage is greater than a preset percentage threshold. This enables the memory control circuit 132 to monitor the percentage of the used capacity of the memory module 120. When the percentage is greater than the preset percentage threshold (i.e., when the used capacity of the memory module 120 exceeds the corresponding preset capacity), it generates a prompt level signal and sends it to the LED driver circuit 134, thereby controlling the LED driver circuit 134 to drive the LED display screen 140 to flash with a preset color to provide a prompt. This further improves the visualization effect of the used capacity during the use of the entire memory storage device 100.

[0104] In one embodiment, the memory control circuit 132 is used to receive a sleep control command sent by an external host to reduce power consumption to a preset state through a host connection interface, calculate the percentage of the statistical value corresponding to the value of the logical address to the entire logic-to-entity mapping table according to the sleep control command, send the percentage to the logic-to-entity mapping table or the buffer memory 150 for recording, and control the memory module 120 to enter the sleep state.

[0105] The memory control circuit 132 is also used to generate a corresponding sleep level signal according to the sleep control command and send it to the LED driver circuit 134;

[0106] The LED driver circuit 134 is also used to drive the LED display screen 140 to reduce to a preset display power state according to the sleep level signal.

[0107] The preset power consumption state is usually a low power consumption state with a certain preset power. After the memory storage device 100 has completed the data transmission in the power-on state, in order to save power consumption, the memory storage device 100 can be further adjusted to enter the sleep state. Before entering the sleep state, the memory control circuit 132 needs to store the above percentage in the logic to entity mapping table or buffer memory 150 in the memory module 120 to lay the foundation for the subsequent wake-up process.

[0108] The memory control circuit 132 also generates a corresponding sleep level signal according to the sleep state control command and sends it to the LED driver circuit 134 so that the LED driver circuit 134 controls the LED display screen 140 to reduce to a preset display power state (i.e., enter sleep state).

[0109] When the LED display screen 140 enters sleep mode, the brightness of the LED display screen can be reduced.

[0110] In this embodiment, the brightness of the LED display screen 140 is adjusted by the memory control circuit 132 according to the sleep control command, which further reduces the power consumption of the entire memory storage device 100 and can further improve the visualization effect of the memory storage device 100 during use.

[0111] In one embodiment, the memory control circuit 132 is used to receive a wake-up control command sent by an external host through a host connection interface, and read a percentage from the logic-to-entity mapping table or buffer memory 150 according to the wake-up control command.

[0112] The memory control circuit 132 is also used to generate a corresponding wake-up level control signal based on the percentage and send it to the LED driver circuit 134;

[0113] The LED driver circuit 134 is also used to drive the corresponding area in the LED display screen 140 to emit light according to the wake-up level control signal.

[0114] In this embodiment, the memory control circuit 132 receives a wake-up control command sent by an external host through the host connection interface. Based on the wake-up control command, it reads the percentage from the logic-to-entity mapping table or the buffer memory 150, and then generates a corresponding wake-up level control signal based on the percentage and sends it to the LED driver circuit 134 to drive the corresponding area of ​​the LED display screen 140 to emit light, thereby further improving the visualization effect of the memory storage device 100 during use.

[0115] In this embodiment, when the memory control circuit 132 reads the percentage from the buffer memory 150 according to the wake-up control command, the time for reading from the logic to entity mapping table is reduced, thereby enabling the LED driving circuit 134 to drive the corresponding area in the LED display screen 140 to emit light quickly. This helps to quickly obtain the used capacity and remaining available capacity of the memory storage device 100, thereby further improving the visualization effect of the memory storage device 100 during use.

[0116] In one embodiment, such as Figure 5 As shown, the memory storage device 100 has a cuboid structure, and the LED display screen 140 is arranged around the periphery of the memory storage device 100.

[0117] In this embodiment, the memory storage device 100 has a cuboid structure, and the LED display screen 140 is arranged around the periphery of the memory storage device 100. The memory control circuit 132 receives control commands sent by an external host through the host connection interface 110. When writing data into the memory module 120 according to the control commands, it further calculates the percentage of the used capacity based on the initial available capacity and the storage capacity occupied by the written data. It generates a corresponding level control signal based on the percentage of the used capacity and sends the corresponding level control signal to the LED driving circuit 134. The LED driving circuit 134 also drives the first preset area 10 in the LED display screen 140 for display based on the level control signal corresponding to the percentage of the used capacity. The percentage of the area of ​​the first preset area 10 in the LED display screen is the same as the percentage of the used capacity.

[0118] In this embodiment, as data is continuously written, the area of ​​the first preset region in the LED display screen 140 continuously increases, allowing direct visual perception of the changes in the used capacity and remaining available capacity of the entire memory storage device 100. The entire memory storage device 100 is like a container filled with water. As the "water source is continuously injected" (i.e., data is written), the "water level" (i.e., the used capacity) of the memory storage device 100 continuously rises, which can greatly enhance the visualization effect during the use of the entire memory storage device 100.

[0119] In one embodiment, the LED display screen 140 is provided with a light-transmitting protective layer.

[0120] By setting a light-transmitting protective layer, the durability of the LED display screen 140 in the memory storage device 100 can be further improved while ensuring the overall visibility of the memory storage device 100.

[0121] In addition, a storage system is provided, including a host and the aforementioned memory storage device 100.

[0122] That is, the above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0123] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0124] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0125] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A memory storage device, characterized in that, An LED display screen is provided on the outer surface of the memory storage device, and the memory storage device includes: Host connection interface, used for coupling with external host; Memory module; The memory controller includes a memory control circuit, an LED driver circuit, and a memory interface. The memory control circuit is electrically connected to the memory module through the memory interface, and the LED driver circuit is electrically connected to both the memory control circuit and the LED display screen. A buffer memory, electrically connected to the memory control circuit; The memory control circuit is used to receive control commands sent by the external host through the host connection interface, read the logic-to-entity mapping table from the memory module according to the control commands, and count the values ​​of the logic addresses in the logic-to-entity mapping table. The memory control circuit is also used to generate a corresponding level control signal based on the statistical value corresponding to the value of the logical address and send it to the LED driver circuit. The level control signal is proportional to the magnitude of the statistical value. The LED driving circuit is also used to drive the corresponding area in the LED display screen to emit light according to the corresponding level control signal; The control commands include data write commands or data erase commands; The memory control circuit is also used to write data into the memory module according to the data write instruction or erase data from the memory module according to the data erase instruction; After executing the data write instruction or the data erase instruction, the memory control circuit is further configured to read the logic-to-entity mapping table into the buffer memory to obtain the real-time statistical value corresponding to the value of the logical address in the logic-to-entity mapping table, and generate a corresponding level control signal based on the real-time statistical value to drive the corresponding area in the LED display screen to emit light and display. The data consists of multiple segments of preset length. During the execution of the data write instruction or the data erase instruction, the memory control circuit is also used to obtain the change in the physical address occupied by the preset length of data after each preset length of data is written or erased, update the segmented statistical value corresponding to the value of the logical address, and generate a corresponding level control signal based on the segmented statistical value to drive the corresponding area in the LED display screen to emit light.

2. The memory storage device according to claim 1, characterized in that, The control commands include power-on commands; The memory control circuit is also used to receive a power-on command sent by the external host through the host connection interface, and read the logic-to-entity mapping table from the memory module into the buffer memory according to the power-on command, so as to obtain the initial statistical value corresponding to the value of the logical address in the logic-to-entity mapping table; The memory control circuit is also used to generate a corresponding level control signal based on the initial statistical value, and send the level control signal to the LED driving circuit to drive the corresponding area in the LED display screen to emit light.

3. The memory storage device according to claim 1, characterized in that, The memory control circuit is used to receive formatting control instructions sent by the external host through the host connection interface, and modify the value of the corresponding logical address in the logical-to-entity mapping table to zero according to the formatting control instructions; The memory control circuit is also used to generate a clear level control signal and send it to the LED driver circuit when the value of the logical address is zero. The LED driving circuit is also used to drive the LED display screen to emit light according to the reset level control signal.

4. The memory storage device according to claim 1, characterized in that, The memory control circuit is also used to calculate the percentage of the statistical value corresponding to the value of the logical address in the entire logical-to-entity mapping table, and send the percentage to the logical-to-entity mapping table for recording; The memory control circuit is also used to generate a prompt level signal and send it to the LED driver circuit when the percentage is greater than a preset percentage threshold. The LED driving circuit is also used to drive the corresponding area in the LED display screen to flash according to the prompt level signal.

5. The memory storage device according to claim 1, characterized in that, The memory control circuit is used to receive a sleep control command sent by the external host to reduce power consumption to a preset state through the host connection interface, calculate the percentage of the statistical value corresponding to the value of the logical address to the entire logic-to-entity mapping table according to the sleep control command, send the percentage to the logic-to-entity mapping table or the buffer memory for recording, and control the memory module to enter a sleep state. The memory control circuit is also used to generate a corresponding sleep level signal according to the sleep control command and send it to the LED driver circuit; The LED driving circuit is also used to drive the LED display screen to reduce to a preset display power state according to the sleep level signal.

6. The memory storage device according to claim 5, characterized in that, The memory control circuit is used to receive a wake-up control command sent by the external host through the host connection interface, and read the percentage from the logic-to-entity mapping table or the buffer memory according to the wake-up control command; The memory control circuit is also used to generate a corresponding wake-up level control signal according to the percentage and send it to the LED driver circuit; The LED driving circuit is also used to drive the corresponding area in the LED display screen to perform the light-emitting display according to the wake-up level control signal.

7. The memory storage device according to claim 1, characterized in that, The memory storage device has a cuboid structure, and the LED display screen is arranged around the periphery of the memory storage device.

8. The memory storage device according to claim 1, characterized in that, During the process of counting the values ​​of logical addresses in the logical-to-entity mapping table, the memory control circuit is also used to read the values ​​of logical addresses in the logical-to-entity mapping table, divide the values ​​of logical addresses into logical address values ​​of fixed equal spaces according to the rated capacity value marked by the memory storage device, read the logical-to-entity mapping table of the logical addresses of the above-mentioned fixed equal spaces, and verify whether the data in the physical address mapped by the logical address is valid data. If so, the memory control circuit is also used to determine whether the physical unit or the physical programmable unit corresponding to the physical address mapped by the logical address value is a valid unit; If not, the memory control circuit is also used to perform a virtual write operation on the physical address mapped by the logical address, and to perform a data read operation after the virtual write operation to verify whether the data is correct. When the verification data is correct, the memory control circuit is also used to determine whether the physical unit or the physical programmable unit corresponding to the logical address value is a valid unit. When the verification data is incorrect, the memory control circuit is also used to determine that the physical unit or physical programmable unit corresponding to the logical address value is an invalid unit.

9. The memory storage device according to claim 1, characterized in that, The LED display screen is equipped with a light-transmitting protective layer.

10. A storage system, characterized in that, It includes a host computer and a memory storage device according to any one of claims 1 to 9.

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