Interface delay circuit, iic bus device, communication system, and interface delay method

Abstract

The application relates to an interface delay circuit, an IIC bus device, a communication system and an interface delay method. The interface delay circuit comprises a first delay circuit and a second delay circuit. The first delay circuit is used for receiving a serial clock signal, and the second delay circuit is used for receiving a serial data signal. The first delay circuit is further used for performing delay processing on the input serial clock signal. When the serial clock signal is a low-level signal, a first delay channel is formed. When the serial clock signal is a high-level signal, a second delay channel is formed. The second delay circuit is further used for performing delay processing on the input serial data signal and correspondingly forming a third delay channel. The delay time of the second delay channel is the same as that of the third delay channel, and the delay time of the first delay channel is smaller than that of the third delay channel. The interface delay circuit and the IIC bus device improve the communication quality of the IIC bus.

Description

Technical Field

[0001] This application relates to the field of electronic communications, specifically to an interface delay circuit, an IIC bus device, a communication system, and an interface delay method. Background Technology

[0002] The IIC bus protocol is currently a commonly used bus protocol. The two ends of the IIC bus are connected to the signal transmitting device and the signal receiving device, respectively. The IIC bus generally requires two lines: a serial clock line (SCL) and a serial data line (SDA). The serial clock line is used as a control line, and the serial data line is used as a data line. Both are signal lines of the IIC bus.

[0003] like Figure 1 As shown, according to the IIC communication protocol, when the IIC bus is idle, both SDA and the serial control line remain at a high level. When the serial control line is high, SDA changes from high to low, which is the Start signal, indicating that the IIC bus communication has started. When the serial control line is high, SDA changes from low to high, which is the Stop signal, indicating that the IIC bus communication has ended. During normal data transmission, the SDA level signal is only allowed to transition between high and low when the serial control line is low.

[0004] However, the above process requires strict timing requirements for both SDA and the serial control line. In current IIC bus applications, if the SDA transition edge is close to the serial control line transition edge, many timing logic errors will occur. Summary of the Invention

[0005] In view of this, this application provides an interface delay circuit, an IIC bus device, a communication system, and an interface delay method. When the interface delay circuit is applied to the IIC bus, it can greatly reduce timing errors of the IIC bus and improve the communication quality of the IIC bus.

[0006] An interface delay circuit includes: a first delay circuit and a second delay circuit, wherein the first delay circuit is used to receive a serial clock signal and the second delay circuit is used to receive a serial data signal.

[0007] The first delay circuit is also used to delay the input serial clock signal. When the serial clock signal is a low-level signal, a first delay path is formed; when the serial clock signal is a high-level signal, a second delay path is formed.

[0008] The second delay circuit is also used to delay the input serial data signal and form a third delay path accordingly.

[0009] The second and third delay paths have the same delay time, while the first delay path has a shorter delay time than the third delay path.

[0010] In one embodiment, the resistance of the first delay path is less than the resistance of the third delay path, and the resistance of the second delay path is equal to the resistance of the third delay path.

[0011] In one embodiment, the first delay circuit includes a first level conversion unit, a second level conversion unit, and a first delay unit that are electrically connected in sequence. The first delay circuit also includes a delay control unit. The control terminal of the delay control unit is electrically connected to the output terminal of the first level conversion unit, the input terminal of the delay control unit is electrically connected to the output terminal of the second level conversion unit, and the output terminal of the delay control unit is electrically connected to the output terminal of the first delay unit.

[0012] The first level conversion unit is used to perform level conversion processing on the input serial clock signal to obtain the first level conversion signal;

[0013] The delay control unit is used to control the first delay unit according to the first level conversion signal, so that the first delay circuit forms a first delay path or a second delay path;

[0014] When the first delay circuit forms the first delay path, the delay control unit controls the first delay unit to be in a short-circuited state.

[0015] In one embodiment, the second delay circuit includes a second delay unit, the second delay unit having the same delay time for the serial data signal as the first delay unit has for the serial clock signal.

[0016] In one embodiment, the first delay unit and the second delay unit are resistive devices.

[0017] In one embodiment, the delay control unit is a switching device. When the first delay circuit forms a first delay path, the delay control unit is closed; when the first delay circuit forms a second delay path, the delay control unit is open.

[0018] In one embodiment, the switching device includes an NMOS switch, and both the first level conversion unit and the second level conversion unit include an odd number of voltage switching devices that are electrically connected in sequence. The gate of the NMOS switch is electrically connected to the output terminal of the first level conversion unit, and the output terminal of the second level conversion unit is electrically connected to the source of the NMOS switch.

[0019] In one embodiment, the switching device includes a PMOS switch, and both the first level conversion unit and the second level conversion unit include an even number of voltage switching devices that are electrically connected in sequence. The gate of the PMOS switch is electrically connected to the output terminal of the first level conversion unit, and the output terminal of the second level conversion unit is electrically connected to the source of the PMOS switch.

[0020] In one embodiment, the delay control unit includes a transmission gate structure. Both the first level conversion unit and the second level conversion unit include an even number of voltage inversion devices that are connected in sequence. The first control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device at the even-numbered position in the first level conversion unit. The second control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device at the odd-numbered position in the first level conversion unit. The input terminal of the transmission gate structure is electrically connected to the output terminal of the second level conversion unit.

[0021] In one embodiment, when the input serial clock signal is a low-level signal, the transmission gate structure is in the on state so that the first delay circuit forms a first delay path;

[0022] When the input serial clock signal is a high-level signal, the transmission gate structure is in the open state, allowing the first delay circuit to form the second delay path.

[0023] In one embodiment, the voltage switching device includes any one of an inverter, a Schmitt trigger, and a voltage selection circuit.

[0024] In one embodiment, the interface delay circuit further includes:

[0025] The first filtering unit is electrically connected to the output terminal of the first delay circuit and is used to filter and output the level signal output by the first delay circuit.

[0026] The second filtering unit is electrically connected to the second delay circuit and is used to filter the level signal output by the second delay circuit.

[0027] In one embodiment, the first filtering unit or the second filtering unit employs an RC filter.

[0028] In addition, an IIC bus device is provided, which is provided with the aforementioned interface delay circuit.

[0029] In addition, a communication system is also provided, including:

[0030] A communication system, comprising:

[0031] The first terminal is used to generate serial clock signals and serial data signals;

[0032] The IIC bus device is electrically connected to the first terminal and is used to receive the serial clock signal and serial data signal sent by the first terminal, transmit the serial clock signal on the serial control line and the serial data signal on the serial data line, and perform delay processing on the input serial clock signal through the first delay circuit to output the delayed serial clock signal. When the input serial clock signal is a low level signal, a first delay path is formed; when the input serial clock signal is a high level signal, a second delay path is formed.

[0033] The IIC bus device is also used to delay the input serial data signal and form a third delay path to output the delayed serial data signal. The delay time of the second delay path and the third delay path are the same, and the delay time of the first delay path is less than the delay time of the third delay path.

[0034] The second terminal is electrically connected to the IIC bus device and is used to receive the delayed serial clock signal and serial data signal output by the IIC bus device.

[0035] In addition, an interface delay method is provided for use on an IIC bus, which includes serial control lines and serial data lines. The interface delay method includes:

[0036] The input serial clock signal is delayed. When the serial clock signal is low, a first delay path is formed; when the serial clock signal is high, a second delay path is formed.

[0037] The input serial data signal is delayed, and a third delay path is formed accordingly. The delay time of the second delay path is the same as that of the third delay path, and the delay time of the first delay path is less than that of the third delay path.

[0038] The aforementioned interface delay circuit, on the one hand, when the serial clock signal is a low-level signal (i.e., transitioning from a high-level signal to a low-level signal), because the delay time of the first delay path is less than the delay time of the third delay path, the delay of the serial data signal is greater than the delay of the serial clock signal, thus increasing the corresponding data hold time. On the other hand, when the serial clock signal is a high-level signal (i.e., transitioning from a low-level signal to a high-level signal), a second delay path is formed. Because the path delay of the serial data signal generated by the third delay path is equal to the path delay of the serial clock signal generated by the second delay path, and since there is a transmission time difference between the serial data signal and the serial clock signal, the data setup time is equal to the transmission time difference between the serial data signal and the serial clock signal, thus keeping the data setup time constant. While increasing the data hold time, it also keeps the data setup time constant, reducing the degree of timing logic disorder caused when the data hold time is close to or equal to 0ns. Overall, this greatly reduces timing errors on the IIC bus and improves the communication quality of the IIC bus. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating the timing principle of IIC bus operation provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram illustrating the timing principle of another IIC bus operation provided in an embodiment of this application;

[0042] Figure 3 This is a circuit structure block diagram of an interface delay circuit provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the first circuit structure of the interface delay circuit provided in the embodiments of this application;

[0044] Figure 5 This is a schematic diagram of the second circuit structure of the interface delay circuit provided in the embodiments of this application;

[0045] Figure 6 This is a schematic diagram of the third circuit structure of the interface delay circuit provided in the embodiments of this application;

[0046] Figure 7 This is a schematic diagram of the fourth circuit structure of the interface delay circuit provided in the embodiments of this application;

[0047] Figure 8 This is a schematic diagram of the fifth circuit structure of the interface delay circuit provided in the embodiments of this application;

[0048] Figure 9 This is a circuit structure block diagram of the IIC bus device provided in the embodiments of this application;

[0049] Figure 10 This is a circuit structure block diagram of the communication system provided in the embodiments of this application;

[0050] Figure 11 This is a flowchart illustrating the interface delay method provided in the embodiments of this application. Detailed Implementation

[0051] like Figure 2 As shown, the IIC bus requires a data setup time T in its timing requirements. su The requirement is greater than 50 ns for the data retention time T. hd The requirement is greater than 0 ns; however, in practical applications, if the IIC bus transmission speed is increased, the data setup time T will increase. su Reduce, data retention time T hd This naturally also decreases when the device data retention time T... hd When the time interval is close to or equal to 0ns, due to system jitter or the difference in length between SDA and the serial control line, a normal data signal may be identified as a Start signal by the system, and the previous data will be discarded to start a new round of communication. Similarly, if the time interval between the rising edge of SDA and the falling edge of the serial control line is close to or equal to 0ns, normal data may be misinterpreted as a Stop signal, causing communication interruption. The above situations can easily cause the IIC bus to malfunction.

[0052] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0053] like Figure 3 As shown, an interface delay circuit 100 includes: a first delay circuit 110 and a second delay circuit 120, wherein the first delay circuit 110 is used to receive a serial clock signal and the second delay circuit 120 is used to receive a serial data signal.

[0054] The first delay circuit 110 is also used to delay the input serial clock signal. When the serial clock signal is a low-level signal, a first delay path is formed; when the serial clock signal is a high-level signal, a second delay path is formed.

[0055] The second delay circuit 120 is also used to delay the input serial data signal and form a third delay path accordingly.

[0056] The second and third delay paths have the same delay time, while the first delay path has a shorter delay time than the third delay path.

[0057] The aforementioned interface delay circuit 100, on the one hand, if the serial clock signal is a low-level signal (i.e., a transition from a high-level signal to a low-level signal), because the delay time of the first delay path is less than the delay time of the third delay path, that is, the delay of the serial data signal is greater than the delay of the serial clock signal, thus increasing the corresponding data hold time; on the other hand, if the serial clock signal is a high-level signal (i.e., a transition from a low-level signal to a high-level signal), a second delay path is formed. Because the path delay of the serial data signal generated by the third delay path is equal to the path delay of the serial clock signal generated by the second delay path, and since there is a transmission time difference between the serial data signal and the serial clock signal, the data setup time is equal to the transmission time difference between the serial data signal and the serial clock signal, thus keeping the data setup time constant. While increasing the data hold time, it can also keep the data setup time constant, reducing the degree of timing logic disorder caused when the data hold time is close to or equal to 0ns, and greatly reducing the timing errors of the IIC bus overall, thus improving the communication quality of the IIC bus.

[0058] In one embodiment, the resistance of the first delay path is less than the resistance of the third delay path, and the resistance of the second delay path is equal to the resistance of the third delay path.

[0059] In one embodiment, such as Figure 4 As shown, the first delay circuit 110 includes a first level conversion unit 111, a second level conversion unit 112, and a first delay unit 113 connected in sequence. The first delay circuit 110 also includes a delay control unit 114. The control terminal of the delay control unit 114 is electrically connected to the output terminal of the first level conversion unit 111, the input terminal of the delay control unit 114 is electrically connected to the output terminal of the second level conversion unit 112, and the output terminal of the delay control unit 114 is electrically connected to the output terminal of the first delay unit 113.

[0060] The first level conversion unit 111 is used to perform level conversion processing on the input serial clock signal to obtain the first level conversion signal and output it to the input terminal of the second level conversion unit 112 and the control terminal of the delay control unit 114 respectively.

[0061] The second level conversion unit 112 is used to perform level conversion processing on the first level conversion signal to obtain a second level conversion signal. The level conversion signal of the second level conversion signal has the same level direction as the serial clock signal.

[0062] The delay control unit 114 is used to control the first delay unit 113 according to the first level conversion signal, so that the first delay circuit 110 forms a first delay path or forms a second delay path;

[0063] When the first delay circuit 110 forms the first delay path, the delay control unit 114 controls the first delay unit 113 to be in a short-circuited state.

[0064] In one embodiment, the second delay circuit 120 includes a second delay unit, the second delay unit having the same delay time for the serial data signal as the first delay unit 113 has for the serial clock signal.

[0065] The first level conversion signal is output to the control terminal of the delay control unit 114 as a corresponding control signal. The first level conversion signal and the second level conversion signal can be electrically opposite or the same, which is closely related to the circuit structure of the delay control unit 114.

[0066] The aforementioned level conversion process includes level conversion between high and low levels, which can include changes in level polarity or changes in the absolute value of the level itself, depending on the specific circuit structure of each level conversion unit.

[0067] When the serial clock signal is a low-level signal, the first level conversion unit 111, the second level conversion unit 112, and the delay control unit 114 form a first delay path. Since the on-resistance of the delay control unit 114 is generally small, it can usually be ignored. Because the delay time of the first delay path is less than the delay time of the third delay path, that is, the delay of the serial data signal is greater than the delay of the serial clock signal, the corresponding data holding time T is [determined]. hd Increase.

[0068] When the serial clock signal is a high-level signal (i.e., transitioning from a low-level signal to a high-level signal), the first level conversion unit 111, the second level conversion unit 112, and the first delay unit 113 form a second delay path. The path delay of the serial data signal generated by the third delay path is equal to the path delay of the serial clock signal generated by the second delay path. Since there is a transmission time difference between the serial data signal and the serial clock signal, the data setup time T is... su This means there is a transmission time difference between the serial data signal and the serial clock signal, i.e., the data setup time T. su constant.

[0069] In one embodiment, such as Figure 4 As shown, the second delay circuit 120 includes a second delay unit 121, and the delay time of the second delay unit 121 for the serial data signal is the same as the delay time of the first delay unit 113 for the serial clock signal.

[0070] In one embodiment, the first delay unit 113 and the second delay unit 121 are resistive devices, which are inductors or resistors.

[0071] In one embodiment, such as Figure 4 As shown, the second delay circuit 120 also includes a third level conversion unit 122, the output terminal of the third level conversion unit 122 being electrically connected to the input terminal of the second delay unit 121.

[0072] The third level conversion unit 122 may include multiple voltage switching devices. By setting multiple voltage switching devices, the ability of the second delay circuit 120 to remove glitches is enhanced. Furthermore, by setting multiple voltage switching devices, the switching level of the input serial data signal can be adjusted to meet actual needs.

[0073] In one embodiment, the delay control unit 114 is a switching device. When the first delay circuit 110 forms a first delay path, the delay control unit 114 is closed, and when the first delay circuit 110 forms a second delay path, the delay control unit 114 is open.

[0074] In one embodiment, such as Figure 5 As shown, the delay control unit 114 includes an NMOS switch P1, and the first level conversion unit 111 and the second level conversion unit 112 each include an odd number of voltage switching devices Q connected in sequence. The gate of the NMOS switch P1 is electrically connected to the output terminal of the first level conversion unit 111, and the output terminal of the second level conversion unit 112 is electrically connected to the source of the NMOS switch P1.

[0075] Since both the first level conversion unit 111 and the second level conversion unit 112 include an odd number of voltage inversion devices Q connected in sequence, the polarity of the input level signal and the output level signal of the first level conversion unit 111 and the second level conversion unit 112 respectively changes.

[0076] In one embodiment, such as Figure 5 As shown, the first delay unit 113 can use the first resistor R1, and the second delay unit 121 can use the second resistor R2.

[0077] Specifically, when the input serial clock signal is a low-level signal, the NMOS switch P1 is turned on, the first resistor R1 is short-circuited, and the first level conversion unit 111, the second level conversion unit 112 and the NMOS switch P1 form a first delay path. When the input serial clock signal is a high-level signal, the NMOS switch P1 is turned off, and the first level conversion unit 111, the second level conversion unit 112 and the first resistor R1 form a second delay path.

[0078] In one embodiment, such as Figure 6 As shown, the delay control unit 114 includes a PMOS switch P2, and the first level conversion unit 111 and the second level conversion unit 112 each include an even number of voltage switching devices Q connected in sequence. The gate of the PMOS switch P2 is electrically connected to the output terminal of the first level conversion unit 111, and the output terminal of the second level conversion unit 112 is electrically connected to the source of the PMOS switch P2.

[0079] Since both the first level conversion unit 111 and the second level conversion unit 112 include an even number of voltage inversion devices Q connected in sequence, the polarity of the input level signal and the output level signal corresponding to the first level conversion unit 111 and the second level conversion unit 112 does not change.

[0080] In one embodiment, such as Figure 6 As shown, the first delay unit 113 can use the first resistor R1, and the second delay unit 121 can use the second resistor R2.

[0081] Specifically, when the input serial clock signal is a low-level signal, the PMOS switch P2 is turned on, the first resistor R1 is short-circuited, and the first level conversion unit 111, the second level conversion unit 112, and the PMOS switch P2 form a second delay path. When the input serial clock signal is a high-level signal, the PMOS switch P2 is turned off, and the first level conversion unit 111, the second level conversion unit 112, and the first resistor R1 form a second delay path.

[0082] In one embodiment, such as Figure 7As shown, the delay control unit 114 includes a transmission gate structure. The first level conversion unit 111 and the second level conversion unit 112 each include an even number of voltage inversion devices Q connected in sequence. The first control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device Q at the even-numbered position in the first level conversion unit 111. The second control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device Q at the odd-numbered position in the first level conversion unit 111. The input terminal of the transmission gate structure is electrically connected to the output terminal of the second level conversion unit 112.

[0083] When the input serial clock signal is a low-level signal, the resistive device corresponding to the first delay unit 113 is short-circuited, and the transmission gate structure is in the conducting state so that the first delay circuit 110 forms the first delay path.

[0084] When the input serial clock signal is a high-level signal, the transmission gate structure is in an open state so that the first delay circuit 110 forms a second delay path.

[0085] In one embodiment, such as Figure 7 As shown, the first delay unit 113 can use the first resistor R1, and the second delay unit 121 can use the second resistor R2.

[0086] The aforementioned transmission gate structure may include CMOS transmission gate circuits.

[0087] Among them, Figures 5 to 7 In the illustrated embodiment, by providing multiple voltage switching devices Q that are electrically connected in sequence in the first level conversion unit 111 and the second level conversion unit 112, it is beneficial to enhance the ability of each delay path to remove glitches.

[0088] In one embodiment, the voltage switching device Q includes any one of an inverter, a Schmitt trigger, and a voltage selection circuit.

[0089] In one embodiment, such as Figure 8 As shown, the interface delay circuit 100 also includes:

[0090] The first filtering unit 130 is electrically connected to the output terminal of the first delay circuit 110 and is used to filter and output the level signal output by the first delay circuit 110.

[0091] The second filtering unit 140 is electrically connected to the second delay circuit 120 and is used to filter and output the level signal output by the second delay circuit 120.

[0092] In one embodiment, the first filtering unit 130 and the second filtering unit 140 employ RC filters.

[0093] When both the first filter unit 130 and the second filter unit 140 use RC filters, the filter resistors and filter capacitors corresponding to the first filter unit 130 and the second filter unit 140 are the same, so as to avoid causing additional impact on the path delay of the first filter unit 130 and the second filter unit 140 respectively. This ensures that the path delay difference between the first delay path and the third delay path, as well as the path delay difference between the second delay path and the third delay path, depends only on the path delay difference between the first delay circuit 110 and the second delay circuit 120.

[0094] By setting the first filter unit 130 and the second filter unit 140, glitches in each path can be further filtered out, reducing the risk of circuit mis-triggered in each path.

[0095] In one embodiment, the output terminals of the first filter unit 130 or the second filter unit 140 may be further configured with Schmitt triggers to flip the output level signals of each path to suit the load requirements. At the same time, it can further filter out glitches in the output level signals of each path and reduce the risk of circuit mis-triggered in each path.

[0096] In addition, such as Figure 9 As shown, an IIC bus device 10 is also provided, which is provided with the aforementioned interface delay circuit 100.

[0097] In addition, such as Figure 10 As shown, a communication system 200 includes:

[0098] The first terminal 20 is used to generate serial clock signals and serial data signals;

[0099] The IIC bus device 10 is electrically connected to the first terminal 20 and is used to receive the serial clock signal and serial data signal sent by the first terminal 20, transmit the serial clock signal on the serial control line, and transmit the serial data signal on the serial data line. The input serial clock signal is delayed by a first delay circuit to output a delayed serial clock signal. When the input serial clock signal is a low-level signal, a first delay path is formed; when the input serial clock signal is a high-level signal, a second delay path is formed.

[0100] The IIC bus device 10 is also used to perform delay processing on the input serial data signal and form a third delay path accordingly to output the delayed serial data signal. The delay time of the second delay path and the third delay path are the same, and the delay time of the first delay path is less than the delay time of the third delay path.

[0101] The second terminal 30 is electrically connected to the IIC bus device 10 and is used to receive the delayed serial clock signal and serial data signal output by the IIC bus device 10.

[0102] In IIC bus communication, when the first terminal 20 acts as the master, the second terminal 30 acts as the slave; when the first terminal 20 acts as the slave, the second terminal 30 acts as the master. The communication process is the same in both cases and will not be described in detail.

[0103] In addition, such as Figure 11 As shown, an interface delay method is also provided, applied to the IIC bus, which includes serial control lines and serial data lines. The interface delay method includes:

[0104] Step S300: Delay processing is performed on the input serial clock signal. When the serial clock signal is a low-level signal, a first delay path is formed; when the serial clock signal is a high-level signal, a second delay path is formed.

[0105] Step S310: Delay processing is performed on the input serial data signal to form a third delay path, wherein the delay time of the first delay path is less than the delay time of the third delay path, and the delay time of the second delay path is equal to the delay time of the third delay path.

[0106] The aforementioned interface delay method, on the one hand, if the input serial clock signal is a low-level signal (i.e., a transition from a high-level signal to a low-level signal), the delay time of the first delay path is less than the delay time of the third delay path, meaning the delay of the serial data signal is greater than the delay of the serial clock signal, thus increasing the corresponding data hold time. On the other hand, if the input serial clock signal is a high-level signal (i.e., a transition from a low-level signal to a high-level signal), a second delay path is formed. Since the path delay of the serial data signal generated by the third delay path is equal to the path delay of the serial clock signal generated by the second delay path, and there is a transmission time difference between the serial data signal and the serial clock signal, the data setup time is equal to the transmission time difference between the serial data signal and the serial clock signal, thus keeping the data setup time constant. While increasing the data hold time, it also keeps the data setup time constant, reducing the degree of timing logic disorder caused when the data hold time is close to or equal to 0ns. Overall, this greatly reduces timing errors on the IIC bus and improves the communication quality of the IIC bus.

[0107] The division of each unit in the interface delay circuit 100 described above is only for illustrative purposes. In other embodiments, the interface delay circuit 100 can be divided into different units as needed to complete all or part of the functions of the interface delay circuit 100.

[0108] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0109] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0110] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0111] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. An interface delay circuit, characterized by, include: A first delay circuit and a second delay circuit, wherein the first delay circuit is used to receive a serial clock signal and the second delay circuit is used to receive a serial data signal; The first delay circuit is also used to delay the input serial clock signal. When the serial clock signal is a low-level signal, a first delay path is formed; when the serial clock signal is a high-level signal, a second delay path is formed. The second delay circuit is also used to delay the input serial data signal and form a third delay path accordingly; The second delay path and the third delay path have the same delay time, and the delay time of the first delay path is less than the delay time of the third delay path; The first delay circuit includes a first level conversion unit, a second level conversion unit, and a first delay unit connected in sequence. The first delay circuit also includes a delay control unit. The control terminal of the delay control unit is electrically connected to the output terminal of the first level conversion unit, the input terminal of the delay control unit is electrically connected to the output terminal of the second level conversion unit, and the output terminal of the delay control unit is electrically connected to the output terminal of the first delay unit. The first level conversion unit performs level conversion processing on the input serial clock signal to obtain a first level conversion signal. The delay control unit controls the first delay unit according to the first level conversion signal to enable the first delay circuit to form either the first delay path or the second delay path. When the first delay circuit forms the first delay path, the delay control unit controls the first delay unit to be in a short-circuited state.

2. The interface delay circuit according to claim 1, characterized in that, The resistance of the first delay path is less than the resistance of the third delay path, and the resistance of the second delay path is equal to the resistance of the third delay path.

3. The interface delay circuit according to claim 1, characterized in that, The second delay circuit includes a second delay unit, the delay time of which for the serial data signal is the same as the delay time of the serial clock signal by the first delay unit.

4. The interface delay circuit according to claim 3, characterized in that, The first delay unit and the second delay unit are resistive devices.

5. The interface delay circuit according to claim 1, characterized in that, The delay control unit is a switching device. When the first delay circuit forms the first delay path, the delay control unit is closed. When the first delay circuit forms the second delay path, the delay control unit is open.

6. The interface delay circuit according to claim 5, characterized in that, The switching device includes an NMOS switch transistor. Both the first level conversion unit and the second level conversion unit include an odd number of voltage inversion devices that are connected in sequence. The gate of the NMOS switch transistor is electrically connected to the output terminal of the first level conversion unit, and the output terminal of the second level conversion unit is electrically connected to the source of the NMOS switch transistor.

7. The interface delay circuit according to claim 5, characterized in that, The switching device includes a PMOS switch transistor. Both the first level conversion unit and the second level conversion unit include an even number of voltage switching devices that are electrically connected in sequence. The gate of the PMOS switch transistor is electrically connected to the output terminal of the first level conversion unit, and the output terminal of the second level conversion unit is electrically connected to the source of the PMOS switch transistor.

8. The interface delay circuit according to claim 1, characterized in that, The delay control unit includes a transmission gate structure. Both the first level conversion unit and the second level conversion unit include an even number of voltage inversion devices that are electrically connected in sequence. The first control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device at the even-numbered position in the first level conversion unit. The second control terminal of the transmission gate structure is electrically connected to the output terminal of the voltage inversion device at the odd-numbered position in the first level conversion unit. The input terminal of the transmission gate structure is electrically connected to the output terminal of the second level conversion unit.

9. The interface delay circuit according to claim 8, wherein when the input serial clock signal is a low-level signal, the transmission gate structure is in a conducting state so that the first delay circuit forms the first delay path; When the input serial clock signal is a high-level signal, the transmission gate structure is in an open state so that the first delay circuit forms the second delay path.

10. The interface delay circuit according to any one of claims 6 to 9, characterized in that, The voltage switching device includes any one of an inverter, a Schmitt trigger, and a voltage selection circuit.

11. The interface delay circuit according to claim 1, characterized in that, The interface delay circuit also includes: The first filtering unit is electrically connected to the output terminal of the first delay circuit and is used to filter and output the level signal output by the first delay circuit. The second filtering unit is electrically connected to the second delay circuit and is used to filter and output the level signal output by the second delay circuit.

12. The interface delay circuit according to claim 11, characterized in that, The first filtering unit or the second filtering unit uses an RC filter.

13. An IIC bus device, characterized in that, The IIC bus device is provided with an interface delay circuit as described in any one of claims 1 to 12.

14. A communication system, characterized in that, include: The first terminal is used to generate serial clock signals and serial data signals; The IIC bus device of claim 13 is electrically connected to the first terminal and is used to receive a serial clock signal and a serial data signal sent by the first terminal, transmit the serial clock signal on the serial control line, and transmit the serial data signal on the serial data line. A first delay circuit is used to delay the input serial clock signal to output a delayed serial clock signal. When the input serial clock signal is a low-level signal, a first delay path is formed; when the input serial clock signal is a high-level signal, a second delay path is formed. The IIC bus device is also used to perform delay processing on the input serial data signal and form a third delay path to output the delayed serial data signal. The delay time of the second delay path and the third delay path are the same, and the delay time of the first delay path is less than the delay time of the third delay path. The second terminal is electrically connected to the IIC bus device and is used to receive the delayed serial clock signal and serial data signal output by the IIC bus device.

15. An interface delay method, characterized in that, The interface delay method is implemented using the interface delay circuit described in any one of claims 1 to 12, and is applied to the IIC bus, wherein the IIC bus includes a serial control line and a serial data line, and the interface delay method includes: The input serial clock signal is delayed. When the serial clock signal is a low-level signal, a first delay path is formed; when the serial clock signal is a high-level signal, a second delay path is formed. The input serial data signal is delayed, and a third delay path is formed accordingly. The delay time of the second delay path is the same as that of the third delay path, and the delay time of the first delay path is less than that of the third delay path.

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